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This paper presents a wideband low-spur phase-locked loop (PLL) in a standard 90-nm CMOS process. A simple but effective calibration technique is used to reduce the current mismatch of the charge-pump and achieve low reference spurs. The calibration is based on the successive-approximation- register (SAR) control in conjunction with the pulse-width scaling technique to enlarge the current mismatch for a better calibration resolution. The operation frequency range of the microwave PLL covers from 39.5 to 47.1 GHz. The measured phase noise and reference spurs are −92 dBc/Hz at 1-MHz offset and −57.63 dBc, respectively.

This letter presents the first RF frequency divider on glass to demonstrate the feasibility of system on display (SoD). The frequency divider is developed in 1P2M 3 mum low-temperature polycrystalline silicon (LTPS) thin-film transistor technology. The core cell of the LTPS direct injection-locked frequency divider is the single stage ring oscillator. The additional cross-coupled transistor pair increases the phase shift of the ring oscillator to meet the oscillation condition. The maximum locking range of the LTPS frequency divider is 2 MHz, and it can be operated from 120 Hz to 8 MHz with frequency tuning. Operated at 10 V, the frequency divider consumes 1.8 mW of power. The area of the frequency divider circuitry is 2.13 times 2.6 mm.

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is an emerging technology to manufacture active matrix liquid crystal displays. With the TFT's maximum frequency of oscillation fmax exceeding 3.5 GHz, it becomes feasible to develop integrated circuits (ICs) in LTPS TFT technology to facilitate system on panel or system on display. This paper investigates the LTPS TFT characteristics for developing RF ICs. The dc and ac equivalent-circuit models were developed for LTPS TFT RF integrated-circuit design. A phase-locked loop (PLL) was demonstrated using the 3-μm LTPS TFT technology. The supply voltage and power consumption of the PLL are 8.4 V and 25 mW, respectively. The operation frequency range of the TFT PLL is from 2 to 10 MHz, and the measured root-mean-square jitter is 235 ps.

Low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) is an emerging technology to manufacture active matrix liquid crystal displays (AMLCDs). With its maximum frequency of oscillation f max reaching beyond 1 GHz, it becomes feasible to develop integrated circuits in LTPS TFT technology to facilitate system on panel or system on display. This paper investigates the LTPS TFT characteristics for developing RFID tags. An equivalent circuit model was proposed for LTPS TFT RFIC design. An ASK demodulator for the RFID tag was demonstrated using 3µm LTPS TFT technology. The demodulator can operate at the carrier frequency of 13.56 MHz and the highest data rate is 100 kb/s.

This paper presents a low power wide tuning range 0.18 mum CMOS voltage-controlled oscillator. The VCO is oscillating at 1.5 times of the LO frequency to reduce the size of tank inductor. Capacitor bank switching is adopted to increase the VCO tuning range. To ensure oscillation at low frequency band, the bias current is adjusted automatically with respect to oscillation frequency. The frequency coverage of the CMOS VCO is from 675 MHz to 1275 MHz, and the tuning range is 62%. The operation supply voltage and power consumption of the VCO are 1V and 5 mW, respectively. The measured phase noise is - 98 dBc/Hz at 100 kHz offset.