Search

In this article, low-temperature Cu–Cu bonding with the Ag passivation layer was accomplished at 180 °C for 3 min without a postannealing process. The Ag passivation layer effectively prevents Cu from oxidation and assists Cu diffusion to realize low-temperature bonding. The small grain size of the Ag passivation layer controlled by sputtering working pressure is observed to improve bonding quality. Different plasma treatment parameters and bonding conditions were executed to evaluate bonding quality. The diffusion behavior of passivation bonding is investigated, and the corresponding mechanism is discussed as well. In addition, reliability assessments, including thermal cycling, high-temperature storage, and unbiased highly accelerated stress test, indicate excellent stability of this bonding structure, showing the potential for low-temperature bonding technology in 3-D integration applications.

We report on CdSe@ZnS light-emitting diodes (QLEDs) showing both high efficiency and long operational lifetime by introducing thermally cross-linkable 2,7-disubstituted fluorene-based triaryldiamine (VB-FNPD) as the hole transporting layer and 1,4,5,8,9,11-hexaazatriphenylene hexacarbonitrile (HAT-CN) as the hole injection layer. The green QLEDs achieved a maximum external quantum efficiency (EQE) of 8.0% and power efficiency (PE) of 32.1 lm W−1 with low efficiency roll-offs. More importantly, the corresponding QLED demonstrated a long lifespan in operation by simple encapsulation without desiccation. Under the initial luminance of 2000 cd m−2 and a continuous flow of constant current, the device still held luminance of 1000 cd m−2 after 50 h operation. The overall decay profile was fitted by two single exponential components, with time constants of 17.2 and ∼104 h, which is superior to that using the conventional polymer as the hole transporting layer. The thermally polymerizable hole transporting materials therefore offer an effective approach to realize both good efficiency and long-term stability in QLED.

Fan-out wafer-level packaging (FOWLP) has evolved from chip-scale packaging to be one of the enablers of heterogenous integration through chip-first or redistribution-layer (RDL)-first processes, which draw significant momentum in packaging industries to develop newer and better materials. Among all of the essential packaging materials currently being investigated, novel laser release materials are of particular interest because they are vital to the successful separation of reconstituted wafers and glass carriers. Thus, the thermal, chemical, and mechanical stability of the laser release material play a vital role for success in FOWLP integration. In this study, four laser release materials with UV-light absorbance were evaluated through experiments divided into two phases to select a champion material for chip-first and RDL-first FOWLP integration. Phase I consisted of the collection of material properties and characteristics including light transmittance, interaction with laser energy, thermal stability, adhesion, and melt rheology to determine compatibility with RDL-first and chip-first processes, respectively. In Phase II, all candidate laser release materials were introduced to a short-loop evaluation that started with a laser release material coating on 300-mm glass carrier with a coefficient of thermal extension (CTE) of 8 ppm/°C, followed by 50-nm titanium deposition, 100-nm copper deposition, and dielectric material coating before encapsulation with epoxy molding compound. Multiple 355-nm laser powers that created different diameters of effective ablation region inside the crater, were used to determine the sensitivity of each candidate material. Meanwhile, chips sized, were picked and placed on coated glass carriers with candidate laser release materials to evaluate the compatibility with the chip-first process. Finally, design of a die bonding experiment was used to summarize the optimal conditions of a laser release material, proved compatible with RDL-first in advance, for a chip-first process. Through the comprehensive material evaluation discussed in this study, optimal laser release materials for the RDL-first and chip-first processes are identified. Of particular interest are materials that possess both laser release properties and good adhesion, since their use in die bonding applications will enhance throughput and lower the cost of ownership for FOWLP.

Continuous scaling down NAND flash memory toward below 1Xnm node generation will result in serious floating gate (FG) poly depletion and significantly impact the cell reliability performance. In this study, the FG implantation before inter-poly-dielectric deposition was proposed. We have successfully explored the methods to minimize the FG implanted damage issue and hence the void-free control gate (CG) can be achieved after the CG poly-Si fill-in. After optimizing the FG implanted processes, the cell reliabilities on 1Xnm NAND flash device were verified. The FG poly depletion can be effectively reduced by the additional FG dopant, which results in the significant improvement on the natural threshold-voltage (Vt) distribution width, the program noise, and the program/erase Vt degradation. Moreover, there is no degradation on non-cycle data retention when adding the FG implantation, which suggests no extra FG dopant penetrated into tunnel oxide as the trap sites to enhance the trap-assisted tunneling leakage under high temperature baking.

This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5- $\mu \text{m}$ -diameter/50- $\mu \text{m}$ -length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12- $\mu \text{m}$ diameter are bonded using three step temperature bonding profile. Further stacked DRAM/Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.

Aquatic insects living in fast-flowing streams have developed various types of attachment systems to resist being carried away by strong currents. Combinations of various attachment devices offer aquatic insects advantages in underwater adhesion on substrates with different surface properties. In this study, the net-winged midge (Blepharicera sp.) larvae were investigated to understand micro-/nano-structural attachment mechanisms. The hierarchical structure of insect adhesive surfaces was characterized using Optical Microscopy (OM), Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM). Centrifugal measurements were also conducted to measure the critical rotational velocity at which the larvae of Blepharicera sp. can adhere to substrates with varying roughness. Commercial suckers require smooth substrate surface to maintain a pressure that is lower than the surrounding pressure for adhesion under the sucker cup while the suckers of net-winged midge larvae possess hierarchical micro-/nano-structures, which attach closely to rough surfaces underwater. Furthermore, the functions of microstructures observed on the sucker, including wrinkled surface, inward setae, outer fibers, and nick were explored and may contribute to underwater adhesion. The aligned C-shaped suckers can attach and detach effectively by closing or opening the gap. The unique microstructure and adhesion capability of such suckers could shed light on the design and synthesis of novel bio-inspired devices for reversible underwater adhesion.

Popcorn nanoparticles (pop-NPs) consisting of a Pd/Cu alloy were synthesized using a seed-mediated growth method. The Cu and Pd atoms were co-deposited on a cubic Pd seed to reduce the energy of fault stacking. The same synthesis method with a reduced volume of the Cu(II) salt leads to Pd/Cu alloy nanoparticles with branches (br-NPs). Large Pd nanocubes (Pd NCs) were prepared via epitaxial deposition and using tetrachloropalladate (PdCl42−) only. The high-resolution TEM analysis results show the pop-NPs and br-NPs to be single crystals with $$\left(0\overline{2}1\right)$$ and $$\left(02\overline{2}\right)$$ planes, respectively. The results of X-ray photoelectron spectroscopy and cyclic voltammetry measurements corroborated that Pd is enriched on both surfaces. The materials were placed on a glassy carbon electrode to obtain a differential pulse voltammetric sensor for dopamine (DA). The electrochemical sensitivities are (a) 1.55 μA μM−1 cm−2 for the Pd/Cu pop-NP sensor in its linear range (15–300 μM), (b) 1.17 μA μM−1 cm−2 for the br-NP sensor in the linear range (15–200 μM), and (c) 0.97 μA μM−1 cm−2 for the Pd NC sensor in its linear range (15–100 μM). The best working potentials are near 0.10 V (vs. SCE) for all three sensors. The pop-NP-based sensor performs particularly well due to it selectivity over ascorbic and uric acid.

In the development of semiconductor packaging technology from planar to three-dimensional vertical integration, chip interconnection density has increased, and the distance of signal transmission has dropped to improve overall device performance. In this research, an architecture composed of through‑silicon via (TSV) and solder microbump (μbump) is utilized to assemble an ultra thin-type chip into a three-dimensional integrated circuit (3D-IC) package. To explore the influence of residual thermomechanical residual stress induced during the manufacture of the 3D-IC package on the subsequent reliability of the thermal cycling test (TCT), this study establishes a nonlinear simulation methodology for investigating the coupling effect of the manufacturing process and the TCT. The plastic and creep behaviors of the solder μbump are considered in the finite element modeling. The concerned geometric dimensions and underfill materials are also parametrically analyzed. Furthermore, the inelastic strain accumulated in the crucial SnAg solder μbump is examined. Results indicate that the residual strain in the manufacturing process causes an obvious packaging warpage and converges at the subsequent TCT stage. The creep of the solder μbump increases up to 50% in thermal cycling, thereby highlighting the importance of considering the creep model. Moreover, the parameterization of chip thickness can minimize the inelastic strain increment of the solder μbump, and the low Young's modulus of the underfill materials exerts a significant effect on the warpage of the packaging module and the stress compliance of the μbumps.

With increasing demand for mobile devices to be lighter and thinner and consume less power while operating at high speed and high bandwidth, many equipment suppliers and assembly participants have invested great efforts to achieve fine-line fan-out wafer-level packaging (FOWLP). However, the inherent warp of reconstituted wafers, which can contribute to poor die placement accuracy and/or delamination at the interface of the build-up layer and carrier, remains a major challenge. In this study, the interactions among laser release layer, glass carrier, and build-up layer were evaluated for optimization of redistribution layer (RDL)–first FOWLP as a foundation to move toward fine-line FOWLP. In this study, a series of experiments incorporating glass carrier, laser release layer, and build-up layers were carried out to determine the optimal setup for RDL-first FOWLP. First, glass carriers (300 mm × 300 mm × 0.7 mm) with coefficients of thermal expansion of 3 and 8 ppm/°C were treated with 150-nm laser release layers. After deposition of 0.1 μm of sacrificial material on the glass carrier, 8-μm build-up layers were coated and patterned by lithography to electroplate Cu interconnections with a density of approximately 10% of the surface area. Subsequent to die attachment, molding compound was applied on top to form a 200-μm protective overcoat. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 308-nm laser to complete the design of experiments (DOE). An experiment to study the correlation of glass carrier, laser release layer, build-up layers, and molding compound in RDL-first FOWLP processes is discussed to address full process integration on 300-mm glass substrates. The combination of glass carrier, laser release layer, build-up layer, and molding compound will pave the way for realizing cost-effective RDL-first FOWLP on panel-size substrates.

Fan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 µm thick) with coefficient of thermal expansion of 8 ppm/oC were treated by selected laser release layers. After deposition of 0.05-µm Ti/0.15 µm Cu on the glass carrier, passivation of around 8 µm was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-µm reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.

Three dimensional integrated circuit technology has been recently received much interests because it could meet the requirements such as small form factor, high performance, low cost and heterogeneous integration in system-in-package technologies for next generation electronics. For high performance 3D chip stacking, high density interconnections are essential. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. In this study, two methods of fluxless chip-on-chip bonding process with 30μm pitch lead free solder micro bumps interconnection were demonstrated and the reliability of micro joints was also evaluated. The plasma treatment and the formic acid treatment were used to remove the tin oxidation layer upon the surface of solder micro bumps. The assembly of the chip-on-chip test vehicle with a micro bumps diameter of 18μm and a pitch of 30μm was conducted. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and the silicon carrier. A solder micro bump structure of Cu/SnAg having a thickness of 7μm/15μm was fabricated in silicon chip and the silicon carrier consisted of Cu under bump metallization (UBM) with a thickness of 5μm. During bonding process, the micro joints were formed at pre-bonding and reflowed in reflow oven with a peak temperature of 250 °C. Then, the die shear test was used to check the solder micro joints bonding strength between the silicon chip and carrier by two methods of fluxless process. After bonding process, the microgaps were then filled by a capillary underfill and cured at 165 °C for 2 hours. Reliability tests of temperature cycling test (TCT) and high temperature storage (HTS) were selected to assess the effect of the fluxless bonding process on the reliability of solder micro joints interconnections.

As requirements increase for mobile devices to be lighter and thinner and to operate at high speed and high bandwidth, innovations in wafer-level packaging have evolved to 3-D structures, such as package-on-package (PoP), fan-out integration, and through-silicon-via (TSV) interposer architectures. However, wafer-level packaging is still considered to be costly and slow in throughput due to wafer size limitations. In this study, temporary bonding and debonding processes using mechanical or laser release technologies were applied in the fabrication process of an integrated embedded glass interposer as a foundation for 3-D integrated circuit (IC) packaging on panel-level packaging. Glass interposers having dimensions of 10 mm × 10 mm and a thickness of 120 μm were fabricated. The interposers had through-glass vias (TGVs) 25 μm in diameter and 3000 I/O pads of copper under-bump metallization (UBM) and were designed as a nearly full-array type. The interposers were supported by a temporary bonding material on silicon or glass wafers and embedded by built-up dielectric material on which fan-out redistribution circuit layers were deposited. For forming the pattern of the redistribution layer, a UV laser was used to form 75-μm-diameter blind vias, and conductive interconnections were made by a semi-additive process (SAP) using photolithography and electrolytic copper. The process of building up layers from the glass interposer to form an embedded fan-out interposer can eliminate a joining process required by traditional 2.5-D IC integration. Finally, the embedded fan-out carrier is separated from the glass or silicon wafer through a laser debonding process. An experiment to study the correlation of bonding material and release material with built-up lamination in backside processes will be discussed in this paper to address full process integration on panel-size substrates. The combination of temporary bonding technology with mechanical or laser release technologies will pave the way for realizing cost-effective 3-D IC packaging on panel-level substrates.

Three-dimensional integrated circuit (3D-IC) packaging has attracted considerable research interest because it allows the integration of heterogeneous functions among stacked chips. The thermal mismatch stresses induced by thermal cycling loads in the interconnects that are composed of a through silicon via (TSV) and microbumps are a serious concern, and thus, a thinner stacked die is required. To shrink the foregoing thickness to less than 10 μm, a novel assembly approach involving the use of pre-stuffed molding material at the wafer-level grinding process is proposed in this study. The assembly results are performed by using a chip-on-wafer module. In addition, the parametric estimation of the induced stress/strain resulting from the geometries of fine-pitch TSVs under temperature cycling loads is also performed by using non-linear finite element analysis. In thick silicon chips, the capability of a stress-release mechanism for the TSV and microbumps depends on the adoption of underfill material and the proper selection of its elastic modulus. By contrast, the non-linear stress/strain at all the interconnects of a 3D-IC package with extremely thin stacked chips decreases due to the excellent flexibility provided by the silicon chip. The results of this study are valuable to the configuration design and demonstrate the feasibility of 3D-IC packages with thin stacked chips assembled through the proposed assembly approach.

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.

Copper wires are increasingly used to replace gold wires in wire-bonding technology owing to their better electrical properties and lower cost. However, not many studies have been conducted on electromigration-induced failure of Cu wedge bonds on Al metallization. In this study, we investigated the failure mechanism of Cu-Al wedge bonds under high current stressing from 4 × 104 A/cm2 to 1 × 105 A/cm2 at ambient temperature of 175°C. The resistance evolution of samples during current stressing and the microstructure of the joint interface between the Cu wire and Al-Si bond pad were examined. The results showed that abnormal crack formation accompanying significant intermetallic compound growth was observed at the second joint of the samples, regardless of the direction of electric current for both current densities of 4 × 104 A/cm2 and 8 × 104 A/cm2. We propose that this abnormal crack formation at the second joint is mainly due to the higher temperature induced by the greater Joule heating at the second joint for the same current stressing, because of its smaller bonded area compared with the first joint. The corresponding fluxes induced by the electric current and chemical potential difference between Cu and Al were calculated and compared to explain the failure mechanism. For current density of 1 × 105 A/cm2, the Cu wire melted within 0.5 h owing to serious Joule heating.

Reduced the wafer thickness has high density arrays of through silicon via (TSV). It has significantly required in the assembly technology of three-dimensional integrated circuits (3D-ICs) packages. Find a good approach during the processes. It can decrease the damage risk for stacked chips in chip thinning processes and to enhance the micro-bumps (p-bump) mechanical reliability in this study. A chip-to-wafer (C2W) module filled with a suitable filling the gap at the bottom to a combination of stacked chips and use initialization between the molding material is considered. Compared with traditional technology and methods, significant change in the manufacturing process C2W procedure is filled into the bottom during filling, in order to achieve a pre-lead type material after the step of thinning the chip. The main advantage of the above embodiment is to reduce the thickness of the thinned mechanical load applied to the adjacent molded material, while a highly reduced thickness of the stacked chips to 30 micrometers, the back support is trying to achieve stacked silicon chips. By using the suggested method another advantage is the productivity potential because subsequent packaging process can be greatly simplified.

In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation, were developed and integrated to perform well. The BT substrate design and PCB for electrical characterization of reliability tests are included as well. The results indicate that the device with the glass interposer can be integrated and there is also data showing the feasibility of the glass interposer for electronics applications.

The resonance phenomenon is suppressed by adjusting the damping of the comb accelerometer structure to widen the frequency bandwidth of the capacitive accelerometer. The capacitive accelerometer with asymmetrical combs, fabricated with DRIE and anodic bonding, is presented. The damping category of the accelerometer is introduced, in which the squeeze-film damping coefficient and the damping ratio factor are detailed. The damping ratio factor of the accelerometer, measured by a vibration method, is 0.17. The damping ratio factor of the optimized structure is calculated of 0.15 to 0.18 with the change of experiential modulus C from 25 to 30, theoretically.

In this paper, we investigated the assembly characterization for reliability test. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, glass thinning and backside RDL formation, were developed and integrated to perform well. The BT substrate design and PCB for electrical characterization of reliability tests are included as well. The results indicate that the device with the glass interposer can be integrated and there is also data showing the feasibility of the glass interposer for electronics applications.

To overcome the severe challenges of achieving an extra-thin thickness down to 10 μm for chip stacking of 3D-IC module such as the mechanical damages appear at chip grinding, subsequent steps of wafer handling, and robust assembly, a novel pre-molding technology applied to assembled stacked module prior to chip thinning procedure is presented in this study. Packaging vehicle is fabricated to demonstrate the feasibility of proposed approach. Moreover, failure estimation and mechanical reliability are also implemented by using a 3D nonlinear finite element analysis.

In 3D integration, die stacking together with underfilling by capillary-type underfill are the principal processes within whole conventional assembly process. How to integrate and shorten the total process steps during assembly and increase the die-stacking yield especially for thin die stack to improve the throughput that can meet the requirement from industry will be a crucial issue. In this investigation, we proposed the high throughput adhesive bonding scheme by using wafer-level underfill material for the die-to-interposer stacking with 30µm-pitch micro interconnections. The reliability characterization of the die-to-interposer stack by such bonding scheme was implemented and confirmed.

Optimization of the polishing and cleaning steps during the copper chemical mechanical polishing (Cu CMP) process can be accomplished by modification of Cu trench profile, control of Cu surface roughness, and reduction of residual Cu ions on the ultra-low k (ULK) surface. For the tuning of the polishing process, the optimized profile will improve the sheet resistance (Rs) and TDDB (time-dependent dielectric breakdown). The cleaning effectiveness would be influenced by the clean chemicals and clean process. The correlation between cleaning effectiveness and voltage ramp dielectric breakdown (VRDB) was investigated. In addition, inductively coupled plasma mass spectrometry (ICP-MS) was found to be a useful tool for the evaluation of post cleaning performance.

Sea shells are composed of calcium carbonate crystals interleaved with layers of viscoelastic proteins, having dense, tailored structures that yield excellent mechanical properties. Shells such as conch (Strombus gigas), giant clam (Tridacna gigas), and red abalone (Haliotis rufescens) have hierarchical architectures that differ depending on growth requirements and shell formation of the particular mollusk. Mechanical tests have been carried out on these shells for a comparison of strength with respect to the microstructural architecture and sample orientation. The mechanical response is found to vary significantly from specimen to specimen and requires the application of Weibull statistics in order to be quantitatively evaluated. The complex micro-laminate structure of these biocomposite materials is characterized and related to their mechanical properties. The red abalone has the highest compressive (233–540 MPa) and flexure strengths of the three shells. The giant clam has the lowest strength (87–123 MPa) and the conch has an intermediate value (166–218 MPa) in compression. The high compressive strength observed in the abalone is attributed to an optimization of microstructural architecture in the form of 2-D laminates, enhancing the fracture toughness of this shell material and enabling higher stresses to develop before fracture. D 2005 Elsevier B.V. All rights reserved.

In this paper, the p-type Si/SiGe metal-oxide-semiconductor field-effect transistor (PMOSFET) utilizing a strain-graded-Si 1− x Ge x well, has been successfully fabricated by ultra-high-vacuum chemical vapor deposition (UHVCVD). Due to the inverse grading Ge composition in conjunction with higher valence-band discontinuity at Si 0.7 Ge 0.3 /Si-buffer interface, most of carriers are populated at the bottom of SiGe-conducting channel, which undergo higher mobility. It is found that by grading Ge fraction in the channel, the devices exhibit the excellent property not only of higher mobility but also enhancement in extrinsic transconductance and linear operation range over a wider dynamic range than those of devices with uniform Ge profile for the same integrated Ge dose in SiGe conducting well.

The random telegraph noise (RTN) characteristics of 28-nm pMOSFETs with tip-shaped SiGe source/drain have been investigated. RTN analysis found that strained devices undergo higher compressive strain; the trap position from the Si/SiO2 interface is reduced, because of the closer trap energy level near the valence band. Although tip-shaped SiGe process induces higher oxide trap density, the trap position corresponding to the tunneling attenuation length (λ) may result in lower 1/f noise level in tip-shaped SiGe S/D devices as compared with that of control devices.

Three-dimensional integrated circuits (3D-ICs) packaging has attracted a lots of attentions due to it has advantages of integrating heterogeneous functions among stacked chips. The thermal mismatch stresses with regard to interconnects composed through silicon via (TSV) and microbump induced by thermal cycling loads becomes a serious concern while a thinner stacked die thickness is required. To shrink the foregoing thickness less than 10 μm, a novel assembly approach assisted with the use of pre-stuffed molding material at the wafer-level grinding process is proposed in this research. In addition, parametric estimations of the induced stress/strain from the geometries of fine-pitch TSVs under temperature cycling loads is also performed by using a non-linear finite element analysis. As silicon chip is thick, the capability of stress released mechanism for the TSV and microbump is found to depend upon the adoption of underfill material with the proper selection of its elastic modulus. By contrast, the non-linear stress/strain at the entire interconnects of 3D-ICs package with extreme thin stacked chips reduce since the excellent flexibility provided by silicon chip is elaborated. The examined results presented in this study are valuable to the configuration designs and the feasibility of 3D-ICs package with thin stacked chips utilized the proposed assembly approach.

Cryogenic ion implantation process has received increasing attention because it provides better amorphization performance and less end-of-range defects. In this study, 20nm-thick CoSi 2 film was formed on cryogenic carbon ion-implanted poly-Si substrate and the agglomeration behavior of CoSi 2 film after high temperature RTA annealing was investigated by four-point-probe resistivity measurement. Results suggest that the thermal stability of CoSi 2 film is greatly improved when cryogenic carbon pre-amorphization implant (PAI) with energy of 15keV and dose more than or equal to 2E15 ions/cm2 was performed on poly-Si substrate before CoSi 2 formation. The suppression of agglomeration of CoSi 2 film during 950°C RTA annealing is likely due to the homogeneous distribution of fine-grained CoSi 2 film formed on fully amorphized poly-Si substrate. In addition, it was found that the microstructure of underlying poly-Si of stacked poly-Si substrate strongly affects the agglomeration behavior of CoSi 2 film. The precise control of amorphization depth by adjusting carbon PAI energy can lead to improvement in CoSi 2 thermal stability.

Continuous technology scaling on NAND FLASH results in serious FG poly depletion issue due to Phosphorous out-gassing and degrades the cell reliability. Phosphorous implantation (P-IMP) into in-situ dope poly can improve poly depletion issue, but the FG bending and FG height loss were observed. In this study, we have successfully explored the methods to minimize FG bending and FG height loss issue by adding plasma oxide (PO) as screen oxide and/or changing the rotation times and temperature control of ion implantation. Finally, P-IMP on FG was validated at 36nm NAND FLASH device and shows significantly improvement on FG depletion and cell reliability.

For USJ engineering, cryogenic implantation is proposed for the reduction of dopant TED effect (i.e., Xj reduction) and the reduction of EOR defect formation. (i.e., less dopant deactivation)1 However, condensation defects are formed during the wafer warm up period due to the temperature of the cold wafer surface, and this impacts the device electrical performance. In this study, we use a heater lamp and post N 2 purge function to improve the lower wafer temperature issue after the cryogenic implantation process. In order to minimize the wafer to wafer temperature difference, we can adjust the wafer cassette elevator position and post N 2 purge time. Turn-on heater lamp 8min with elevator position at slot14 and post N 2 purge 40min, we can improve the wafer surface temperature to ∼23°C with wafer to wafer temperature range ∼0.6°C. The wafer surface temperature after the heater lamp function is close to room temperature implantation and it would be benefit to suppress the surface condensation defects formation.

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30µm or less than 30µm. Sheet-type molding compound (SMC) was used to achieve the assembly of ultra-thin chip stacking module. The feasibility of this novel assembly was demonstrated and some process issues were also discussed in this investigation.

In this research, a backside illuminated CMOS image sensor (BSI-CIS) without through-silicon via and TSV based Si interposer are developed with thin wafer handling technology. The BSI-CIS wafer is implemented front-side processes then temporary bonded on a Si carrier by using ZoneBOND™ technology. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5um, which is visible light transparent to meet the back-side illumination requirement. TSV fabrication, void-free TSV filling, bumping, wafer thinning, thin wafer handling and backside RDL formation are well developed and 30um TSV, 60um thin wafer have been successfully integrated to Si interposer. Cu/Sn bumps with 50µm size are formed with the bump height uniformity less than 5% in wafer level. The wafer-level package of BSI-CIS and TSV based Si interposer have been successfully developed and demonstrated, the characterization results of three layer stacked module is also disclosed in the paper.

A working p-type SiGe double-quantum-well metal–oxide–semiconductor field effect transistor (DQW-pMOSFETs) has been fabricated and characterized. The upper quantum well with 15%-Ge acts as an induced-carrier buffer to slow holes into the Si surface channel and increases the number of high-mobility holes in the 30%-Ge well at the bottom under high gate voltage by improving carrier confinement. DQW devices with a thinner Si-spacer layer between the two SiGe quantum wells exhibit an improved effective hole mobility and wider gate voltage swings but also reduced 1/ f noise levels than Si-controlled pMOSFETs. The DQW has an enhanced carrier confinement compared to a single quantum-well (SQW) device; however, the degradation of mobility and transconductance observed in a sample DQW indicates that this poor transport mechanism may result from an additional hole scattering effect at the Si/SiGe interface.

We developed a novel CMOS architecture that uses mechanical tensile stress, induced by the Si nitride-capping layer, together with the pseudomorphic compressive stress in SiGe layer to improve the drive current of both n- and pMOSFETs simultaneously. The unique advantage of this process flow is that on the same wafer, individual MOSFET performance can be adjusted independently to their optimum due to the separation process for two type devices. It is found that n- and pMOSFETs in the novel CMOS architecture behaved better in performance, not only a higher drain-to-source saturation current but also higher transconductance with wide gate voltage swing, than the Si-control devices, thus making this flow to show a great flexibility for developing next-generation high-performance CMOS.

Through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed and there are many challenges for processing. For process, the major differences between Glass and Si interposer are method for via formation and isolation. The test vehicle for Glass interposer is successfully processed. Glass material is composed with SiOx, it is good isolation for electrical current. The polymer-based PBO is used for passivation. For structure of glass interposer, there is one RDL on the front-side and backside, respectively. The other structure is 2 RDL on the front-side and one RDL one the backside. The CD of through glass via is 30 μm, it is formed by Corning Co. Cu overburden and Ti barrier are removed by wet etching process. For top RDL (line-width = 20μm), Cu plating process with seed layer (Ti/Cu) wet-etching process is applied. The PBO material is used for passivation, the process temperature is blow 200°C. Top UBM (15μm in diameter; 4μm/5μm-thick Cu/Sn) is formed with a top passivation opening (15μm). The structure is analyzed and demonstrated by SEM analysis. All the results indicate that the glass interposer with polymer passivation can be preceded and the cost for process is cheaper than Si interposer.

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.

Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip stacking, high density interconnections are required in high-performance electronic products. Though the bumping process used could be either electroplating or electroless plating for fine pitch solder micro bumps, its process effect on the reliability performances of micro joints still needs to be clarified from the microstructural point of view, especially for the fine pitch solder micro bump interconnections. In this study, we discussed the effect of Ni/Au metal finishing fabricated by electro- and electroless plating on the reliability properties of 30μm-pitch lead-free solder micro interconnections. Palladium layer was chosen to evaluate its influence on the reliability response of fine-pitch solder micro joints with electroless Ni/Au surface finishing. The chip-to-chip test vehicle having more than 3000 solder micro bumps with a bump pitch of 30μm was used in this study. Two types of metal finishing, electroplating Ni/Au and electroless plating Ni/Pd/Au, were chosen and fabricated on the silicon carrier. In silicon carrier, the thickness of Ni layer was 2~3 μm while that of electroplating and electroless plating Au layer was 0.5μm and 0.02μm respectively. The thickness of Pd layer within the electroless Ni/Pd/Au structure was 0.05~0.1μm. The silicon chip with a solder micro bump structure of Cu/Ni/SnAg having a thickness of 5μm/3μm/5μm was used for C2C bonding. We adopted the fluxless thermocompression process for both types of micro joints and then the chip stack was assembled by capillary-type underfill. Temperature cycling test (TCT) and electromigration test (EM) were conducted to assess the effect of metal finishing on the reliability properties of those solder micro bump interconnections. The reliability results revealed that the thickness of Au layer would apparently influence the microstructure evolution within the solder micro bump interconnection after bonding process though the micro joints with thick Au layer could pass the 1000 cycles TCT. The micro joints with complicated interface reaction resulted from the thicker Au layer might lead a negative effect on the long-term reliability properties while the Pd layer would enhance the wetting ability of solder micro bump during joining. The results of EM reliability test displayed that both types of the micro joints had excellent electromigration resistance under the testing condition of 0.08A/150°C. The activated IMC growth within the micro joint during EM testing was the major reason for this superior property. This investigated completely presented the effect of metal finishing by electro- and electroless bumping processes on the reliability properties of fine pitch solder micro bump joints.

In the evolution of IC package, the primary trend is regarded to be the upgrading from planar 2D integration to 3D stacking. But before stepping into 3D IC category, a transitional generation called 2.5D is proposed. Due to the extremely fine pitch of modern IC, the IC substrate is difficult to match due to the incomparable line width/space. Therefore, a silicon interposer is introduced to fulfill the requirement of circuit re-distribution. In this paper, a package structure contains Si interposer to meet the demand of smaller and thinner form factor is proposed. The interposer is embedded into substrate by means of dielectric material lamination rather than solders joining and flip chip bonding. The embedded packaging technology is an integration of embedding active and passive components in built-up substrates and printed circuit boards (PCB). It can also be regarded as a process integration of PCB substrate and silicon substrate that raised the package density and miniaturized the package volume. In this investigation, an 8 inch thinned wafer was used as the test vehicle. Through silicon vias (TSVs) for interconnection could be produced either by deep reactive ion etching (DRIE) at wafer-level or by laser drilling at chiplevel. Meanwhile, Si chips were interconnected to the Si interposer to form an integrated 2.5D module. Afterwards, the 2.5D module was embedded by laminating a dielectric layer on both side of the module. Subsequently, the UV laser was used to form blind vias on the dielectric layer, and the chemical processes including de-smear, seed layer coating, Cu plating were applied to form the circuits or the BGA pads on the top or the bottom surface of build-up layer to connect the circuits of the 2.5D module. After circuit forming, the dielectric layer was fully cured at 170°C to enhance the adhesion between the Cu trace and the dielectric material. With this architecture, the thickness of interposer in a 2.5D-SiP could be subtracted, and the electrical performance should be improved because of a shorter signal transmission route. The feasibility of the packaging structure has been verified. The reliability is assessing by preconditioning, and the results were also discussed here.

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

Wavelength conversion with a high efficiency and wide conversion range can easily be realized by applying an assist beam of short wavelength to a dual-pumped semiconductor optical amplifier (SOA). Experimental results reveal that an assist beam can improve the conversion efficiency and signal-to-background ratio by up to 8.5 and 4.1 dB, respectively, when the SOA is biased at the current that makes the SOA transparent to the assist beam. The efficiency can exceed -10 dB over an 80-nm wavelength conversion range using a 23-dB gain SOA. The assist beam increases the system power budget because it simultaneously improves the conversion efficiency and reduces the receiver power penalty. The power penalties for up-converting and down-converting 10-Gb/s signals to 25 nm of wavelength range are less than 0.5 and 2.5 dB, respectively.

Heavy metal ions arising from human activities are retained strongly in water; therefore public water supplies must be monitored regularly to ensure the timely detection of potential problems. A phosphate-modified dendrimer film was investigated on a quartz crystal microbalance (QCM) for sensing metal ions in water at room temperature in this study. The chemical structures and sensing properties were characterized by Fourier transform infrared spectroscopy and QCM measurement, respectively. This phosphate-modified dendrimer sensor can directly detect metal ions in aqueous solutions. This novel sensor was evaluated for its capacity to sense various metal ions. The sensor exhibited a higher sensitivity level and shorter response time to copper(II) ions than other sensors. The linear detection range of the prepared QCM based on the phosphate-modified dendrimer was 0.0001 ~ 1 μM Cu(II) ions (R2 = 0.98). The detection properties, including sensitivity, response time, selectivity, reusability, maximum adsorption capacity, and adsorption equilibrium constants, were also investigated.

In this paper, we report, for the first time, the fabrication and characterization of p-type doped-channel Si/SiGe field-effect transistors (DCFETs) using uniformly doping and delta doping in the SiGe conducting channel. For the same device parameters and process conditions, the δ-DCFET is shown having much smaller leakage current and larger current drivability than uniformly doped-channel FET (u-DCFET). This is because the additional V-shaped potential formed well by the δ-doped layer in the SiGe layer offers an excellent channel hole confinement and the larger forward turn-on voltage promises a linear operation over a wider dynamic range than that of u-DCFET.

3DIC integration has been well know as the next generation of semiconductor technology with the advantages of small form factor, high performance, low power consumption, high density integration, etc. The stacked assembly is one of the key enabling technologies to perform 3D integration. One popular approach to achieve intrinsic metal interconnect is stacked bonding by lead-free solder bumps. With the demand of high performance and high density applications, the development of fine pitch micro-bumps becomes more and more important in order to meet the requirements of low profile, light weight, and high pin counts for 3DIC integration applications There are three major important steps in assembly technologies for 3DIC integration: 1) micro-bumping wafer; 2) fabricating the TSV (through-silicon via)/RDL (redistribution layer)/IPD (integrated passive device) interposer/chip wafer with UBMs on its top-side and either ordinary solder bumps or UBMs at its bottom-side (temporary bonding and de-bonding the wafer to a supporting wafer is usually required); and 3) dicing the wafer into individual chip and bond it to the interposer/chip wafer (C2W) bonding or wafer to wafer (W2W) bonding. In this study, ultra fine pitch In lead-free solder micro-bumps are investigated. Emphasis is placed on wafer bumping, assembly, and reliability of micro-bumps for 3DIC integration applications. In this work, the optimum bonding condition is determined and the cross sections are characterized with SEM.