1. Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device
- Author
-
Yajuan Su, Qing-Chun Zhang, Ying-Fei Wang, Rui Chen, Tianyang Gai, Libin Zhang, Ping Li, Xiaojing Su, Lisong Dong, Yayi Wei, and Tian Chun Ye
- Subjects
010302 applied physics ,Materials science ,Dependency (UML) ,stress memorization technique ,business.industry ,Al diffusion ,Process (computing) ,Layout proximity effects ,01 natural sciences ,TK1-9971 ,Electronic, Optical and Magnetic Materials ,Stress (mechanics) ,Logic gate ,0103 physical sciences ,Trench ,MOSFET ,Hardware_INTEGRATEDCIRCUITS ,Optoelectronics ,Electrical engineering. Electronics. Nuclear engineering ,Electrical and Electronic Engineering ,business ,Metal gate ,high-k HfO₂ ,NMOS logic ,Biotechnology - Abstract
For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and length of diffusion effect. Based on the oxygen diffusion mechanism analysis of layout proximity effects in high-k/Metal gate NMOS device, an optimized process is proposed to suppress the layout dependency. The experiment result indicates that modified low temperature stress memorization technique process can suppress layout dependency efficiently without performance degradation of the devices.
- Published
- 2021