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Aluminum scandium nitride (Al1−xScxN/AlScN) (x = 0.32) Lamb wave resonators (LWR) have been fabricated and tested to demonstrate electromechanical coupling coefficients (kt2) in excess of 10%. The resonators exhibited an average kt2 and unloaded quality factor (Qu) of 10.28% and 711, respectively, when calculated from the measured data. Applying the Butterworth Van-Dyke (BVD) model to the measured data enabled the extraction of the resonator's lumped element parameters to calculate the motional quality factor (Qm), which neglects the contributions of the electrical traces. For the best measured resonator response, results from the BVD model showed a Qm of 1184 and a resulting figure-of-merit (FOM = K2 · Qm) of 100. Comparing the response of similar AlScN and AlN resonators shows that the AlScN LWR has a significantly lower motional resistance (Rm), suggesting that AlScN has a strong potential for use in piezoelectric microelectromechanical oscillators.

To transition aluminum nitride (AlN) microresonator filters into a manufacturable technology, accurate control of the resonator frequency across a wafer is required. This paper describes a postfabrication rapid thermal anneal approach to trim resonator frequency over 27 000 ppm with an accuracy of 500 ppm. Measurements made on 22.4 MHz resonators indicate that the effect of annealing on the resonators saturates in 5 min and upshift the resonator frequency super linearly with temperature. We replicate the frequency trimming effect on hermetically sealed wafer level packaged devices to reduce the across-wafer frequency distribution from 22 000 to 4000 ppm. We confirm that this postannealing technique is permanent by temperature cycling the resonators from 50 $^{\circ}{\rm C}$ to 125 $^{\circ}{\rm C}$ . This technique provides a method to trim AlN microresonator frequency overcoming effects such as thin film variations, which are inherent to microsystems fabrication. $\hfill{[2013\hbox{--}0091]}$

Al–0.5%Cu films patterned with an anodization mask of barrier Al2O3 are micromachined by porous-type anodization followed by chemical dissolution of porous Al2O3. Electrochemical micromachining results in well-defined metallic pillars separated by micro-grooves. The trapezoidal shape of the pillars is due to the lateral pore propagation under the anodization mask. Regardless of undercutting, porous-type anodization shows a higher degree of anisotropy than mostly isotropic wet chemical etching. The vertical growth of pores is accelerated with respect to the lateral propagation of pores by increasing the voltage of porous-type anodization. Consequently, the lateral pore propagation is minimized and for ~3 µm thick Al–0.5%Cu films the etch factor increases from 2.6 to 4.3 when the voltage is increased from 20 V to 60 V. Comparing the results obtained with the micromachining of ~3 µm and ~10 µm thick films at the same voltage, the etch factor decreases as the depth of micro-grooves increases. The etch factor depends on the distribution of secondary current density at the pattern scale during porous-type anodization, which is defined by the anodization mask coverage. A higher degree of anisotropy of porous-type anodization (in comparison to wet chemical etching) allows for more accurate shape control of three-dimensional metallic microstructures.

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

We have developed a complete process module for fabricating front end of line (FEOL) through silicon vias (TSVs). In this paper we describe the integration, which relies on using thermally deposited silicon as a sacrificial material to fill the TSV during FEOL processing, followed by its removal and replacement with tungsten after FEOL processing is complete. The uniqueness of this approach follows mainly from forming the TSVs early in the FEOL while still ultimately using metal as the via fill material. TSVs formed early in the FEOL can be formed at comparatively small diameter, high aspect ratio, and high spatial density. We have demonstrated FEOL-integrated TSVs that are 2 µm in diameter, over 45 µm deep, and on 20 µm pitch for a possible interconnect density of 250,000/cm2. Moreover, thermal oxidation of silicon can be used to form the dielectric isolation. Thermal oxidation is conformal and robust in the as-formed state. Finally, TSVs formed in the FEOL alleviate device design constraints common to vias-last integration.

One of the challenges of laser cooling a semiconductor is the typically high index of refraction (greater than 3), which limits efficient light output of the upconverted photon. This challenge is proposed to be met with a novel concept of coupling the photon out via a thin, thermally insulating vacuum gap that allows light to pass efficiently by frustrated total internal reflection. This study has the goal of producing a test structure that allows investigation of heat transport across a 'nanogap' consisting of a thin film supported over a substrate by an array of nanometer-sized posts. The nanogap is fabricated monolithically by first creating a film of SiO 2 on a silicon substrate, lithographically defining holes in the SiO 2 , and covering this structure including the holes with silicon. Selective lateral etching will then remove the SiO 2 , leaving behind a thin gap between two Si layers spaced apart by nanometer-scale Si posts. Demonstration of this final step by successfully undercutting the a-Si upper layer due to the hydrophobic nature of silicon and the slow etch rate of buffered oxide etch in the small gap has proved to be problematic. Arriving at a feasible solution to this conundrum is the current objective of this project in order to begin investigating the thermal conductivity properties of the structure.

A desire to monolithically integrate near infrared (NIR) detectors with silicon complementary metal oxide semiconductor (CMOS) technology has motivated many investigations of single crystal germanium on silicon (Ge/Si) diodes [1-3]. Reduction of the epitaxy thermal budget below the typical chemical vapor deposition (CVD) in-situ clean temperature (Tin-situ clean > 780°C) is also increasingly desired to reduce integration complexity. Reduced temperature growth approaches have included p+-Ge/n-Si detectors formed with low temperature poly-Ge (e-beam evaporation) or heavily dislocated single crystal germanium (molecular beam epitaxy, T ~ 450°C), which have had dark currents of ~5 mA/cm2 and responsivities of ~15 mA/W at 1310 nm, despite the large number of defects in and at the Ge/Si interface. Responsivities in these materials are however low and believed to be limited by a small diffusion length (i.e., 5-30 nm [2, 4]) due to fast electron recombination in the defect rich germanium. In this paper, we evaluate a commercially available high density plasma chemical vapor deposition (HDP-CVD) process to grow low temperature (i.e., Tin-situ & Tepitaxy < ~450°C) germanium epitaxy for a p+-Ge/p-Si/n+-Si NIR separate absorption and multiplication avalanche photodetectors (SAM-APD). This device structure is of interest both to examine ways to enhance the responsivity with internal gain as well as to examine alternatives to InGaAs-InP structures for NIR Geiger mode (GM) detection. A silicon avalanche region is highly desirable for GM to reduce after-pulsing effects, which are related to defect density that are smaller in Si than in InP [5]. Despite the high defect densities in the Ge and at the interface, the Ge-Si APDs in this work are found to have relatively low dark count rates in Geiger mode.

Patterned arrays with alternating regions of the metallic phase and porous aluminum oxide are fabricated by using a dense layer of barrier aluminum oxide as a mask for porous-type anodization of 99.5% Al and 0.5% Cu films. The pore curvature at the interface between the metallic phase and porous aluminum oxide is investigated as a function of anodization voltage. The degree of anisotropy, which is defined as a ratio between vertical and lateral propagation of pores, increases slightly as anodization voltage increases. The pore curvature compromises the mask transfer during anodization due to the lateral pore propagation under the anodization mask. For miniaturization of regions composed of Al-Cu, it is important to establish the width of anodization mask required to preserve the metallic phase between two regions of porous aluminum oxide. Our results show that a 2 μm wide anodization mask is necessary during porous-type anodization of 3 μm thick Al-Cu films at a chosen set of anodization conditions (40 V, 3% w/v H 2 C 2 O 4 , 5°C).

Porous-type anodization of patterned ∼10 μm thick Al-Cu films results in microstructures with alternating regions of Al-Cu and porous Al 2 O 3 . The volumetric expansion of porous Al 2 O 3 is minimized by increasing the anodization solution temperature. The fidelity of the mask transfer (10 μm wide) is compromised by the lateral pore propagation under the anodization mask. The Al-Cu pillars formed after complete dissolution of porous Al 2 O 3 have a trapezoidal shape. The height of pillars is twice (8 μm) the distance corresponding to the lateral pore propagation (4 μm). In contrast to wet chemical etching, porous-type anodization of patterned Al-Cu films is not isotropic.

Fabrication of patterned anodic aluminum oxide arrays using a dense layer of barrier aluminum oxide as the anodization mask is described. This fabrication process includes patterning of the aluminum film with a photoresist and brief anodization at a high voltage. The photoresist is then removed and the aluminum film is again anodized at a low voltage to grow porous aluminum oxide. Using this procedure, we are able to fabricate anodic aluminum oxide arrays on silicon wafers consisting of alternating regions of porous aluminum oxide and aluminum metal perpendicular to the silicon substrate.