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Test structure development is critical for single wafer pattern collapse evaluations. A good test vehicle not only allows optimization and benchmarking of different processes, but also facilitates understanding of the underlying mechanism. For high aspect ratio silicon nanopillar arrays, by increasing the gap distance in one direction while keeping the other direction constant, an unexpected higher collapse rate is found. This preliminary finding is contradictory to the prevalent models that are based on equilibrium force balance between capillary and mechanical interactions. It is postulated that the asymmetric arrangement of pillars facilitates the formation of liquid bridge and thus more pattern collapse. Such test structures can bring useful insights to understand the dynamic mechanism of pattern collapse.

Vertical PNP bipolar transistor test structures were fabricated and measured, attempting to electrically obtain information on carrier lifetime in the voltage-supporting base region of Insulated Gate Bipolar Transistors (IGBTs). Owing to the structural similarity, the test structures and functional IGBTs can be integrated on the same wafers, making it possible to directly correlate lifetime data and IGBT characteristics. To solve a problem of leaky backside PN junction, common base current gain of the test devices was measured without applying a reverse bias between the collector and base terminals, which suppressed the leakage to an acceptable level. A simple analytical formula to convert the current gain to hole lifetime in the N-type base region was proposed and used, that takes into account the existence of a commonly used N-buffer layer adjacent to the backside P-collector layer. The validity of the formula was confirmed using TCAD simulations. This method was applied to IGBT wafers with two different wafer thicknesses (i.e., base lengths): $120~{{\mu }}\text{m}$ and $360~{{\mu }}\text{m}$ . Consistent lifetime values extracted in spite of the largely different thicknesses supports the validity of the proposed lifetime estimation method.

Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development of a new method for a simultaneous extraction of the gate overlap capacitances and of the channel width and length variations. The approach is presented and illustrated using experimental data obtained by C-V measurements of the MOSFETs in a CMOS test structure. The characterization results are compared with the parameters obtained via I-V measurements of the corresponding devices.

In this paper, a test structure of ring oscillator (RO) with addressable devices under test (DUTs) is described for the extracting of MOSFET capacitance-voltage (C-V) curves. With a high oscillation frequency, the influence of the gate-leakage current will be reduced to negligible. The addressable array and its calibration method in this work mitigate the impact from the layout, spatial and process variations, and improve the test accuracy. Moreover, the consumption of the layout area and test lines are also reduced by this structure.

In this work, a high frequency reflection-type phase shifter implemented in 0.13 μm SiGe HBT technology is presented. It is based on a single-pole single-throw switch topology, utilizing HBTs in reverse-saturation. The phase shifter achieves a return loss of -2.8/-2.5 dB for a phase control of 90.4° at 240 GHz, respectively. The power consumption is 6.8 mW during the ON state. The phase-shifter test structure was fabricated and the measured results show a good agreement with the simulations.

Date of Conference: 4-18 May 2020 Conference name: 33rd IEEE International Conference on Microelectronic Test Structures, ICMTS 2020 This paper presents a complete test structure and characterisation system for the evaluation of nanoelectrode technology. It integrates microfabricated nanoelectrodes for electrochemical measurements, 3D printing and surface tensionconfined microfluidics. This system exploits the inherent analytical advantages of nanoelectrodes that enables their operation with small volume samples, which has potential applications for onwafer measurements.

Avalanche-mode visual light emission in Si diodes is shown to be useful for rapid assessment of the origin of non-ideal currents. In the test structure design, it was important to consider the breakdown-voltage distribution, diode size and contact positioning to obtain light-spot appearances at positions related to bulk defect distributions.

The record low contact resistivity $(\rho_{\mathrm{c}})$ of Ti contact to Ge:B $(8.1\mathrm{x}10^{-10}\Omega-\mathrm{cm}^{2})$ is achieved by in-situ doped CVD using the high-order Ge precursor $(\mathrm{Ge}_{2}\mathrm{H}_{6})$ . The best achievable $[\mathrm{B}]_{\mathrm{act}}$ . of $7\mathrm{x}10^{20}\mathrm{cm}^{-3}$ and extended epitaxial process window are obtained using $\mathrm{Ge}_{2}\mathrm{H}_{6}$ . By optimizing the [B] and [Sn], 2% Sn addition into Ge epitaxy reaches the lowest $\mathrm{p}_{\mathrm{c}}$ of $4.1\mathrm{x}10^{-10} \Omega-\mathrm{cm}^{2}$ . Further Sn addition (4.7% and 13.2%) increases $\rho_{\mathrm{c}}$ due to reduced [B], and degrades the thermal stability. The record low resistivity $(2\mathrm{x}10^{-4}\Omega-\mathrm{cm})$ among epitaxial p-type Ge and GeSn is also demonstrated. Optimized metal etching processes ( $\mathrm{Cl}_{2}+\mathrm{BCl}_{3}$ for metal on $\mathrm{GeSn}:\mathrm{B}$ , while $\mathrm{C}1_{2}$ for metal on Ge:B) are necessary to minimize etching of GeSn:B and Ge:B, and to fabricate the test structure. A two-sheet-resistance model is used to correctly extract the $\rho_{\mathrm{c}}$ . B segregation $(> 1\mathrm{x}10^{21}\mathrm{cm}^{-3})$ at the metal/semiconductor interface enables the record low $\rho_{\mathrm{c}}$ .

Characterizing junction is essential in new devices research. We are investigating a hybrid infrared-sensitive opto-electronic device on silicon-based large scale integrated circuits, among others, PbS colloidal quantum dots/ZnO/Si hybrid IR detector. To assess such new materials we propose a coaxial circular test structure. The structure is composed of common-central inner (circular) and outer (doughnut) electrodes. In addition to traditional Circular TLM (CTLM) test structure, which was used for ohmic contact, the junction type (ohmic or Schottky) can be identified and quantitatively be analyzed by measuring various gaps and surface areas of the proposed structure (Coaxial CTLM, CCTLM). The measurement using test structure on our n-type ZnO / n-type Si heterojunction sample revealed that the junction was Schottky type, which was opposite to our expectation.

Charge-based capacitance (CBCM) measurements require precise measurement of AC currents. This work describes a test structure that produced periodic pulses of current to mimic a CBCM circuit. It was measured in both wafer form on a parametric test system and in package form on a functional test system. Average currents from 600 pA to $10 \mu \mathrm{A}$ at frequencies between 290 kHz and 2.6 GHz were measured on both systems. The parametric tester was shown to be capable of measuring AC currents across that entire range of currents and frequencies. The functional tester was capable at high frequencies, but showed measurement errors at lower currents, seemingly in agreement with its DC current measurement specifications. This technique could be used to validate the limits of any test hardware prior to designing an AC circuit.

Accuracy of extracting ultra-low contact resistivity by the end-resistance method is evaluated. As the contact length becomes smaller than the transfer length, the end-resistance approaches the contact resistance, and the error decreases with the reduction of contact length and contact resistivity. The contact resistivity lower than $10^{-9}\Omega-\mathrm{c}\mathrm{m}^{2}$ can be extracted with accuracy lower than $3\times 10^{-10}\Omega-\mathrm{c}\mathrm{m}^{2}$. This end-resistance method is verified by self-aligned transmission line model test structure. Statistic analysis of the distribution of contact resistance and the uniformity of the contact interface are also demonstrated.

As semiconductor devices shrinks down to sub 10nm range, contact resistance has become a significant performance factor that needs to be studied. Existing test structures such as Transmission line model (TLM) structures are no longer sensitive enough to determine the small changes in specific contact resistance (SCR) at confidence level. This paper reports a methodology to determine SCR in a TLM test structure using Sentaurus Technology Computer-Aided Design (TCAD). The tool is demonstrated to be effective to model and characterize test structures with TCAD. An analysis on the correlation between doping concentration and ohmic contact was investigated. The SCR value is calculated from the extracted total resistance using the analytical model of TLM test structure.

Data on temperature-time curves measured at chimney-roof penetration are reported here. The tests were performed in different configurations in order to reproduce all the possible conditions in which a chimney may operate. To do this, a chimney was installed in a corner test structure and in an axi-simmetric test structure, and in three roofs of different thickness, thermal resistance, and layers position. The space between chimney and roof was left open, sealed with metal sheets, sealed with insulating panels, and filled of insulating material respectively.

A new approach to the design of transparent diamond indenters is proposed, which allows one to obtain a full optical image of the investigated area of the sample surface, including images directly during measurements by applying the indentation and scratching methods. In this case, it is not required to use immersion liquids that fill the region between the sample and the indenter. The measured area is observed with an optical microscope with illumination through an objective lens. Using an indenter in the form of a trihedral Berkovich pyramid, images of the surface of a test structure and the residual indentation are reconstructed and an image of the surface during its deformation under the application of a load to the indenter is obtained.

Thermopile sensors have a wide range of applications in consumer and industry. Seebeck coefficient is a basic thermal parameter of thermopile sensors. Extracting the Seebeck coefficient of both materials and thermocouple in thermopile sensors is of great importance. In this work, an on-chip test structure is designed. It consists of a substrate, a framework, supporting legs and a sensitive region which has a resistor serving as both heater and temperature detector. A set of on-chip test structures are fabricated along with a thermopile sensor. Its measurement results are analyzed and compared with apparatus measurement results. These results are consistent with each other, and the validity of structure is verified.

We present a method for accurately de-embedding the electrical effects of the bias and measurement electrode structure used for spin-torque oscillator (STO) measurements. We propose a simple, but very accurate, method that requires only one additional test structure per STO wafer. We show that the effects of the electrode structure, including phase shift over frequency and insertion loss, can be removed, providing an accurate measurement of the true STO parameters. Our method is verified using 24 STOs across four different wafers each containing 140 STOs.

In this paper, an improved small-signal model of an InAlAs/InGaAs InP-based HEMT device based on RC network is proposed. In the small-signal model, the gate-drain resistance R gd is added to characterize the symmetrical distribution of the under-gate depletion region in the low-voltage case. The RsubCsub series network is used to characterize the influence of lossy substrate on the output characteristics of InP HEMT and improve the fitting accuracy of output admittance. The extraction of extrinsic parameters is realized by the open-short test structure method. The intrinsic elements are determined by solving the intrinsic Y parameters and making reasonable optimizations. The results show that the measurement data of S-parameters are consistent with the simulation results of the model, and the RsubCsub series network can significantly improve the fitting accuracy of output admittance.

Vertical PNP bipolar transistor test structures were fabricated, which can be integrated on the same wafer with functional IGBTs. Common-base current gain was measured by applying zero voltage to the leaky back side junction, from which minority carrier lifetime in the base region was extracted. The structure makes it possible to measure the lifetime after a real IGBT fabrication process flow, and to correlate it with the characteristics of IGBTs on the same wafer.

We assessed potential degradation of MOSFET characteristics induced by post-processing of extra bond pads. The pads are used as stable electrical connections in repairing and test. The test structure consists of $\pmb{16\times 16}$ arrayed PMOSFETs designed with 0.6 $\pmb{\mu}\mathbf{m}$ CMOS technology. An aluminum pad is deposited on the arrayed structure using a silicon shadow mask, and wire bonding is performed subsequently. The characteristics of $I_{\mathrm{d}}-V_{\mathrm{g}}$ were compared before and after the post-process. The result indicates that the post-processing does not affect the characteristics of MOSFETs, and therefore it can be used to place post-processed bond pads over an LSI chip.

This paper presents the simulation of specifically MEMS specimen in the presence of stress concentration factor due to notches. FEM models are realized to study the effect of notch geometric parameters on the stress concentration factor of the gold specimen subjected to tensile loading. Test structures without notch, and with single notch are modeled and realized Maximum axial stresses produced in the specimens and the corresponding stress concentration factors for the notched specimens are obtained using FEM modeling. Realized test structure has been firstly experimentally tested by using profilometers measurements. A first identification of the numerical FEM model is obtained by comparison of the central deflection of the specimen with the central deflection of the measured notched specimen.

The ability to expose a huge kerf/PCM (Process Control Monitor) test structure at the same level is limited from top down finger polishing. Also, in Scanning Electron Microscopy (SEM) the electron beam (e-beam) shift for electron beam absorbed current (EBAC) analysis is not able to cover the whole structure. The recently implemented technique described herein combines the focus ion beam (FIB) chemical enhanced milling method with EBAC analysis to stop the polishing at the upper layer and split the EBAC analysis into portions from the test structure. These help to improve the area of interest (AOI) evenness and enable the extension of the EBAC analysis.

In this paper, the interface between Al2O3 and p-type 4H-SiC is evaluated using x-ray photoelectron spectroscopy (XPS) measurements. These studies are made on dielectric-semiconductor test structures with Al2O3 as dielectric with different pre-and post-deposition treatments. XPS measurements on the as-deposited samples with two different pre-surface cleaning have shown no formation of a SiO2 interlayer. However, after the post deposition rapid thermal annealing (RTA) at 1100 °C in N2O for 60s, a SiO2 interlayer is formed. The surface band bending was determined from Si 2p core level peak shifts measured using XPS. These results suggest that Al2O3 deposited on the p-type 4H-SiC have a net positive oxide charge which is complementary to that of n-type 4H-SiC. From these shifts it was found that the as-deposited RCA cleaned sample had an oxide charge of 5.6×1013 q/cm-2, as compared to standard cleaned samples, having 4.6×1013 q/cm-2. A further reduction in oxide charge was observed after annealing at 1100 °C in N2O, down to a value of 4×1013 q/cm-2.

A nano-film transistor test structure, simulating nano Air-gap thin film transistor (TFT), is developed to study TFT's breakdown when it vibrates at high temperature. To achieve point-wise linear GPa mechanical stress (MS), in situ detection of probe integrated with digital spiral micrometer is designed. Under various GPa order and temperatures loading MS, gate leakage current is measured to study TFT's breakdown. Hot hole injection with high mobility is proposed to be the cause of TFT's breakdown.

The effect of low energy implantation of P or C ions in 3 C-SiC on the properties of Ti/Ni/Au contacts has been examined for doses in the range 10 13 –10 15 ions/cm 2 . Measurements of specific contact resistance, ρ c , were performed using the two-contact circular test structure. The magnitude of ρ c for the Ti/Ni/Au contacts on unimplanted SiC was 1.29×10 −6 Ω cm 2 . The value of ρ c increased significantly at an implant dose of 1×10 15 ions/cm 2 . The dependence of R sh and ρ c on ion dose has been measured using both C and P implant species.

A modified design of the transmission line model test structure uses the simple calculation of specific contact resistance, ρc, based on a two contact linear pattern but without the requirement of a mesa etch. This modified structure uses a linear TLM with semicircular terminations at each end. The function of the semicircular terminations is to confine the fringing fields at the ends of the linear TLM contacts. Simple analytical equations for determining ρc have been developed on the basis of the modified linear TLM pattern. These calculations have shown good agreement with a finite element model (FEM) of the modified TLM test structure using typical parameters for metal/ SiC contacts.

This paper reports new findings about the plasma induced damage on silicon on thin BOX. The plasma charge collected by source or drain causes Vth shift, which depends on BOX thickness. In addition, the plasma charge collected by gate also has same effect with drain antenna. The mechanism of this phenomena is investigated with various test structure.

This paper has shown that, by simply inserting a matching line, the probe pad effects on antenna impedance matching and frequency shift can be reduced. Simulation and measurement results confirm the method.

The effect of HCI (hot-carrier injection) degradation on the variability of FETs is studied with a novel test structure. Using a space-and time-efficient technique, a large number of degradation measurements can be taken in the time usually required for a single device. Studies with this structure have shown that variability is actually reduced by the degradation caused by HCI stress.

We investigate the potential distribution and breakdown of GaN-on-silicon HEMTs by using a test structure with a floating sense node located between gate and drain, in the access region. To demonstrate the effectiveness of the adopted method, we analyze two different wafers, having different 2DEG retraction in the OFF-state and different time to breakdown. We demonstrate that: 1) the floating node can effectively be used to evaluate the potential distribution in the access region; 2-D simulations are compared with the experimental data to demonstrate the effectiveness of the method and 2) the time to breakdown is strongly influenced by the distribution of the potential (and of the electric field) in the access region. A superior robustness is found on devices characterized by an improved distribution of the 2DEG potential between gate and drain. In contrast, devices with a lesser 2DEG retraction show early breakdown when subjected to OFF-state stress. For the first time, we demonstrate a direct correlation between the 2DEG retraction and the OFF-state long-term stability of GaN-on-Si HEMTs. The results reported within this paper provide further insight on the physical origin of time-dependent breakdown in GaN-based power transistors.

An optimized test structure to study rear surface passivation in Cu(In,Ga)Se-2 (CIGS) solar cells by means of photoluminescence (PL) is developed and tested. The structure - illustrated in the abst ...

Understanding of the accuracy of well (here, N-well or NW) placement is a key feature for device characterization and understanding of yield detractors. An analysis technique which provides quick turnaround and allows not only quick examination across large areas but also SEM resolution is needed. Failure analysis of an RX (active) Short in a < 14 nm serpentine/comb test structure indicated a junction problem. A novel yet simple technique for mapping junction profiles based on contrasts observed in low energy e-beam SEM voltage contrast (SEM-VC) was evaluated on carefully delayered samples. The test samples were also characterized by scanning capacitance microscopy (SCM) to correlate with SEM-VC results. The SEM-VC in one case exactly predicted the well image. However, further investigation showed that distinct SEM-VC features on other similarly delayered samples had nothing to do with the underlying junction profiles. For this reason, OBIRCH (Optical Beam Induced Resistance CHange) was used to determine areas of high and low leakage for an SRAM-like test structure.

In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.

Test structures are proposed to characterize Thin-Film-Transistors in array that control a transparent electrode array platform, used for bio-chemical applications. The structures are post-processed electrodes that connect the source terminals of multiple TFTs. This characterization is essential to determine the limits, in terms of sensitivity and operation frequency in the case of impedance measurements on biological cells, as well to investigate other possible biological applications.

We propose a new method which can extract the information about the electronic traps in the semi-insulating GaN buffer of AlGaN/GaN heterostructure field-effect transistors (HFETs) using a simple test structure. The proposed method has a merit in the easiness of fabricating the test structure. Moreover, the electric fields inside the test structure are very similar to those inside the actual transistor, so that we can extract the information of bulk traps which directly affect the current collapse behaviors of AlGaN/GaN HEFTs. By applying the proposed method to the GaN buffer structures with various unintentionally doped GaN channel thicknesses, we conclude that the incorporated carbon into the GaN back barrier layer is the dominant origin of the bulk trap which affects the current collapse behaviors of

A variety of strain sensors have been developed to measure internal deformations of elastomeric structures. Strain sensors measuring extremely small mechanical strain, however, have not yet been reported due mainly to the inherently intrusive integration of the sensor with the test structure. In this work, we report the development of a minimally intrusive, highly sensitive mechanical strain transducer realized by monolithically embedding a Fabry-Pérot (FP) etalon into a poly(dimethylsiloxane) (PDMS) block test structure. Due to the extreme sensitivity of the FP resonance condition to the thickness of the spacer layer between the two reflectors, the limit of detection in the mechanical deformation can be as low as ~110 nm with a 632.8 nm laser used as the probing light. The compatibility of PDMS with additive fabrication turned out to be the most crucial enabling factor in the realization of the FP etalon-based strain transducer.

Top-gated MOS capacitors on bulk MoS2 and transistors of few-layer MoS2 were designed and fabricated. They can be potentially utilized on various TMD and high-k materials for fast and robust electrical characterization. The 3-terminal transistor test structure shows advantages of significant reduction of parasitic effects. C-V and I-V measurements were successfully conducted to characterize few-layer MoS2 transistors with sub-10 nm HfO2 dielectric.

International audience; Microfabricated test structures are presented for the proof validation of a new chemical sensor concept. The proposed detection principle is based on time constant shift of a thermal device covered with zeolites when target species are adsorbed. © 2016 IEEE.

This work focuses on the development of a novel test structure to evaluate the dynamic behavior of electrical characteristics in the boron-implanted germanium samples during the solid phase epitaxial regrowth (SPER) at low temperature annealing of 360 and 400 °C with various annealing times ranging from 30 to 300 min. In the early stage of SPER annealing, the sheet carrier concentration is increased with annealing time. And then, it will saturate to a level after about 2 hr annealing which implies the completion of SPER process.

The transport properties of graphene field effect transistors are typically characterized using a conventional test structure consisting of graphene on silicon dioxide with deposited metal contacts. Two of the primary parameters affecting the total resistance of this structure are the channel mobility and contact resistance. A simple model is used to describe the impact of these parameters on total device resistance and experimentally extract them. Important issues related to characterizing the transport properties of graphene field effect transistors are presented and discussed.

Large-scale measurement of material property is not suit for the MEMS thin-film. Research the in-situ measuring method for material property of the MEMS thin-film is urgently. A center-anchored circular plate is adopted as the test structure here. The resonance frequency of the circular plate is measured to extract the Young’s modulus of a MEMS thin-film. The accuracy of this non-contact in-situ measuring method has been verified by CoventorWare. The inferences of the stress gradient have been analyzed. The advantages of the test structure and the measuring method present here also have been discussed.

Multiple techniques including electrical resistance measurement plus calculation, cross-sectional view of passive voltage contrast (XPVC) sequential searching, planar and cross-section STEM are successfully used to isolate a nanoscale defect, single metallic stringer in a snakecomb test structure. The defect could not be found by traditional failure analysis methods or procedures. The unique approach presented here, expands failure analysis capabilities to the detection of nanometer-scale defects and the identification of their root causes. With continuous shrinking feature sizes, the need of such techniques becomes more vital to failure analysis and root cause identification, and therefore yield enhancement in fabrication.

In this paper we report the fabrication and detailed electrical characterization of a novel test structure based on Metal-Ferroelectric-Oxide-Semiconductor transistor with internal metal contact, aiming at extracting the surface potential and the investigation of internal voltage amplification expected due to negative capacitance effect. The proposed test structure is p-Fe-FET with a thin Al contact in-between the PVDF ferroelectric and a pedestal oxide, enabling access to the internal voltage potential in all the regimes of operations, from weak to strong inversion. Moreover, the capacitances of reference MOS transistor and of Fe-FET can be independently probed. The test structure was fabricated on low doped silicon with STI isolation, in n-implanted well, with a gate stack including 6.5nm of SiO 2 , 50nm of Al, 100nm of P(VDF-TrFE) and Au as top contact. The fabricated p-type Fe-FET has an excellent subthreshold slope of 75mV/decade, Ion/Ioff > 107 and Ioff in the pA range. Based on voltage and capacitive measurements, the Fe-FET surface potential is extracted for the first time. We demonstrate that the internal node voltage amplitude can be controlled by the sweeping conditions of the polarization loops. The test structure appears highly suited for the future investigation of the negative capacitances and of more complex ferroelectric gate stacks.

In this paper we report on a multilink electromigration test structure in which the current density is varied for the different links. We show the time to failure can be determined for each link by analyzing the resistance vs. time characteristic of the whole chain. Distributions of the obtained times to failure are then used to compute electromigration current exponent and threshold product. Both parameters can be determined with satisfactory accuracy by performing a reduced set of experiments. This structure and method can therefore be employed to significantly reduce experimental workload and cycle time usually required for complex electromigration parameters determination, such as electromigration threshold product.

This articles details investigation into metal voiding observed on electroplated gold interconnect during high temperature wafer-scale bake. The test structures and methodology to measure this effect are discussed in detail. Various factors affecting a metal voiding phenomenon were examined and measured. A drainage ratio is defined to quantify the effects of test structure layout proportions on gold void formation. Different metal formulations were also investigated to better comprehend the influence of metal composition on gold void formation. Furthermore the effect of temperature on void formation was studied and an activation energy of 2.0 eV was estimated for this phenomena. Several methods are proposed to minimize any reliability impact from this phenomenon.

We show measurement results of variation-tolerance of an error-hardened dual-modular-redundancy flip-flop fabricated in a 65-nm process. The proposed error-hardened FF called BCDMR is very strong against soft errors and also robust to process variations. We propose a shift-register-based test structure to measure variations. The proposed test structure has features of constant pin count and fast measurement time. A 65nm chip was fabricated including 40k FFs to measure variations. The variations of the proposed BCDMR FF are 74% and 55% smaller than those of the conventional BISER FF on the twin-well and triple-well structures respectively.

A test structure on the basis of nanoprofiled aluminum to determine the curvature radius of the cantilever tip is described. This structure was tested by studying tips with different geometries. The test structure allows one to determine the tip sharpness geometry with an accuracy of 2 nm.

High-k LTCC tapes with ultralow sintering temperatures were developed from lead-free perovskite powders. Lowering of the sintering temperature from 1250°C down to 900°C has been achieved by means of ultrafine ceramic powders in combination with suitable sintering aids. The tape-casting process has been optimized for ultrafine powders with an enhanced sintering activity. Low-sintering high-k tapes of a thickness down to 40 μm, suitable for LTCC processing, were obtained. The sintering behavior of these high-k tapes has been studied and compared with other LTCC materials. Dielectric properties of the high-k material have been investigated on a multilayer test structure consisting of up to 20 dielectric layers. After metallization with an Ag conductor, the green tapes were stacked and laminated. Sintering of these multilayer stacks at 900°C gives dense ceramic samples. Permittivities up to 2000 have been obtained, together with low dielectric losses. Material compatibility with several Ag/Au-thick-film-paste systems has been tested.