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In this paper, we have demonstrated a plasma activated low-temperature die-level oxide-oxide direct bonding with advanced wafer dicing technologies. This evaluation used blanket 300-mm silicon wafers. $1\ \mu\mathrm{m}$ Tetraethyl orthosilicate (TEOS) oxide was deposited by plasma-enhanced chemical vapor deposition (PECVD) directly on the silicon (Si) wafer surface, followed by chemical mechanical planarization (CMP). Atomic Force Microscopy (AFM) was used to examine the roughness of the wafer surface before dicing and it showed $\mathrm{R}_{\mathrm{a}}$ . Several dicing technologies such as diamond blade dicing, step-cut blade dicing, bevel blade dicing, and stealth laser dicing were evaluated for this integration scheme. In the end, diamond blade dicing has the most compatibility with many materials, but it led to large chipping on the edges of the die. Stealth laser dicing achieves edge chipping of less than $2\ \mu\mathrm{m}$ , which is the least amount of damage among of all dicing methods tested in this study. In the bonding test, the 10 mm square silicon die was bonded to a 35-mm square silicon substrate. Both silicon die and substrate are of thickness $760\ \mu\mathrm{m}$ . Prior to direct oxide-oxide bonding, both silicon die, and substrate went through a two-step cleaning process. The detailed process of the plasma activated die-level direct bonding is discussed.

Understanding and simulating 3D doping performed by Plasma Immersion Ion Implantation on FinFETs or on deep trenches for flash memories or power devices applications is a key topic to optimize process parameters and to forecast effect of form factor evolution requested by technology scaling. In this work, we developed a model based on the following strategy.1-Calculation of angle and energy distribution of ions and neutrals reaching wafer surface as function of PIII process parameters (TRIM Monte Carlo simulation in gases)2-Calculation of local ion distributions (quantity, angle and energy distribution) along the top, walls and bottom of Fins or trenches based on simple geometrical model with shadowing effect.3-Calculation of local in depth dopant distribution on all points of the structure based on TRIM Monte-Carlo simulation4-Recalculation of mean concentration profile and comparison with 1.5D SIMS.Effect of main process parameters (plasma density and pressure) is shown as well as geometrical parameters of doped structures (aspect ratio, tapering angle). After having compared the model to experimental data, impact of geometrical changes due to technology scaling is discussed (fin pitch for Finfet application, form factor for trench doping applications)

Self-aligned contact (SAC) is required for 7 nm node to reduce susceptibility of contact-to-gate short failures. This requires forming a SAC cap on metal-recessed gate. The SAC cap formation is usually achieved by removing nitride on the field by planarization techniques such CMP (chemical mechanical polishing) or GCIB (gas cluster ion beam) processes. Significant gate stack height variation can be observed lot-to-lot and wafer-to-wafer due to accumulated variations from multiple steps, including several CMP steps, before the SAC cap module, especially during early research and development prior to full optimization of the steps before the SAC cap module. GCIB potentially offers a method by which the early development stage variation due to CMP steps can be reduced, allowing integration and device learning during the early stages of a program. This study shows a comparison of SAC cap formation by CMP only vs. GCIB with integrated metrology enabled location specific processing. By using GCIB with feed-forward scatterometry measurements taken from a 2D measurement pad we have been able to significantly improve both lot-to-lot and wafer-to-wafer variation on early development wafers. This has led to improvement in within wafer SAC cap thickness non-uniformity, wafer to wafer and lot to lot device yield for gate-contact over a CMP-only process flow.

Particle contamination within a plasma-etching chamber causes tool down time in semiconductor manufacturing. The purpose of this work is to investigate the sources of contamination and find an effective solution for Back End of Line (BEOL) processes and improve tool up time. Despite typical maintenance, such as cycling chamber, wiping Electric Static Chuck (ESC) components and replacing chamber consumable parts, particle contamination issue persisted. Contamination analysis and ESC examination suggested etch byproduct redeposition during chuck discharge step as root cause. Modifying the discharge step was found to reduce the particle failure rate from 50% to 7%. This significant improvement confirms redeposition on ESC during discharge step and particle resuspension from ESC surface is the primary source for the particle contamination issue.

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

The effect of bulk chemistry of deposited oxide materials on the eventual wafer bonding energy was fundamentally studied. Although low-temperature silicon oxide (LTO) and tetraethyl orthosilicate (TEOS) exhibited the same bulk density, and nitrogen plasma generated a higher degree of surface activation for TEOS than LTO, using LTO as the bonding oxide resulted in a much higher bonding energy than TEOS. This was attributed to the relatively high percentage of hydrogen-bonded silanol groups in LTO, which pointed to the existence of fine defect areas in LTO that would better accommodate the water molecules generated later by the interfacial condensation reactions. A pre-bonding baking step was found favorable for LTO wafer bonding.

For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

This study explored the effects of substrate surface pretreatments on the nucleation and growth of metal–organic chemical vapor deposited ruthenium. In situ plasma (dry), featuring O2, Ar, and H2/Ar chemistries, and ex situ (wet) treatments, consisting of a standard RCA bath, were examined in the nucleation and growth of up to 50-nm-thick metallic Ru films on SiO2 and Hf–silicate surfaces. The resulting surface morphology, grain size, and roughness of the metallic films were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM), while Rutherford backscattering spectrometry (RBS) was used for compositional measurements. It was determined that an in situ plasma treatment using a H2/Ar yielded metallic Ru films with the highest nucleation density, smallest grain size, and lowest resistivity. Film buckling was also observed for the Ru films deposited on H2/Ar pretreated surfaces. The behavior was attributed to the presence of compressive strain. The films deposited on RCA-cleaned and Ar plasma treated surfaces exhibited very similar physical and electrical characteristics to the films grown on untreated substrates. Alternatively, the use of O2 plasma surface treatment adversely affected Ru nucleation on the SiO2 surface. Relevant mechanisms for Ru nucleation and growth on SiO2 and Hf–silicate nontreated surfaces are discussed in the context of the various predeposition dry and wet treatments.

The electrical properties of ultrathin amorphous Al2O3 films, grown by low temperature metal-organic chemical vapor deposition from aluminum(III) 2,4-pentanedionate and water as co-reactants, were examined for potential applications as gate dielectrics in emerging complementary metal-oxide semiconductor technologies. High-frequency capacitance–voltage and current–voltage techniques were used to evaluate Al2O3 films deposited on silicon oxynitride on n-type silicon (100) substrates, with thickness ranging from 2.5 to 6.5 nm, as a function of postdeposition annealing regimes. Dielectric constant values ranging from 11.0 to11.5 were obtained, depending on the annealing method used. Metal-insulator-semiconductor devices were demonstrated with net equivalent oxide thickness values of 1.3 nm. Significant charge traps were detected in the as-deposited films and were mostly passivated by the subsequent annealing treatment. The main charge injection mechanism in the dielectric layer was found to follow a Poole–Frenkel behavior, with post-annealed films exhibiting leakage current an order of magnitude lower than that of equivalent silicon oxide films.

A low-temperature (320–480 °C) metal-organic chemical vapor deposition (MOCVD) process was developed for the growth of ruthenium and ruthenium oxide thin films. The process used bis(ethylcyclopentadienyl)ruthenium [Ru(C5H4C2H5)2] and oxygen as, respectively, the ruthenium and oxygen sources. Systematic investigations of film formation mechanisms and associated rate limiting factors that control the nucleation and growth of the Ru and RuO2 phases led to the demonstration that the MOCVD process can be smoothly and reversibly modified to form either Ru or RuO2 through simple and straightforward modifications to the processing conditions–primarily oxygen flow and substrate temperature. In particular, films grown at low oxygen flows (50 sccm) exhibited a metallic Ru phase at processing temperatures below 480 °C. In contrast, films grown at high oxygen flow (300 sccm) were metallic Ru below 400 °C. Above 400 °C, a phase transition was observed from Ru to RuOx (0 < x < 2.0) to RuO2 as the processing temperature was gradually increased to 480 °C.

A low-temperature metalorganic chemical vapor deposition process was developed and optimized, using a design of experiments approach, for the growth of ultrathin aluminum oxide (Al2O3) as a potential gate dielectric in emerging semiconductor device applications. The process used the aluminum β-diketonate metalorganic precursor [aluminum(III) 2,4-pentanedionate] and water as, respectively, the metal and oxygen source reactants to grow Al2O3 films over a temperature range from 250 to 450 °C. The resulting films were analyzed by x-ray photoelectron spectroscopy, x-ray diffraction measurements, Rutherford backscattering spectrometry, nuclear-reaction analysis for hydrogen profiling, scanning electron microscopy, transmission electron microscopy, and atomic force microscopy. The as-deposited Al2O3 phase was amorphous and dense and exhibited carbon and hydrogen incorporation of, respectively, 1 and 10 at.%. Postannealing at 600 °C led to a reduction in hydrogen concentration to 1 at.%, while maintaining an amorphous Al2O3 matrix.

A novel hybrid bonding process has been developed that achieved a successful copper/SiO 2 heterogeneous bonding.

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm 2 . Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch

300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.

Satellite spot defects are a class of defects widely observed in photoresist processing in 248 nm and 193 nm lithography. These defects become more and more significant as the feature sizes shrink and can potentially become “killer” defects, leading to bridging between lines and/or blocking vias. Traditional potential solutions (i.e., optimization of development rinse step) have yielded improvements in the past but did not eliminate the problem. The use of water-soluble topcoat layers was shown to eliminate these defects but it imposes limitations on throughput and cost and it is incompatible with 157 nm lithography and 193 nm immersion schemes. In this work, we report the use of aqueous surfactant solutions for the suppression of defects in 248 nm and 193 nm lithography, with emphasis on satellite spot defects. Suppression of total defects by up to ~99% and practically complete elimination of satellite spot defects were achieved by use of aqueous surfactant solutions for various resists. A handful of materials that can be incorporated into rinse solution for the successful elimination of blob defects in a variety of resists were identified. It was determined that the two most important factors that enable successful defect elimination are the surfactant concentration and the extent of surfactant adsorption to specific resist systems.

A low-temperature metal organic chemical vapor deposition (MOCVD) process for the growth of aluminum oxide for gate dielectric applications has been developed. Amorphous films were deposited on 200-mm Si(100) wafers, employing an Al β-diketonate precursor [Al(III) 2,4-pentanedionate] and H2O. Chemical and microstructural properties of films grown in a temperature range of 250-450°C were studied using x-ray photo-electron spectroscopy (XPS), xray diffraction (XRD), Rutherford back-scattering spectrometry (RBS), nuclear reaction analysis (NRA), cross-sectional (X) scanning and transmission electron microscopy (XSEM and XTEM). A design of experiment (DOE) method was used for process mapping and optimization. An optimized process window was defined for the growth of dense, amorphous films with carbon and hydrogen inclusion as low as 1 at. % and 3 at. % respectively. Post-deposition annealing studies indicated that chemical and structural film properties are generally stable up to 650°C. The electrical performance of the films was evaluated by capacitance-voltage (C-V) and currentvoltage (I-V) measurements on metal-oxide-semiconductor (MOS) structures. The dielectric constant (k) obtained was 6.7-9.6 (depending on annealing conditions), with equivalent oxide thickness (EOT) as low as 1.3 nm. Leakage current densities lower than that of equivalent SiO2 films were also achieved.

In this work, the electrical performance and interfacial characteristics of MOCVD-grown Al2O3 films are evaluated. Electrical characteristics (dielectric constant, leakage current) of as-deposited and annealed capacitor metal-oxide-semiconductor (MOS) stacks were determined using capacitance-voltage (C-V) and current-voltage (I-V) measurements. It was observed that the electrical properties were dependent upon specific annealing conditions, with an anneal in O2 followed by forming gas being superior with respect to leakage current, resulting in leakage characteristics superior to those of SiO2. All annealing conditions evaluated led to an increase in dielectric constant from 6.5 to 9.0–9.8. Also, Al2O3 growth and interfacial oxide growth characteristics on oxynitride/Si and Si substrates were evaluated and compared using spectroscopic ellipsometry. A parasitic oxide layer was observed to form on silicon during the initial stages of MOCVD Al2O3 growth, while a thin oxynitride layer deposited on Si prevented the growth of interfacial oxide.

In this work, Ru and RuO2 films have been investigated for potential applications in emerging CMOS gate electrode and memory capacitor bottom electrode applications. Films were deposited on SiO2 using chemical vapor deposition (CVD) and low power plasma assisted CVD (PACVD) in a 200-mm wafer deposition cluster tool using a metal beta-diketonate precursor [Bis (2,2,6,6-tetramethyl-3,5-heptanedionato) (1,5-cyclooctadiene) ruthenium (II)]. Hydrogen and oxygen were employed as the reactive gases to deposit, respectively, Ru and RuO2, over a wafer temperature range from 320°C to 480°C. The resulting film properties were analyzed using cross-sectional scanning electron microscopy (CS-SEM), four point resistance probe, x-ray photoelectron spectroscopy (XPS), Rutherford backscattering spectrometry (RBS) and x-ray diffraction (XRD). Both Ru and RuO2 films could be deposited with minimal carbon concentration (∼5 at. %). The purity of the films was also reflected in the as-deposited resistivity of the films, which was as low as 47 μΩ-cm, and was strongly dependent on processing conditions. In order to assess thermal stability, the films were subsequently annealed in forming gas and oxygen ambients for 60 min at 650°C. It was observed that, generally speaking, CVD RuO2 films were stable, with respect to resistivity, in oxidizing ambients, while annealing in a reducing ambient resulted in significant film densification and reduction of the film resistivities to as low as 43 μΩ-cm. Ru films demonstrated good adhesion after anneals in oxidizing, but not in reducing ambients.

Silicon nitride technology has been incorporated in ultra-large scale integration (ULSI) microchip fabrication, thin film transistors (TFT), solar cells, and many other applications in a rapidly expanding market. Nevertheless, silicon nitride technologies currently in use face considerable limitations. Low pressure chemical vapor deposition (LPCVD) occurs at relatively high temperature (>700 °C) and plasma enhanced chemical vapor deposition (PECVD), although occurring at temperatures below 300 °C, produces hydrogen-rich films and could be self-limiting in terms of conformality and damage to the devices due to ion bombardment. In the present work, successful low temperature thermal chemical vapor deposition (LTCVD) of silicon nitride is reported on 8” silicon wafers. The use of a halide-based silicon precursor, tetraiodosilane (SiI4) has led to the deposition of high quality silicon nitride thin films at temperatures as low as 300 °C.Characterization of resulting film properties has been performed to determine their dependence on deposition parameters by Auger Electron Spectroscopy (AES), Rutherford Backscattering Spectroscopy (RBS), Fourier Transform Infrared (FTIR), Nuclear Reaction Analysis (NRA), Ellipsometry, Capacitance-Voltage (C-V), and Current-Voltage (I-V) measurements.

Robust ultrathin (20 nm) trilayer low k SiNx/SiNy/SiCNH dielectric Cu caps (k ~4.0-4.2) with post ultraviolet (UV) cure compressive stress were developed and integrated into 22nm CMOS Back End Of Line (BEOL) devices. The new cap reduces device's capacitance (~ 4 %) and enhances stress stability in Cu-Ultra low k structures

A low-temperature metallorganic chemical vapor deposition process has been developed for the growth of hafnium silicate thin films for advanced gate dielectric applications. In this process, a metallorganic hafnium precursor, tetrakis(dimethylamino-)hafnium, and a metallorganic silicon precursor, tris(dimethylamino)silicon, were employed, using O 2 as a co-reactant. Films were deposited at a substrate temperature in the range of 250-450°C. The films were subsequently annealed in oxygen and forming gas ambients to assess thermal stability. The resulting films were characterized by Auger electron spectroscopy to determine composition and X-ray diffraction to determine microstructure. Electrical test structures were fabricated with as-deposited and annealed hafnium silicate films, and C-V and J-V measurements were performed. As-deposited dielectric constant values ranging from 6.9 to 12.9 were achieved depending on processing conditions and resulting film composition. Leakage current density at flatband voltage minus 1 V for a 26 nm thick as-deposited film was measured to be 1.6 X 10 -1 A/cm 2 and was shown to decrease following an O 2 anneal. The performance of these hafnium silicate films was also compared to hafnium oxide films deposited using the same Hf precursor and O 2 oxidizer approach.