Search

Increasing demands for mass storage and new paradigm computing ask for non-volatile memories that can meet reliability requirements. Hf0.5Zr0.5O2-based (HZO) memory has attracted growing attention due to its excellent CMOS compatibility. This letter investigated the time dependent dielectric breakdown (TDDB) of HZO ferroelectric under both forward and reverse stress conditions, which is relevant to the memory’s practical operation. The key similarities and the differences for both breakdown conditions have been identified and the underlying mechanism is explored. It is found that the pre-existing oxygen vacancies near the bottom electrode play the key role and all the observed phenomenon can be explained. Therefore, the precise control of these pre-existing oxygen vacancies can be critical for future TDDB improvement.

In this brief, typical locations of the interface and oxide traps generated by the hot carrier degradation (HCD) in FinFETs are studied with experiments and “atomistic” TCAD simulations under the worst case stress conditions. The typical round-Fin locations of different types of traps are analyzed by comparing the experimentally extracted results with the calibrated TCAD simulations. Then, the traps’ different impacts on HCD variations in both forward and reverse bias modes are employed to disclose the typical lateral locations of different traps. The results suggest that for both n- and p-type of FinFETs under the worst case stress conditions, the interface traps and oxide traps (type 1) are mainly distributed in the midchannel region closer to the source side on the Fin side, whereas oxide traps (type 2) are mainly distributed in the midchannel region closer to the drain side on the Fin top. Therefore, the two types of oxide traps originate in the different generation locations but may share the same atomistic structures in the same device. The results are helpful to the physical understandings of HCD in the FinFET technology.

In this paper, our recent studies on the hot carrier degradation (HCD) in FinFETs, as well as HCD-induced dynamic variability, are summarized. The kinetics and statistics of FinFET HCD are experimentally investigated. New observations on HCD are reported, which are due to the simultaneous generation of both interface and oxide traps. Based on the trap-based approach, instead of the conventional carrier-based approach, the HCD and its variations are well-described with the proposed multi trap-based compact models, that are unified over the full $\{V_{gs},V_{ds}\}$ bias region. The typical average locations of the HCD-induced traps in FinFET under the worst-case stress condition are also identified. The results are helpful for the physical understanding and modeling of HCD, and the reliability-aware circuit design for FinFET technology.

As a promising alternative to the fundamental device structure, the gate-all-around silicon nanowire transistor (GAA SNWT) has been studied extensively for decades. In this chapter, the device physics, compact modeling, and fabrication process of GAA SNWT are systematically reviewed, as well as its potential applications in terms of different technology diversities. In the first part, the bulk-Si based integration scheme, quasi-ballistic transport characterization, parasitic capacitance, and self-heating modeling of GAA SNWT are presented. Following that, the variability and reliability physics and models of GAA SNWT are studied in-depth. Finally, the application examples in electrostatic discharging, radio frequency/analog circuit, and bio-sensor of GAA SNWT are demonstrated.

Author(s): Liu, YY; Liu, F; Wang, R; Luo, JW; Jiang, X; Huang, R; Li, SS; Wang, LW | Abstract: The complexity of charge trapping in semiconductor devices, such as high-κ MOSFETs, is increasing as the devices themselves become more complicated. To facilitate research into such charge-trapping issues, here we propose an optimized simulation framework that is composed of density-functional theory (DFT) for electronic structure calculation and Marcus theory for the calculation of charge-trapping rates. The DFT simulations are either carried out or corrected by using the Heyd-Scuseria-Ernzerhof hybrid functional. Using this framework, the hole-trapping characteristics along multiple paths in Si/SiO2/HfO2 stacks are investigated, and the relative importance of each path is revealed by calculating its exact hole-trapping rate. Besides the study on crystalline stacks, we also create an amorphous stack, which is more realistic compared with experiments and real devices, to reveal more active trapping centers and to study the statistical feature of charge trapping induced by structural disorder. In addition, to seek effective measures for relieving these charge-trapping problems, the effects of hydrogen and fluorine passivations are discussed, and physical insights for improving the performance of high-κ MOSFETs are provided.

In this work, ultrathin indium tin oxide (ITO) radio frequency (RF) transistors have been demonstrated for the first time, where inverted gate structure are used with a flexible polyimide substrate using magnetron sputtering at a thermal budget below 200 °C. The 160 nm channel length device exhibits excellent DC characteristics, including mobility of 26 cm2/V•s and an I on /I off ratio of 6.6×108. A record-high extrinsic cut-off frequency (f T ) of 2.1 GHz and an extrinsic maximum oscillation frequency (f max ) of 3.7 GHz have also been obtained, which are more than one order of magnitude higher than previous results on flexible substrate. A high conversion gain of -20.9 dB has been achieved for the gigahertz frequency mixer based on flexible ITO RF transistor. Moreover, the stability of DC and RF performance under different bending conditions up to 50,000 bending cycles or down to 1 mm bending radius are studied without device failure.

In this paper, we report high-speed ultrathin-body (3.5 nm) indium-tin-oxide (ITO) transistors using high-k HfLaO dielectrics with a thickness of 5 nm. Because of its low dielectric constant and large bandgap, ITO is a promising channel material for scaling below the 5 nm regime for advanced low-power electronics with excellent short-channel-immunity. Here, we fabricate sub-100-nm channel length ITO transistors with ultrahigh on/off ratio near 1011 and ultralow off-state current below 10 fA/μm. The 15-nm-long ITO transistor exhibits high performance with the maximum on-state current of 970 μA/μm and peak g m of 400 μS/μm at V ds = 0.5 V. NAND, NOR, and SRAM based on enhancement/depletion mode (E/D) inverters have achieved full rail-to-rail output characteristics and stable memory function. Finally, We demonstrated a stage delay of 0.49 ns/stage for a 5-stage ring oscillator based on bootstrapped mode (BST) inverter, which is the best among all results based on metal-oxides transistors.

Hole velocity in black phosphorus exceeds most other semiconductors at room temperature and is even higher at low temperatures., As a strong candidate for future electronics, atomically thin black phosphorus (BP) has attracted great attention in recent years because of its tunable bandgap and high carrier mobility. Here, we show that the transport properties of BP device under high electric field can be improved greatly by the interface engineering of high-quality HfLaO dielectrics and transport orientation. By designing the device channels along the lower effective mass armchair direction, a record-high drive current up to 1.2 mA/μm at 300 K and 1.6 mA/μm at 20 K can be achieved in a 100-nm back-gated BP transistor, surpassing any two-dimensional semiconductor transistors reported to date. The highest hole saturation velocity of 1.5 × 107 cm/s is also achieved at room temperature. Ballistic transport shows a record-high 36 and 79% ballistic efficiency at room temperature and 20 K, respectively, which is also further verified by theoretical simulations.

To deeply understand the charge trapping process in high-k gate stacks, we theoretically investigate the hole trapping characteristics of interfacial oxygen vacancies in (110) and (100) Si/SiO 2 /HfO 2 stacks. Si/SiO 2 and SiO 2 /HfO 2 interfacial defects are studied, and the hole trapping rate of each defect is calculated through ab initio simulation combining density-functional theory and Marcus theory. Among the possible hole traps considered in this work, it is suggested that the oxygen vacancies at SiO 2 /HfO 2 interface are the dominant under strong negative gate bias stress, and those at Si/SiO 2 interface can be effective traps only when hydrogen atom (H) or hydroxyl (OH) is induced at the vacancy. Moreover, the most dominant hole trap among the considered traps in the (110) structure locates at the Si/SiO 2 interface, while that in the (100) structure locates at the SiO 2 /HfO 2 interface.

Zn 0.5 Fe 2.5 O 4 nanoparticles (NPs) of 22 nm are synthesized by a one-pot approach and coated with silica for magnetic hyperthermia agents. The NPs exhibit superparamagnetic characteristics, high-specific absorption rate (SAR) (1083 wg −1 , f = 430 kHz, H = 27 kAm −1 ), large saturation magnetization ( M s = 85 emu g −1 ), excellent colloidal stability and low cytotoxicity. The cell uptake properties have been investigated by Prussian blue staining, transmission electron microscopy and the inductively coupled plasma-mass spectrometer, which resulted in time-dependent and concentration-dependent internalization. The internalization appeared between 0.5 and 2 h, the NPs were mainly located in the lysosomes and kept in good dispersion after incubation with human osteosarcoma MG-63 cells. Then, the relationship between cell uptake and magnetic hyperthermia performance was studied. Our results show that the hyperthermia efficiency was related to the amount of internalized NPs in the tumour cells, which was dependent on the concentration and incubation time. Interestingly, the NPs could still induce tumour cells to apoptosis/necrosis when extracellular NPs were rinsed, but the cell kill efficiency was lower than that of any rinse group, which indicated that local temperature rise was the main factor that induced tumour cells to death. Our findings suggest that this high SAR and biocompatible silica-coated Zn 0.5 Fe 2. O 4 NPs could serve as new agents for magnetic hyperthermia.

In this paper, the degradation of drain-induced barrier lowering (DIBL) in FinFETs is experimentally studied under various hot carrier degradation (HCD) stress conditions. A test method is developed to characterize channel barrier height modulation under different HCD stress conditions. A linear relationship of ΔV thlin and ΔV thsat after HCD is found. Then a compact model of HCD-induced ΔDIBL is proposed. The results are helpful for the physical understanding and modeling of HCD in nanoscale FinFETs and aging-aware circuit design.

In this paper, the impact of body bias on hot carrier degradation (HCD) in advanced FinFET devices is experimentally investigated. It is observed that the degradation of I dsat is increasing with body bias for the short-channel core devices, while an opposite tendency is found in the long-channel IO devices. The different dependences are found due to the mechanisms of the single-carrier event (SCE) in short-channel devices but the multi-carrier event (MVE) in long-channel devices. The results are helpful for the physical understanding of HCD in FinFET devices.

The temperature dependence of hot carrier degradation (HCD) in FinFET is observed to vary with bias conditions, channel local temperature and degradation time. It is found that the total HCD consist of both contributions from interface traps and oxide traps, whose individual temperature behaviors are different. Therefore, the total HCD composition varies with different conditions causing nonuniversal temperature dependence of HCD. The understandings are helpful for the physical investigation and modeling of HCD in advanced FinFET Technology.

In this paper, based on the quantitatively characterized factor of channel current percolation path (PP), the local current fluctuations characteristics in device channel can be directly determined by I-V curves only, which links the microscopic PPs to macroscopic device electrical parameters. The results indicate that the newly-defined “killer ratio” of PP is highly correlated with subthreshold swing degradation rate in both planar devices and FinFETs. It is also found that the current in PP area increases slower with V_{g} than the current in non-PP area, which is verified through TCAD and SPICE simulations. The explanation of the physical nature of correlated behavior sheds new light on understanding statistical variability and reliability in nanoscale devices.

The interface between III-V and metal-oxide-semiconductor materials plays a central role in the operation of high-speed electronic devices, such as transistors and light-emitting diodes. The high-speed property gives the light-emitting diodes a high response speed and low dark current, and they are widely used in communications, infrared remote sensing, optical detection, and other fields. The rational design of high-performance devices requires a detailed understanding of the electronic structure at this interface; however, this understanding remains a challenge, given the complex nature of surface interactions and the dynamic relationship between the morphology evolution and electronic structures. Herein, in situ transmission electron microscopy is used to probe and manipulate the structural and electrical properties of ZrO2 films on Al2 O3 and InGaAs substrate at the atomic scale. Interfacial defects resulting from the spillover of the oxygen-atom conduction-band wavefunctions are resolved. This study unearths the fundamental defect-driven interfacial electric structure of III-V semiconductor materials and paves the way to future high-speed and high-reliability devices.

Compared with conventional tunneling field-effect transistor (TFET), the new junction-modulated TFET (JTFET) can reliably and effectively achieve much steeper switching behavior and higher ON current by only changing the gate layout configuration. To facilitate the JTFET circuit simulation, in this work, we establish a physical tunneling current model of JTFET based on the analytical surface potential modeling. The modeled results with different device parameters are in good agreement with the simulated results by Sentaurus TCAD tools, showing the validity of proposed model.

In this paper, hot carrier degradation (HCD) in FinFET is studied for the first time from trap-based approach rather than conventional carrier-based approach, with full Vgs/Vds bias characterization and self-heating correction. New HCD time dependence is observed, which cannot be predicted by traditional models. A trap-based HCD compact model is proposed and verified in both n- and p-type FinFETs, which is unified across different Vgs/Vds regions with different carrier transport mechanisms. Impacts of HCD on analog circuits is also demonstrated, showing bias runaway effect. The results provide new insights of HCD in FinFET, which are helpful to circuit design for reliability.

In this paper, it is reported for the first time that, in nanoscale high-k/metal-gate MOSFETs, the hot carrier degradation (HCD) follows a two-stage law in some stress conditions. Both interface traps and oxide traps contribute to HCD causing its time-dependence varies with different stress modes. The results are helpful for the physical understanding of HCD in nanoscale devices.

Metal oxide semiconductor thin-film transistors (TFTs) have been recognized as the most promising technology in the field of flexible electronics and flat-panel displays because of their high mobility, low-temperature fabrication process, and spatial uniformity of device characteristics. In this chapter, we review the development and operating principles of the metal oxide semiconductor TFTs, as well as the compact-modeling framework. For both the non-degenerate and degenerate conductions, the core compact models, including the analysis of surface potential and drain current, are discussed and compared. To enhance the computational efficiency of the calculations, an explicit and closed-form scheme for the surface potential solution is developed by including both exponential deep and tail states. The resulting DC and surface potential models give accurate descriptions with single-piece formulas, which are suitable for CAD applications. The numerical simulation and experimental results are also included in order to assess the validity of the models introduced.

In this paper, the impacts of interface traps on tunneling FET (TFET) are examined in terms of different trap energies and distributions, charge neutrality level (CNL), and effects of random trap fluctuation, in comparison with MOSFET. It is found that the Vth shifts and subthreshold swing (SS) degradation induced by interface traps in TFET and MOSFET have the same trends, but the impacts on ION are different because of the novel conduction mechanism of TFETs when compared with MOSFETs. Moreover, nTFET is intrinsically more immune (or susceptible) to Vth shift induced by acceptor(or donor-) type interface traps than nMOSFET. Therefore, reducing the potential degradation induced by the interface traps can be achieved by optimizing the position of CNL. The results indicate that nTFET is more immune to the Vth shift than nMOSFET with CNL below a critical energy. In addition, the trap-induced SS degradation of TFET is severer than MOSFET in electrostatics. Moreover, it is found that the ION, Vth, and IOFF fluctuations in nMOSFET and nTFET are also dependent on the position of CNL. With CNL below the critical energy, the ION fluctuation and Vth fluctuation of nTFET are smaller than those of nMOSFET. The results are helpful for the interface optimization of TFETs.

In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated by theoretical modeling and simulation. In this paper, process-dependence of the correlation between LER and LWR is studied. The experimental results indicate that both Si Fin and nanowire have strongly correlated LER/LWR, and the cross-correlation of two edges depends on the fabrication process. Based on the improved simulation method proposed in the Part I of this paper, the impacts of correlated LER/LWR in the channel of double-gate devices are investigated. The results show that Vth distribution strongly relies on cross-correlation, and can exhibit non-Gaussian distribution and/or multipeak distribution, which enlarges the Vth variation.

In this paper, a CMOS compatible silicon nanowire (Si NW) fabrication method on bulk silicon substrate is carried out using the self-limiting oxidation (SLO) to accurately control its size and cross-sectional shape. A predictive model for the 2-D SLO of Si NWs is presented. In this model, both the reduced reaction rate and diffusivity result in the oxidation rate degradation. The orientation dependence and the deformation of silicon core and oxide shell are further discussed here. The modeling results show good agreement with the experimental data within a wide range of oxidation temperatures, oxidation time, and various initial silicon core sizes. This model provides useful process design guidelines for Si nanostructures, especially in controlling the final diameter and cross-sectional shape of Si NWs from the top-down approach.

In this paper, the impacts of device short-channel effects (SCEs) on the random threshold voltage (V TH) variation in nanoscale bulk MOSFETs are investigated. Firstly, the direct relationship between SCEs and random variations are examined. By adopting the electrostatic integrity (EI) as the index for SCEs, clear correlations of device SCEs with random V TH variations are observed, which indicate that the random variations can be reduced by simply improving the SCEs in MOS devices with the same channel doping. In addition, the random dopant fluctuation (RDF) induced σ Vth has a linear relationship with EI and channel doping. Then, considering the contribution of SCEs on RDF modeling, a new normalization method of X VT plot is proposed, which provides a physical way to analyze random V TH variation in nanoscale MOSFETs with different process/device parameters (i.e., with different electrostatic designs).

In nanoscale MOSFETs with narrower width, the random telegraph noise (RTN) is conspicuous during the device aging caused by negative bias temperature instability (NBTI), which leads to difficulty for accurate assessment of end-of-life variability. Based on fast voltage stepping stress (FVSS) technique to predict the long-term degradation, an improved extraction method is proposed for eliminating the impact of RTN. As a result, the long-term and end-of-life variability can be predicted more precisely in ultra-narrow devices.

The frequency dependence of oxide trap coupling effect in nanoscale MOSFETs under AC switching condition is discussed thoroughly, with experimental and theoretical studies. By using AC STR measurement, a decreased tendency of trap coupling strength with increased frequency is observed. Rather than conventional 2-state trap model, it is found that only the explanation based on complete 4-state trap model is a reasonable interpretation, verified by Monte-Carlo simulation. The impacts of trap coupling frequency characteristics on digital circuits are also evaluated, showing a frequency-dependent underestimation of transient circuit performance if ignoring the above effect.

For the first time, two different types of electron traps are clearly identified in Ge nFETs with Type-A controlled by the HfO 2 layer thickness and Type-B by the Si growth induced Ge segregation. Only Type-B are responsible for mobility degradation and they do not saturate with stress time, while the opposite applies to Type A. A PBTI model is proposed and validated for the long term prediction.

In this paper, a modified 4-state trap model (4SM) is proposed and adopted in practical simulations including measurement delays, which can well explain the different frequency dependences of single oxide trapping and AC NBTI observed in experiments. The results also indicate the most probable activation energy of high-κ gate oxide traps, which is helpful for deep understanding of the physical origin and the impact of trapping/detrapping in nanoscale MOS devices under different frequencies.

This paper gives an outline of our recent findings on the random telegraph noise (RTN) in nanoscale MOS devices and circuits.

A simple device-level characterization method to decompose the amplitudes of different random variation sources in FinFET technology is proposed for the first time. The impacts of the major two categories of random variation sources: metal gate granularity (MGG) and line-edge roughness (LER) on V th variation are decomposed based on the differences in the physical mechanisms. The proposed method is verified based on 14nm FinFET platform. This work can provide helpful guidelines for future variation-aware technology development.

A CMOS compatible method to fabricate non-planar silicon nanowires is realized on bulk silicon substrate using self-limiting oxidation with high control-capability of the nanowire size and shape. A predictive model of 2-D self-limiting oxidation for non-planar silicon nanodevices is also proposed and shows its good agreement with the experimental data in a wide range of oxidation temperatures, process time, and variety initial silicon core sizes. The shape evolution of silicon core during oxidation is successfully modeled and is verified by high-resolution SEM. Unlike traditional planar oxidation model which is limited in planar oxidation without any stress, the proposed predictive model is based on cylindrical Deal-Grove (D-G) equation including stress effect, and takes into account of the orientation dependence and the flow of SiO2 as viscous fluid, which can be successfully applied to process engineering of non-planar Si nanowire transistors.

In this paper, an analytical model for parasitic gate capacitances in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is developed for the first time. A practical 3-D architecture of SNWTs with surrounding-gate cylindrical channel and source/drain extension regions is taken into account in the parasitic gate capacitance modeling. The parasitic gate capacitances of the SNWT are divided into four parts: 1) outer fringe capacitance Cof; 2) inner fringe capacitance Cif; 3) overlap capacitance Cov; and 4) sidewall capacitance Cside. The 3-D capacitance system is calculated by useful methods such as the equivalent transformation and inversion of Schwarz-Christoffel mapping. The obtained model agrees well with the results of 3-D electrostatic numerical simulations. The results show that the proportion of parasitic gate capacitances in the total capacitance is increased in this gate-all-around architecture due to the ultrasmall dimension of the SNWT channel; thus, the proportion of the intrinsic capacitance is reduced. Among the capacitances, Cof is found to be the largest contributor to the total parasitic gate capacitance in FO1 delay calculation, and Cside manifests itself as a nonnegligible parasitic capacitance. The developed capacitance model can be easily incorporated into a compact core model of SNWTs for further device/circuit design optimizations with various device parameters.

In this brief, the silicon nanowire transistor (SNWT)-based circuits of current mirrors (NWCMs) have been successfully fabricated for the first time. The key figures of merit of current mirrors (CMs) are experimentally studied, including output voltage coefficient (OVC), output resistance, and dc matching error e. The experimental results indicate that, due to the unique quasi-1-D transport properties of the SNWTs, NWCMs exhibit superior performance than planar metal-oxide-semiconductor-field-effect-transistor-based CMs (PCMs) in the inversion operation region. Furthermore, NWCMs operating in the subthreshold region shows even better performance than PCMs. With the inherent advantages of the gate-all-around structure, the SNWT is very promising for analog and mixed-signal integrated circuits and particularly has its unique potential at subthreshold operation for low-power applications.

The silicon nanowire transistor (SNWT) with gate-all-around (GAA) structure can be considered as one of the potential candidates for ultimate scaling due to its superior gate control capability and improved carrier transportation property. In this paper, hot carrier injection (HCI) and negative bias temperature instability (NBTI) behavior of n-type and p-type SNWTs with top-down approach is discussed. In addition to initial fast degradation and quick saturation of NBTI stress behavior, non-negligible impacts of electron traps on the stress/recovery characteristics in p-SNWTs with metal gate is found and characterized with a kind of combined I g – I d RTN technique. The NBTI behavior is modeled taking account of the impacts from unique structural nature of GAA SNWTs. NBTI induced performance degradation of the typical nanowire-based circuits is estimated based on the proposed model. In addition, stochastic degradation induced by single/few trap in the thin-body SNWTs is observed and analyzed.

The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated in this paper. First, the main variation sources in SNWTs are overviewed, with the detailed discussion on the specific sources of NW cross-sectional shape variation, random dopant fluctuation in NW source/drain extension regions and NW line-edge roughness (LER). Then, following the measurement-modeling approach, via calibrated statistical simulation that is based on the modified analytical model for GAA SNWTs with corrections of quantum effects and quasi-ballistic transport, the variability sources in SNWTs are experimentally extracted from the measured devices with 10-nm-diameter NW channels and TiN metal gate. The results indicate that NW radius variation and metal-gate work function variation dominate both the threshold voltage and on-current variations due to the ultrascaled dimensions and strong quantum effects of GAA NW structure. The NW LER also contributes, but relatively less, to the threshold voltage variation.

In this paper, the negative-bias temperature instability (NBTI) in p-type gate-all-around silicon nanowire MOSFETs (SNWTs) is investigated for circuit aging analysis. Several important features of NBTI in SNWTs are discussed, including the impacts of 2-D hydrogen diffusion, the nonuniform temperature profile caused by self-heating effects, the multiple crystallographic orientations of nanowire channel surface, the gate-trimming process-induced additional trapping effects, and the impacts of oxide hole trapping. A predictive NBTI model for SNWTs is proposed and adopted in circuit simulation to evaluate the performance degradations of typical logic and analog circuits, such as inverter, static random access memory cell, ring oscillator, and current mirror. Without considering other indirect factors, the results indicate that the performance degradation directly due to NBTI alone is relatively small, i.e., within the range of less than 8% degradation for the typical circuits simulated. However, the NBTI behavior in SNWTs is sensitive to process variations, which cause enhanced variability problem by inducing time-dependent threshold voltage fluctuations.

The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most efficient in improving the driving current and RF performance of n-SNWTs under the same stress value. In addition, the transverse compressive strain is also beneficial to the performance improvement, and can be combined in the stress engineering. Particularly, transverse biaxial compressive strain can effectively enhance the driving current, and at the same time slightly decrease the off-current of n-SNWT, which is beneficial for high speed and low power design. The results indicate that, due to the unique feature of gate-all-around 1D structure, the strain design in SNWTs, especially the combination of longitudinal strain and transverse strain, can be specially optimized for better device performance.

Shape controllable silicon nanowires (SiNWs) have been fabricated with CMOS compatible top-down fabrication process by carefully designing the oxidation temperature, time, and the original shape of Si wires. Higher oxidation temperature favors the formation of circular SiNWs, since the impact of oxidation retardation on the oxidation rate at sharp corners is reduced, and the discrepancy between the oxidation rates of different SiNW planes is minimized. In our work, high quality circular SiNWs with diameter of 5 nm have been successfully fabricated at high oxidation temperature of 950 °C. Pentagonal, triangular, and circular SiNWs with diameter around 10 nm have also been obtained at 950 °C by controlling the oxidation time and the original shape of the wires.

In this paper, the effects of nanowire line-edge roughness (LER) in gate-all-around silicon nanowire MOSFETs (SNWTs) are comprehensively investigated through 3-D statistical simulation. The LER impacts on both the device performance variation and mean value degradation are discussed in detail. Due to the unique nature of a nanowire structure, the LER in SNWTs contains two degrees of freedom, which allows the nanowire edges to vary in arbitrary transverse direction and which is different from the LER in traditional devices with one degree of freedom. In order to identify the relative importance of the diameter and center position variations, the nanowire LER can be considered as the combination of two basic types: One has a varied diameter with a fixed center (type A), and the other has a varied center position with a fixed diameter (type B). The results indicate the tradeoff between these two types of LER, with type A of a larger performance variation and type B of a larger performance degradation. Furthermore, as the gate length Lg shrinks below the correlation length Λ of the nanowire LER, the impacts from the source/drain extension region will dominate the variation. The impact of the main LER parameters is discussed for the scaled case with a non-Gaussian distribution in the device electrical parameters observed, and a new statistical method is proposed for better evaluation. On the other hand, the performance variation becomes insensitive to the correlation length in the case of Λ > Lg, which indicates a higher tolerance for the nanowire LER design in ultrascaled SNWTs. The optimized LER parameters are also given for the nanowire LER design with acceptable performance variation and suppressed mean value degradation in SNWTs.

A new method to fabricate high-performance gate-all-around silicon (Si) nanowire transistors (SNWTs) based on fully Si bulk (FSB) substrate is proposed and demonstrated by both simulation and experiments in this paper. Due to the large fan-out and deep junction of Si source/drain (S/D) region connecting with the bulk substrate, the FSB SNWTs can effectively alleviate the self-heating effects with technology scaling. Thermal behavior of multiwire SNWTs is investigated and FSB SNWTs show superior self-heating immunity to SNWTs based on Si-on-insulator (SOI) substrate (SOI SNWTs). In addition, the bottom parasitic transistor can be well suppressed in this structure. Although FSB SNWTs have larger gate parasitic capacitance, the CV/I is found to be comparable to the SOI SNWTs. With self-aligned, fully epi-free compatible CMOS processes, this new architecture was successfully fabricated, which exhibit high on-off current ratio of 2.6 × 108 due to better heat dissipation and low S/D resistance realized in this structure.

Gate-all-around silicon nanowire transistor (SNWT) can be considered as the potential candidate for highly scaled devices. This paper mainly discusses a new process integration scheme, which features bulk substrate based, epi-free integration, self-aligned structure and large source/drain fan-out. The characteristics of the fabricated device with 10nm diameter nanowire were investigated. The transport behavior of the SNWTs is experimentally estimated, with a modified experimental extraction methodology for SNWTs given, which takes into account the impact of temperature dependence of parasitic resistance. The sub-40nm SNWTs exhibit high ballistic efficiency at room temperature. Self-heating effect is also experimentally characterized and due to the 1-D nature of nanowire and increased phonon-boundary scattering in GAA structure, the self-heating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected.

Gate-all-around (GAA) Si nanowire SONOS memory cells (SNWMs) have been fabricated on Si substrate using fully epi-free compatible CMOS technology. A parasitic bottom SONOS memory (PBM) was formed when the SNWM was fabricated on bulk Si substrate. The impact of the PBM on the performance of the SNWM is investigated in this paper. The PBM shows a slower program speed, a faster erase speed, and worse retention characteristics than the SNWM. Therefore, the PBM severely degrades the performance of the SNWM due to its slower program speed and worse retention characteristics, and should be carefully controlled for the SNWM based on bulk Si substrate.

Low-frequency noise (LFN) in n-type silicon nanowire MOSFETs (SNWTs) is investigated in this letter. The drain-current spectral density exhibits significant dispersion of up to five orders of magnitude due to the ultrasmall dimensions of SNWTs. The measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed. At high drain current, however, the input-referred noise spectral density increases rapidly with the drain current, which indicates the significant impact of the ultranarrow source/drain extension regions of SNWTs. As a result, design optimizations to reduce the impact of parasitic resistance in SNWTs are necessary for analog/RF applications.

A new body-on-insulator (BOI) FinFET device structure based on bulk-Si substrate has been proposed and experimentally demonstrated in this paper. In comparison with other bulk FinFETs, the BOI FinFET features the localized insulator below the Si-Fin body, which can achieve both low source/drain (S/D) parasitic resistance and effective suppression of the S/D leakage beneath the Si-Fin channel, as well as good heat dissipation capability. The device fabrication process is basically compatible with conventional CMOS technology. High drive current, low subthreshold swing, and excellent short-channel behavior are observed in the fabricated BOI FinFETs.

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shur's model. The physical understanding of the apparent mobility in SNWTs is also discussed using flux's scattering matrix method.

The design of silicon nanowire MOSFETs (SNWTs) for RF applications is discussed in this paper based on 3-D simulation, including the impacts of the parasitic capacitances and resistance. The results indicate that large parasitic capacitances are a dominant factor for nanowire structure, which can significantly degrade the ac characteristics of SNWTs. Resistance of the ultranarrow source/drain extension (SDE) regions, which is the main contributor to the total series resistance of SNWTs, is another important factor influencing the device performance. The requirement of contact resistance of source/drain regions in SNWTs is relatively relaxed compared to the SDE regions. Considering the tradeoff between parasitic capacitances and resistance, optimization of the doping profile in SDE regions of SNWTs with 10-nm gate length is further investigated for RF applications.

In this letter, negative bias temperature instability (NBTI) in silicon nanowire field-effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires. In long-channel SNWFETs, a fast degradation and a quick saturation of NBTI are observed and discussed. In short-channel SNWFETs, a large fluctuation of NBTI is observed, which mainly originates from the ultrasmall gate areas of the short-channel SNWFETs and the statistical nature of randomly trapped charges in the oxide and at the Si/SiO2 interface. Techniques to suppress the fluctuation and characterize the intrinsic NBTI in ultrasmall SNWFETs are proposed and discussed. A recently developed online gate current method is demonstrated, which effectively alleviates this NBTI fluctuation in SNWFETs.

In this paper, the characteristics of a localized-SOI (L-SOI) MOSFET are investigated for analog/RF applications. In the L-SOI device, the source/drain regions are quasi-surrounded by L-type oxide layers to reduce junction capacitance and avoid source/drain punchthrough, while the channel is directly connected with the substrate to alleviate the self-heating effect. Such structures can combine the advantages of both bulk and SOI MOSFETs and avoid their issues. Due to the unique structure of this novel device, the L-SOI MOSFET can exhibit excellent analog/RF behaviors. Higher g m / I ds ratio and intrinsic gain (g m / g ds)can be received compared with the conventional SOI structure, particularly at low gate bias. Higher and , which are due to higher g m and reduced gate capacitance, can be observed in the L-SOI MOSFET. In addition, better noise performance can be achieved resulting from reduced lattice temperature and improved g m . Thus, the L-SOI MOSFET can be considered as one of the potential candidates for analog/RF applications.