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The indium phosphide (InP) 130 nm double-heterojunction bipolar transistor (DHBT) offers milliwatts of output power and high signal amplification in the lower end of the terahertz frequency band when the transistor is used in a common-base configuration. Instrumentation can directly benefit from this technology by enabling the development of novel broadband sources or synthesizers that rely on our ability to amplify the signal over enormous bandwidths. However, the design of high gain and stable amplifiers presents many obstacles and limitations as we increase the bandwidth and the carrier frequency. Here we show that adding a series resistor at the collector terminal of the common-base transistor prevents instabilities in the terahertz monolithic integrated circuit (TMIC) amplifier and increases its fractional bandwidth. Adopting this technique, we report a state-of-the-art broadband common-base amplifier that exhibits a minimum small-signal gain of 18.9 dB from 325 GHz to 477 GHz. This amplifier presents the highest fractional bandwidth and gain above 300 GHz. Our work demonstrates the feasibility of high-performance amplifiers that address the need of future terahertz electronic systems.

We present a record collector efficiency (54%) and PAE (46%) at 47 GHz for a 250-nm InP HBT power amplifier (PA). Reactively tuned transistor cells using a multi-section hybrid distributed-lumped matching network realize high PAE. The reported PA delivers up to 120 mW at 47 GHz while operating from a 2.75 V power supply. The measured PAE is the highest reported at 47 GHz.

Two high-gain, high power-added-efficiency (PAE) G-band solid-state power amplifier (SSPA) MMICs operating between 160–183 GHz are reported. Both utilize an identical five-stage gain-lane, and on-chip combining of these gain-lanes satisfies the output power (Pout) objectives. The first result is a 0.24-W PA using 4-way power combining. S21 mid-band gain is 21.0 dB and DC power dissipation (P DC ) is 3.05-W. The 3-dB S21 bandwidth (BW) is between 158.5-182.8 GHz. At 170-GHz, peak Pout is 244-mW (7.5% PAE). Pout is no less than 0.20-W between 160–180 GHz and is 177-mW at 183-GHz. The 170-GHz OP 1dB 1-dB gain compression is 120-mW (3.8% PAE). This PA result improves upon the prior state-of-the-art by 2.2-2.8× for peak SSPA power. The second result is a 0.14-W PA using 2-way combining. S21 mid-band gain is 23.6 dB and P DC is 1.35-W. The 3-dB S21 BW is between 161.0-184.8 GHz. At 170-GHz, peak Pout is 140-mW (9.50% PAE), and Pout is 116–140 mW (8.0-9.5% PAE) between 160–183 GHz. The 170-GHz OP 1dB is 70-mW (5.1% PAE). This PA result improves upon the prior state-of-the-art by 1.4-1.6× for peak SSPA power. This work establishes new SSPA RF power, gain, and PAE performance benchmarks at 160–183 GHz operation using a 250-nm InP HBT technology.

In this letter, we report on GaN-based field-effect transistors with laterally gated two-dimensional electron gas (2DEG). The drain current of the transistor is controlled solely by modulating the width of the 2DEG between buried gates. The lateral Schottky gate contact to the GaN channel layer enhances electron confinement by raising electrostatic potential below the 2DEG, improving isolation between the source and drain. Complete elimination of a top-contact gate reduces the density of trapped electrons near the surface and alleviates capacitive coupling between the trapped electrons and the 2DEG. Owing to the unique device structure and operation principle, the 150-nm-gate transistors with a channel width of 250 nm demonstrated: extremely small output conductance, drain-induced barrier lowering, knee voltage, and knee current collapse, greatly reduced ${g}_{m}$ derivatives near threshold, and nearly constant RF gain along the resistive load line. Furthermore, a preliminary accelerated life test indicated enhanced device reliability due to an absence of the inverse piezoelectric effect. The proposed transistors hold great promise for realizing reliable and efficient power amplifiers with improved transistor linearity.

We report here a compact 140-GHz, 150-mW high-gain solid-state power amplifier (SSPA) monolithic microwave integrated circuit (MMIC) demonstrated in a 250-nm InP HBT technology. It utilizes five-gain stages and two-way on-chip power combining. The amplifier measures 29.5-dB mid-band $S_{21}$ gain and over 125-mW output power across 115–150-GHz operation. The peak 153-mW output power was measured at 140 GHz using only 2.7-mW RF input power—the associated large-signal gain is 17.5 dB with 9.8% power added efficiency (PAE). The 140-GHz OP1 dB 1-dB gain compression power is 106 mW with 7.0% PAE. The dc power dissipation is 1.54 W and its size is only 0.75 mm2. The 3-dB $S_{21}$ gain roll-off is between 112 and 147 GHz. The 115–150-GHz output power variation at 0-dBm input drive is only ±0.5 dB. The peak PAE varies between 8.2% and 10.5%. This D-band result improves upon by $2.3\times $ at 140 GHz the state-of-the-art peak RF power previously demonstrated by SSPA MMICs.

Highly scaled indium phosphide (InP) heterojunction bipolar transistor (HBT) technologies have been demonstrated with maximum frequencies of oscillation ( $f_{\max}$ ) of >1 THz and circuit operation has been extended into the lower end of the terahertz (THz) frequency band. InP HBTs offer high radio-frequency (RF) output power density, millivolt (mV) threshold uniformity, and high levels of integration. Integration with multilevel thin-film wiring permits the realization of compact and complex THz monolithic integrated circuits (TMICs). Circuit results reported from InP HBT technologies include: 200-mW power amplifiers at 210 GHz, 670-GHz amplifiers and fundamental oscillators, and fully integrated 600-GHz transmitter circuits. We review the state of the art in THz-capable InP HBT devices and integrated circuit (IC) technologies. Challenges in extending transistor bandwidth and in circuit design at THz frequencies will also be addressed.

In this paper we review the status of the state-of-the-art and our transition activities for mm-wave, D-, and G-band solid-state power amplifier (PA) MMICs developed into Teledyne Scientific’s 250-nm InP HBT technology. Key design decisions driven by the transistor gain at a given frequency and large-signal load-line are reviewed. Novel PA cell topologies are presented to show how they address the high current biasing required of the 250-nm InP HBT and permit 2× and 4× on-chip combining. PA wafer-mapping by auto-probing on a full thickness 100-mm wafer prior to finishing (thinning to 3-mil, chip singulation) permits the RF identification of known-good-die (KGD) and thus an inventory of parts can be generated. Five established 250-nm InP HBT power amplifiers are presented operating from 55-135 GHz (115-135 mW), 60-130 GHz (160-275 mW), 115-145 GHz (0.25-W @ 140-GHz), 115-185 GHz (75-115 mW), and 180-250 GHz (40-80 mW). Also, included is a novel 190-GHz low-power driver amplifier (high-gain, 100-mW P DC , 3-dBm OP 1dB , 11-dBm P sat with 9.6% PAE).

We report Monte Carlo simulation results of 300nm InP heterojunction bipolar transistors driven to exhibit distortion. IM3 distortion is typically explained by collector velocity modulation. Full-band ensemble Monte Carlo simulations implicate intervalley transfer as an additional source of distortion under conditions of high current, low voltage, and high doping. Simulations reveal that intervalley transfer promotes the formation of traveling accumulation domains which result in high frequency distortion more significant than that caused by velocity modulation. Special care must be taken when designing high current HBT power amplifiers in order to mitigate this effect.

We report here a 250-nm InP HBT based wideband power amplifier that operates between 110-190 GHz and fully covers D-band (110-170 GHz). It utilizes 5-gain stages and 2-way on-chip power combining. The amplifier demonstrates 25.2-dB S21 mid-band gain and 68-117 mW output power between 110190 GHz. The fractional bandwidth associated with 1-dB and 3- dB S21 gain roll-off are 35% (54-GHz) and 43% (66.5-GHz), respectively. The fractional large-signal power bandwidth associated with highest power between 110-190 GHz is 53%. Under small, medium, and large-signal operation, the PA is most efficient between 115-185 GHz – at 3-dBm input power, 73-104 mW output power (5.0-7.5% PAE) is demonstrated over this frequency span. This result represents a significant increase to the state-of-the-art for a mm-wave solid-state power amplifier operating across D-band and a significant fraction of G-band in the simultaneously demonstrated metrics of high output power (by 3-4× higher), bandwidth, gain, and gain flatness.

We report on GaN-based field effect transistors with laterally-gated multiple 2DEG channels, called BRIDGE FETs (buried dual gate FETs). Unique operation principle of the transistors demonstrated unprecedented device characteristics suitable for efficient and linear millimeter-wave power amplifier applications. Multiple 2DEG channels formed in AlGaN/GaN and AlN/GaN material systems are compatible with the BRIDE FET structure, adding design flexibility for an increased drain current density with higher frequency performance. The BRIDGE FET fabricated on a 4-channel epi structure with a net 2DEG density of 1.2×1013 cm-2 exhibited 1.7× higher saturation current density than those on a single-channel with the same 2DEG density. This is attributed to a higher saturation velocity of 2DEG with a lower density per channel. Finally, hexagonal micro-scale device cells consisting of segmented BRIDGE FETs construct a power amplifier (PA) unit cell, where distributing heat sources uniformly over an entire PA cell area maximizes its area power density while minimizing a rise of the peak junction temperature.

Velocity overshoot in heterojunction bipolar transistors has long been recognized to significantly reduce collector signal delay below that predicted under the assumption of a constant saturated electron velocity [1], [2]. This phenomenon has proven critical for high frequency operation of InP DHBTs which has resulted in cutoff frequencies above 1 THz [3]. In order to better understand the operation of these devices, we further explore the microscopic electron dynamics through simulation. We report modulated collector signal delay results from static and dynamic full band ensemble Monte Carlo simulation of a 300nm InGaAs/InP DHBT with a 300 nm collector.

Two high-gain, broadband power amplifier MMICs are reported. The first result is a 140-GHz 0.25-W PA. It utilizes 5-gain stages and 4-way power combining. S 21 gain is 29.4-dB. It demonstrates over 0.21-W P out across 110-150 GHz. 0.25-W P out at 140-GHz requires 4-dBm P in – the associated gain is 16-dB with 7.0% PAE. The 140-GHz OP 1dB 1-dB gain compression is 171-mW with 4.9% PAE. The 3-dB S 21 bandwidth (BW) is between 112-148 GHz. This result improves state-of-the-art by 65% at 140-GHz for peak SSPA power. The second PA result is a 55-135 GHz 115-135 mW PA. It utilizes 4-gain stages and 2-way power combining. Its operation fully covers WR15 (50-75 GHz) to WR08 (90-140 GHz) bands. S 21 gain is 27.3-dB. The S 21 fractional BW at 1-dB and 3-dB gain roll-off are 63% and 81%. Large-signal BW associated with high power and gain between 55-135 GHz is 84%. P out variation over this span at 3-dBm P in is only 11.2% (±13-mW). This result improves state-of-the-art for mm-wave PA’s where simultaneously high P out , fractional BW, gain, and gain flatness are required.

Due to its remarkably high Johnson figure of merit, gallium nitride (GaN) has become the material of choice for applications requiring high output power at high frequencies. In this paper, we have reviewed high-speed switching work to date and we demonstrate a 28 V, 865-MHz switching speed step-down converter that can be applied to envelope tracking (ET). We report a GaN monolithic microwave integrated circuit technology utilized to fabricate a gate driver IC at a switching speed >1 GHz with 100 V breakdown GaN power switch. The on-chip integration of the power switch and gate driver allows in-circuit characterization of the power switch switching speed. Using the integrated gate driver and switch, we report a slew rate of the power switch of 152 V/ns at 50 V, which enables a down converter IC capable of ET with over 50-MHz tracking bandwidth. This paper shows the first demonstration of a GaN low-side gate driver capable of >1-GHz switching, monolithic integration with a 0.15- $\mu \text{m}$ T-gate suitable for up to Ka-band operation, and a >100 V breakdown voltage power switch on the same chip.

We report two 325 GHz series-connected power amplifiers (PAs) using 130 nm InP HBT technology. The unit cell, using two series-connected transistors, produces 8.6 mW at 325 GHz and consumes 243 mW DC power. The PA has a 4.3 dB compressed gain and 2.2% power added efficiency (PAE). Two of these cells are then power-combined, and two further cells are used as driver stages, to form the second design, which produces 11.36 mW at 325 GHz with 9.4 dB compressed gain and 1.09% PAE. The peak small signal gain is 16.6 dB at 325 GHz, and the 3-dB bandwidth is 9 GHz. The total power consumed is 1.12 W and the dimensions including the pads are $0.98 \mathbf{mm} \times 0.98 \mathbf{mm}$ .

Compound semiconductor heterogeneous integration with silicon electronics offers new design opportunities for high performance microsystems. The indium phosphide (InP) material system is an attractive candidate for heterogeneous integration of both electronic and optoelectronic devices. For RF and mixed-signal integrated circuit (IC) applications, InP transistors offer the highest reported RF figures-of-merit, low transistor noise figure and high RF power density. We report on InP heterogeneous integration techniques performed at the wafer-scale using hybrid bonding and at the individual transistor level using micro-transfer printing. Both integration techniques maintain the native substrate transistor performance and have been used to demonstrate high performance millimeter-wave ICs (RF beamformers and power amplifiers).

InP double-heterojunction bipolar transistors (DHBTs) have demonstrated power gain cutoff frequencies $(f_{max})$ above 1THz under low collector voltage due to electron velocity overshoot in the InP drift collector [1] [2]. Under higher collector voltage, however, a quick onset of $\Gamma-\mathrm{L}$ scattering limits the average electron velocity to the saturation velocity (Fig. 1(a)-(c)), leading to a Johnson's figure-of-merit (JFOM) second to GaN HEMTs and a limited transistor power bandwidth for InP DHBTs [3]. Here we propose a velocity-engineered device structure called the segmented-collector DHBT (SC-DHBT) that incorporates p-type scattering layers within the drift collector to reduce the electron kinetic energy and force a greater electron distribution into the low effective mass $\Gamma-$ valley for extended velocity overshoot (Fig. 3(a)). Transport simulations show the collector transit time $\tau_{c}$ is reduced from 1.23ps in the reference design to 0.90ps in a double scatterer design at $V_{cb}=5\mathrm{V}, J_{c}{=}$ 1mA/um2. The proposed SC-DHBT design is suited for large power bandwidth power amplifiers.

In this paper, H-band (220–325 GHz) power amplifier (PA) integrated circuits (ICs) are presented using 250-nm InP HBT technology, where a cascode topology was adopted to achieve high gain and high output power. Three PAs were designed: PA1 was implemented with two-stage cascode HBTs, PA2 combined two PA1s, and PA3 combined four PA1s, by using Wilkinson couplers without isolation resistors. Electromagnetic simulations were carried out for the accurate design of passive circuits such as a microstrip line, a capacitor, and RF pads. The measured insertion loss of the RF pad and Wilkinson coupler was as low as 0.24 dB and 0.70 dB, respectively, at 300 GHz. The three PAs exhibited a measured gain higher than 15 dB with good return losses at 300 GHz. The output powers scaled well with total emitter area of the PAs. PA3 exhibited a maximum output power of 13.5 dBm at 301 GHz. To the best of the authors' knowledge, this corresponds to the highest output power among the previously reported solid-state PAs in this frequency range.

We report an InP/InGaAs/InP double heterojunction bipolar transistor fabricated in a triple-mesa structure, exhibiting simultaneous 404 GHz fτ and 901 GHz fmax. The emitter and base contacts were defined by electron beam lithography with better than 10 nm resolution and smaller than 20 nm alignment error. The base-collector junction has been passivated by depositing a SiNx layer prior to benzocyclobutene planarization, improving the open-base breakdown voltage BVCEO from 3.7 to 4.3 V.

Highly-scaled Indium Phosphide (InP) transistor technologies have bandwidths extending into the terahertz (THz) frequency regime (0.3–3 THz). The high transistor bandwidth can be exploited to both extend circuit operation to THz frequencies and improve system performance at millimeter wave and sub-millimeter wave frequencies. InP heterojunction bipolar transistor (HBT) technologies offer wide bandwidths, high RF power handling and the capability to realize high levels of integration. We review integrated circuit (IC) results from Teledyne's InP HBT technologies that span frequencies from 60 GHz to >600 GHz focusing on performance benefits and applications.

X-band power performance of N-polar GaN HEMTs is reported, including 2-tone results at 10GHz that demonstrate an OIP3/P DC linearity figure of merit of 12dB at a drain voltage of 20V, utilizing tuning of fundamental, second and third harmonic terminations. Compared to available linearity results of GaN HEMTs at 10GHz, the device technology presented here demonstrates the best such ratio reported at 10GHz for any GaN HEMT to date. The N-polar HEMT device exhibits very low 3rd order intermodulation distortion as well as single-tone high power-added efficiency (PAE) of ∼65% with an associated power density of 3W/mm that scales favorably with a drain voltage of 15V. These results show the suitability of N-polar GaN HEMTs for high performance X-band transceiver systems.

We report here two 250-nm InP HBT power amplifiers operating between 180–265 GHz. A 3-stage, 8-PA cell combined design demonstrates S21 gain exceeding 25-dB between 202–257 GHz and 20-dB between 194–265 GHz. Peak output power is 140-mW at 200-GHz with 14.7-dB gain and 5.1% PAE. The PA P sat RF power is at least 100-mW from 190–235 GHz, 82-mW from 183–245 GHz, and 50-mW from 183–263 GHz. This represents 80-GHz large-signal bandwidth from this design. A 3-stage, 16-PA cell combined design demonstrates S21 gain exceeding 24-dB between 200–255 GHz and 20-dB between 194–262 GHz. Peak output power is 248-mW at 200-GHz with 9.0-dB gain and 4.1% PAE. The PA P sat RF power is at least 200-mW from 195–215 GHz, 170-mW from 190–220 GHz, and 100-mW from 185–255 GHz. This represents 70-GHz large-signal bandwidth from this design. These InP HBT amplifier chips represent improvements to state-of-the-art in the following areas: 13% increase to the maximum PA power reported above 200-GHz, first reported 200-mW PA power with 20-GHz (195–215 GHz) operation, highest PA power reported above 240-GHz, first demonstrated 100-mW power to 255-GHz, and 70-GHz (16-cell PA) and 80-GHz (8-cell PA) bandwidth covering most of the WR04 waveguide frequency band.

We present a new millimeter-wave power-combining technique using transmission-line baluns which both connect transistor outputs in series and inductively tune the transistor output capacitances. The baluns are much shorter than a quarter-wavelength (λ/4), hence are more compact and have less insertion loss than a λ/4 balun. We introduce one topology providing an even number of series connections, including 2:1 and 4:1, and a second topology providing either an even or odd number of series connections. We then analyze segmented transformer power-combiners as a set of multi-conductor transmission-lines, and explore the relationship between transformer and transmission-line balun power-combiners. We demonstrate the technique with 2:1 and 4:1 series-connected designs implemented in a 0.25 μm InP HBT process. At 86 GHz, a single-stage power amplifier (PA) using the 2:1 baluns exhibits 30.4% peak PAE, 20.37 dBm output power (Pout) and 23 GHz 3-dB bandwidth from a 448 × 816 μm 2 die. A two-stage PA using the 2:1 baluns exhibits 30.2% PAE, and 23.14 dBm Pout from an 824 × 816 μm 2 die. At 81 GHz, a two-stage PA with 4:1 series output power-combining exhibits 23.4% PAE, and 26.7 dBm (470 mW) Pout from a 1,080 × 980 μm 2 die.

In this paper, we present an approach for characterizing transistors embedded in microstrip lines formed on a thin bisbenzocyclobutene-based (BCB) monomers film at sub-millimeter-wave wavelengths. We demonstrate the approach at frequencies up to 750 GHz and estimate the uncertainty of the procedure.

A 130 nm InP HBT IC technology has been developed capable of circuit demonstrations at > 600 GHz. Transistors demonstrate RF figures-of-merit f t > 500 GHz and f max > 1 THz. The HBTs support high current densities > 25 mA/μm2 with a common-emitter breakdown voltage BV ceo = 3.5 V. The technology includes a multi-level thin-film wiring environment capable of low-loss THz signal routing and high integration density. A large-signal HBT model has been developed capable of accurately predicting circuit performance at THz frequencies. Circuit demonstrations include fundamental oscillators and amplifiers operating at > 600 GHz as well as integrated transmitter and receiver circuits.

We present a high dynamic range W-band frequency conversion IC, incorporating a base-collector diode mixer and a 9:1 LO frequency multiplier, implemented in a 130 nm InP HBT technology. The IC was designed for a broadly tunable 1-22 GHz dual-conversion receiver using a 100 GHz first IF. In up-conversion, from 1-22 GHz to W-band, the IC has 7 dB conversion loss and 23 dB IIP3; in down-conversion, from W-band to 0.1-22 GHz, it has 8 dB conversion loss and 23 dBm IIP3. The IC tunes most of W-band (75-105 GHz) and consumes 2 W.

We present a fully-integrated 94 GHz transceiver front-end in a 130 nm / 1.1 THz fmax InP HBT process. Low power is obtained through low-voltage design and high transistor gain. The IC is designed for multi-function, dual-polarization phased arrays. At 1.5 V collector bias, in dual-polarization simultaneous receiving mode, the IC has 21 dB gain, < 9.3 dB noise figure, and consumes 39 mW, while in transmitting mode with time-duplexed vertical and horizontal outputs, the transceiver achieves 5 dBm output power, 22 dB gain, and consumes 40 mW. At 1.0 V bias, in dual-polarization simultaneous receiving mode, the IC has 22.7 dB gain, < 8.9 dB noise figure, and consumes 26 mW.

We present power amplifier ICs with a small-signal measured 3dB-bandwidth spanning from 24 GHz to 114 GHz, implemented in a 130 nm InP HBT process. The PAs were designed using sub-quarter wavelength transmission-line baluns for output matching and series power combining. The small signal gain is 15 dB and the DC power consumption is 800 mW in low power operation. The measured output power at 3-dB gain-compression varies between 16.5 dBm and 22dBm between 50 GHz and 100 GHz. The peak PAE is larger than 8 % over the same range. The saturated output power and PAE at 90 GHz are 21.95 dBm and 14.7 % respectively.

We present a high-linearity pseudo-differential W- band amplifier IC, implemented in a 130 nm InP HBT process in a 1.1×0.72 mm2 die. Correcting for test structure losses, the amplifier has a measured 21.9 dBm output-referred 3rd order intercept point (OIP3) and a single-stage gain of 6.4 dB at 100 GHz. The amplifier has a noise figure of 6.8 dB +/- 1dB at 95 GHz. The OIP3/Pdc ratio is 0.79 at 100 GHz. To the author's knowledge, these are among the first reported dynamic range measurements for W-band amplifiers.

Through aggressive lithographical and epitaxial scaling, the bandwidths of InP-based heterojunction bipolar transistors have been extended to THz frequencies. At 130nm emitter dimensions, transistors with maximum frequencies of oscillation (ƒ max ) of >1THz have been demonstrated with accompanying circuit demonstrations at 670GHz. At 250nm emitter dimensions, high efficiency and high power density mm-wave power amplifiers covering E-band (71GHz) to G-band (235GHz) have been fabricated. The utility of these high performance transistors can be further enhanced through heterogeneous integration with Si CMOS. We have demonstrated wafer-scale 3D integration of InP and Si using a low temperature oxide-to-oxide bonding process with embedded Cu interconnects.

Two solid-state power amplifiers with record high power added efficiency (PAE) and 100–130 mW output power in 250 nm InP HBT are reported. The 71–95 GHz PA demonstrates 20.7 dB S21 and 25 GHz 3-dB bandwidth at 432.5 mW PDC. Pout is 105–138 mW (21–36% PAE) and RF power density is 1.64–2.15 W/mm. At 81 GHz, 135.6 mW Pout is achieved with 36.0% PAE and 14.1 dB gain. At 81 GHz with reduced input-stage bias, 129.6 mW Pout is achieved with 40.0% PAE and 13.0 dB gain. The 96– 120 GHz PA demonstrates 17.8 dB S21 and 26 GHz 3-dB bandwidth at 442.4 mW PDC. Pout is 84.9–107 mW and RF power density is 1.33–1.64 W/mm. At 102.5 GHz, 98.1 mW Pout is achieved with 21.2% PAE and 12.1 dB gain. The results were obtained class-A DC biasing the PA's. The amplifiers utilizes a novel, compact, and stackable power cell topology for multi-finger HBTs operating at mm-wave and THz frequencies, where 8-way PA cell combining can be realized for future 0.6–0.8 W Pout designs - these designs are currently under development. This work represents record PAE for 100 mW PA's at these frequencies. 40% PAE at E-band (81 GHz) is demonstrated for the first time under class-A bias, as well as PAE greater than 23% across the 71–76, 81–86, and 92–95 GHz bands. The 18.9–22.5% PAE at 100 mW power for the 96–120 GHz PA is a 1.5–3× improvement to state-of-the-art PAE at these frequencies.

We verify a foundry model for state-of-the-art 250 nm heterojunction bipolar transistors with large-signal measurements. We demonstrate the propagation of correlated measurement uncertainties through the verification process, and use them to quantify the differences we observe in the measurements and models.

We report on the development of a 0.25-μm InP HBT IC technology for lower end of the THz frequency band (0.3-3 THz). Transistors demonstrate an extrapolated fmax of >;800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) >;4 V. The transistors have been integrated in a full IC process that includes three-levels of interconnects, and backside processing. The technology has been utilized for key circuit building blocks (amplifiers, oscillators, frequency dividers, PLL, etc), all operating at ≥300 GHz. Next, we report a series of fundamental oscillators operating up to 0.57 THz fabricated in a 0.25-μm InP HBT technology. Oscillator designs are based on a differential series-tuned topology followed by a common-base buffer, in a fixed-frequency or varactor-tuned scheme. For ≥400 GHz designs, a subharmonic down-conversion mixer is integrated to facilitate spectrum measurement. At optimum bias, the measured output power was -6.2, -5.6, and -19.2 dBm, for 310.2-, 412.9-, and 573.1-GHz designs, respectively, with PDC ≤ 115 mW. Varactor-tuned designs demonstrated 10.6-12.3 GHz of tuning bandwidth up to 300 GHz.

We report on a direct epitaxial growth approach for the heterogeneous integration of high-speed III–V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBT) structures were successfully grown on Si-on-lattice-engineered- substrate (SOLES) and Ge-on-insulator-on-Si (GeOI/Si) substrates using molecular beam epitaxy. Structurally, the epiwafers exhibit sharp interfaces and a threading dislocation density of 3.5×10 7 cm −2 as measured by plan-view transmission electron microscopy. HBT devices fabricated on GeOI/Si substrates have current gain of 55–60 at a base sheet resistance of 650–700 Ω/sq, and f t and f max of around 220 GHz. HBT structures with DC and RF performance similar to those grown on lattice-matched InP were also achieved on patterned SOLES substrates with growth windows as small as 15×15 μm 2 . These results demonstrate a promising path of heterogeneous integration and selective placement of III–V devices at arbitrary locations on Si CMOS wafers.

Two E-band (71-76GHz and 81-86GHz) solid-state power amplifiers in 250nm InP HBT are reported. The 71-76GHz PA demonstrates 13.3-16.2dB S21 gain and 33GHz bandwidth. Output power from 71-81GHz is > 360mW. At 76GHz, 439mW Pout (26.4dBm) is achieved with 12.1dB gain and 26.9% PAE - this corresponds to 1.14W/mm power density. The 81- 86GHz PA demonstrates 12.0-14.3dB S21 gain and 40GHz bandwidth. Output power from 76-86GHz is > 337mW. At 86GHz, 358mW Pout (25.5dBm) is achieved with 10.2dB gain and 23.6% PAE - this corresponds to 0.93W/mm power density. This SSPA utilizes a novel, compact power cell topology developed for multi-finger HBTs, which overcomes the inability of the RF output interconnects and combiners to carry the high DC bias currents required by the InP HBT PA cells in the thin-film microstrip interconnect. This work improves upon the state- of-the-art for InP HBT and GaN HEMT E-Band SSPAs by demonstrating higher simultaneous power by 1.0- 2.0dB and large bandwidths, where PAE is > 15-20% in continuous wave (CW) operation. The size of the PA's is small, both only 1.95mm x 0.88mm.

With transistors approaching scaling limits, demonstrating a record device demands ∼20–40 process steps, many at extreme resolution. Facing this, how might a Ph.D. student steer the future of VLSI or of wireless systems? Beyond exploring yet more new channel materials, whether 2D or 3D, we explore below other options.

We report common-base medium power amplifiers designed for G-band (140-220 GHz) and W-band (75-110 GHz) in InP mesa double HBT technology. The common-base topology is preferred over common-emitter and common-collector topologies due to its superior high-frequency maximum stable gain (MSG). Base feed inductance and collector emitter overlap capacitance, however, reduce the common-base MSG. A single-sided collector contact reduces Cce and, hence, improves the MSG. A single-stage common-base tuned amplifier exhibited 7-dB small-signal gain at 176 GHz. This amplifier demonstrated 8.7-dBm output power with 5-dB associated power gain at 172 GHz. A two-stage common-base amplifier exhibited 8.1-dBm output power with 6.3-dB associated power gain at 176 GHz and demonstrated 9.1-dBm saturated output power. Another two-stage common-base amplifier exhibited 11.6-dBm output power with an associated power gain of 4.5 dB at 148 GHz. In the W-band, different designs of single-stage common-base power amplifiers demonstrated saturated output power of 15.1 dBm at 84 GHz and 13.7 dBm at 93 GHz

This paper presents a new InP HBT structure with a collector pedestal under the HBT's intrinsic region by using selective ion implantation and MBE regrowth. This is the first such structure reported in III–V HBTs. Our results exhibit excellent DC performances including high current gain, low base–collector leakage current, and low collector access resistance. One-hundred and seventy gigaHertz ft and 130 GHz fmax were obtained. The RF performances were found to be limited by the regrowth interface charge accumulation. This is expected to be overcome by using compensating p-doping at the regrowth interface.

We report tuned amplifiers designed for the 140-220-GHz frequency band. The amplifiers were designed in a transferred-substrate InP-based heterojunction bipolar transistor technology that enables efficient scaling of the parasitic collector-base junction capacitance. A single-stage amplifier exhibited 6.3-dB small-signal gain at 175 GHz. Three-stage amplifiers were subsequently fabricated with one design demonstrating 12.0-dB gain at 170 GHz and a second design exhibiting 8.5-dB gain at 195 GHz.

Deep submicron transferred-substrate heterojunction bipolar transistors exhibit peaking and singularities in the unilateral power gain (U) at high frequencies. Unbounded U has been observed in some devices over a 20-110 GHz bandwidth. Associated with the effect are a strong decrease in collector-base capacitance with increased bias current, and negative conductance in the common-emitter output conductance G/sub 22/ and positive conductance in the reverse conductance G/sub 12/. Unbounded U is observed in devices operating at current densities as low as 0.56 mA//spl mu/m/sup 2/. A potential explanation of the observed characteristics is dynamic electron velocity modulation in the collector-base junction. A theoretical model for the dynamics of capacitance cancellation by electron velocity modulation is developed, and its correlation with experimental data examined.

A terahertz differential eight-stage amplifier fabricated using state-of-the-art 125 nm double-heterojunction bipolar transistors (DHBT) is presented. The four-port unit-cell chain is designed for optimum forward differential gain with no even and odd-mode reverse gains. Unbalanced single-ended feed networks are added to preserve the amplifier gain without inducing oscillations. The proposed feed scheme is validated by a stable amplifier operation in 325-to-450 GHz range with the peak gain of 22 dB at 375 GHz.

We present W-band power amplifiers which are designed using the sub-quarter-wavelength transmission line balun in a ring-shaped configuration and fabricated in a 0.25 μm InP DHBT technology. Operating at 86GHz, a single-stage PA exhibits 20.86dBm saturated output power with 10.2dB peak power gain, a recored PAE of 35% and a record 3-dB bandwidth of 33GHz. A two-stage PA exhibits 22.75dBm saturated output power with 20.4dB peak power gain, a PAE of 32.8% and a 3-dB bandwidth of 16GHz.

While the growth of III-As and III-P semiconductors is well-established, and their transport properties well-understood, the performance of high-frequency and VLSI electron devices can still be substantially improved. Here we review design principles, experimental efforts, and intermediate results, in the development of nm and THz electron devices, including nm InAs/InGaAs planar MOSFETs and finFETs for VLSI, InGaAs/InP DHBTs for 0.1-1 THz wireless communications and imaging, and ~5nm InAs/InGaAs Schottky diodes for mid-IR mixing.

We report a two-stage W-band power amplifier (PA) using novel 4.1 series power-combining with sub-quarter-wavelength baluns. The power amplifier, fabricated in a 0.25 μm InP HBT technology, produces 470 mW (26.7 dBm) output power at 81 GHz, 23.4 % peak PAE, and >11.5 GHz 3-dB bandwidth. The compact series power-combining networks permit a small 1.06 mm 2 die area and a high 443 mW/mm 2 output power per unit die area.

High bandwidths are obtained with heterojunction bipolar transistors by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. Narrow collector junctions can be obtained by using substrate transfer processes, or -if contact resistivity is greatly reduced -by reducing the width of the base Ohmic contacts in a mesa structure. HBTs with submicron collector junctions exhibit extremely high f max and high gains in mm-wave ICs. Logic gate delays are primarily set by depletion-layer charging times, and neither fτ nor f max is indicative of logic speed. For high speed logic, epitaxial layers must be thinned, emitter and collector junction widths reduced, current density increased, and emitter parasitic resistance decreased. Transferred-substrate HBTs have obtained 21 dB unilateral power gain at 100 GHz. If extrapolated at -20 dB/decade, the power gain cutoff frequency f max is 1.1 THz. Transferred-substrate HBTs have obtained 295 GHz f τ . Demonstrated ICs include lumped and distributed amplifiers with bandwidths to 85 GHz, 66 GHz master-slave flip-flops, and 18 GHz clock rate Δ-Σ ADCs.

The variation of heterojunction bipolar transistor (HBT) bandwidth with scaling is reviewed. High bandwidths are obtained by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. Narrow collector junctions can be obtained by using substrate transfer or collector-undercut processes or, if contact resistivity is greatly reduced, by reducing the width of the base ohmic contacts in a mesa structure. HBTs with submicron collector junctions exhibit extremely high f/sub max/ and high gains in mm-wave ICs. Transferred-substrate HBTs have obtained 21 dB unilateral power gain at 100 GHz. If extrapolated at -20 dB/decade, the power gain cutoff frequency f/sub max/ is 1.1 THz. f/sub max/ will be less than 1 THz if unmodeled electron transport physics produce a >20 dB/decade variation in power gain at frequencies above 110 GHz. Transferred-substrate HBTs have obtained 295 GHz f/sub T/. The substrate transfer process provides microstrip interconnects on a low-/spl epsiv//sub r/ polymer dielectric with a electroplated gold ground plane. Important wiring parasitics, including wiring capacitance, and ground via inductance are substantially reduced. Demonstrated ICs include lumped and distributed amplifiers with bandwidths to 85 GHz and per-stage gain-bandwidth products over 400 GHz, and master-slave latches operating at 75 GHz.

A compact monolithic integrated differential voltage controlled oscillator (VCO) using 0.5-/spl mu/m emitter width InP/InGaAs double-heterostructure bipolar transistors with a total chip size of 0.42 mm /spl times/ 0.46 mm is realized by using cross-coupled configuration for extremely high frequency satellite communications system applications. The device performance of F/sub max/ greater than 320 GHz at a current density of 5 mA//spl mu/m/sup 2/ and 5-V BVceo allows us to achieve a low phase noise 42.5-GHz fundamental VCO with -0.67-dBm output power. The VCO exhibits the phase noise of -106.8 dBc/Hz at 1-MHz offset and -122.3 dBc/Hz at 10-MHz offset from the carrier frequency.

A 214-230GHz solid-state power amplifier (SSPA) MMIC is presented, where at 227.5GHz it simultaneously demonstrates 101mW P,out at 14.0dB compressed gain (4.0mW P,in), with 4.04% PAE - these record SSPA MMIC values represent increases to state-of-the-art by 12% for P,out and 2.3× for PAE at these frequencies in an HBT technology. The maximum compressed Pout is 103mW at 13.1dB gain (5.0mW P,in) and 4.08% PAE. This 2-stage amplifier has 19-21dB S21 gain from 214-235GHz, with 3-dB S21 bandwidth of 240GHz. P,DC is 2.40W. Amplifier cells were fabricated from a 250nm InP HBT technology, jointly with a substrate-shielded, thin-film microstrip wiring environment using BCB. The 80-103mW P,out (214-230GHz) is achieved by 8-way (4-way × 2-way) combining eight cascode cells. Due to the gain of the cascode cell being 10-11dB, a four cascode cell combined predriver could be used to drive the amplifier output stage into saturation - this reduces to SSPA PDC and improves PAE. Across the SSPA bandwidth, the 2:1 and 4:1 power dividers/combiners exhibit only 0.4dB and 0.5dB loss respectively.

We present high-efficiency W-band power amplifier (PA) ICs with a new series-connected power combining technique using sub-quarter-wavelength transmission- line baluns. The PAs are implemented in a 0.25μm InP HBT process. At 86GHz, a single-stage PA exhibits 30.4% peak PAE, 20.37dBm Pout and 23GHz 3dB bandwidth. A two-stage PA exhibits 30.2% PAE, and 23.14dBm Pout. These values of PAE represent a 1.2:1 improvement in the state-of-the-art for E- and W- band PAs having similar RF output powers.