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We present (i) a novel, thermally stable Atomic Layer Deposition (ALD) high-k dielectric stack that, for the first time, has the potential to meet all gate stack requirements for both n- and p-channel Ge FETs, (ii) record low contact resistivity for n-Ge/metal contacts using an implant-free contact scheme with successful implementation into a single nanowire (NW) Ge nFET baseline, (iii) single NW Ge pFETs with short-channel effect (SCE) immunity down to 24 nm physical gate length, of which electrical data show excellent agreement with calibrated models and (iv) demonstration of Ge-channel vertically stacked lateral NW FETs using a 300 mm VLSI compatible platform.

We report the first demonstration of InAs FinFETs with fin width $\textrm {W}_{{\mathrm{fin}}}$ in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height $\textrm {H}_{{\mathrm{fin}}}=20$ nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length $\textrm {L}_{{{\textrm {g}}}}=1~\mu \text{m}$ , peak transconductance $\textrm {g}_{{{\textrm {m},{\mathrm{ peak}}}}}=1430~\mu \text{S}/\mu \text{m}$ is measured at $\textrm {V}_{{\textrm {d}}}=0.5$ V demonstrating that electron transport in InAs fins can match planar devices.

Al x In 1− x As y Sb 1− y quaternary alloys lattice-matched to InAs were successfully grown by molecular beam epitaxy (MBE) for use as buffer layers for substrate isolation in InAs channel devices. The use of In-containing quaternary buffer layers with 5% In was found to dramatically improve the heterointerface between the buffer and a surface InAs channel layer. The composition of these alloys and the extent of lattice matching were accurately determined by double crystal X-ray measurements. A simple model was used to estimate the variation of critical thickness with lattice mismatch for AlInAsSb epitaxially grown on an InAs substrate. Layers with high Al content and low As mole fraction were grown by modulated MBE technique which was found to significantly improve the surface morphology and the composition control of the alloys. In contrast, quaternary alloys with low Al content were grown by conventional MBE and had an rms roughness of less than 0.2 nm.

The integration of III-V semiconductors on silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches have been investigated, including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si- or Ge-on-insulator, epitaxial transfer methods, epitaxial lateral overgrowth, aspect-ratio-trapping techniques, and interfacial misfit array formation. However, manufacturing standards have not been met and significant levels of remaining defectivity, high cost, and complex integration schemes have hampered large scale commercial impact. Here we report on low cost, relaxed, atomically smooth, and surface undulation free lattice mismatched III-V epitaxial films grown in wide-fields of micrometer size on 300 mm Si(100) and (111) substrates. The crystallographic quality of the epitaxial film beyond a few atomic layers from the Si substrate is accomplished by formation of an interfacial misfit array. This development may enable future platforms of integrated low-power logic, power amplifiers, voltage controllers, and optoelectronics components.

The growth of heterostructures lattice matched to InAs(100) substrates for high mobility electronic devices has been investigated. The oxide removal process and homoepitaxial nucleation depends on the deposition parameters to avoid the formation of surface defects that can propagate through the structure during growth which can result in degraded device performance. The growth parameters for InAs homoepitaxy were found to be within an extremely narrow range when using As 4 with a slight increase using As 2 . High structural quality lattice matched AlAs x Sb 1− x buffer layer was grown on InAs(100) substrates using a digital growth technique with the AlAs mole fraction adjusted by varying the incident As flux. Using the AlAs x Sb 1− x buffer layer, the transport properties of thin InAs channel layers were determined on conducting native substrates.

We demonstrate MOVPE-growth of InAs/AlAs0.16Sb0.84/GaSb and InAs/AlAs0.16Sb0.84/InAs heterostructures of excellent quality as observed by transmission electron microscopy and x-ray diffraction 2-theta-omega and rocking curve scans with full width at half maximum routinely below 100 arcsec. Key points regarding interface control for heteroepitaxial nucleation are reviewed and the choice of suitable precursors to minimize the incorporation of C and O are discussed.

We present detailed design, fabrication and characterization of In 0.23 Ga 0.77 As-based planar Gunn diodes in this paper. The devices have AlGaAs/InGaAs/AlGaAs heterojunctions that were grown on a semi-insulating GaAs wafer using molecular beam epitaxy technology. Electron beam lithography was used to define anode and cathode terminal patterns. Devices with various anode–cathode separations (e.g. 4–1.4 μm) were fabricated on the same chip. Spectrum measurements showed oscillation frequencies between 36 GHz and 118 GHz in the fundamental transit-time mode of operation. These devices show great potential as millimeter wave and sub-millimeter wave signal sources for their small size, MMIC compatibility and lithographically controlled oscillation frequencies.

Electrical interface quality of various high- k dielectrics on GaSb, including Al2O3, HfO2, LaAlO3, GdScO3, and HfO2/Ga2O3 bilayer has been studied and compared with reference low (AlGaSb) and high Dit (native oxide) interfaces using photoluminescence intensity measurements for the first time. Al2O3 and HfO2/Ga2O3 bilayer dielectrics are identified with the lowest interface recombination velocity (S=7×104 cm/s) and consequently Dit integrated across essentially the entire bandgap. However, S for even the best identified high- k dielectrics is elevated by 140× over the low Dit AlGaSb reference indicating the need of further improvements for envisioned use in Sb based MOSFETs.

Kelvin probe force microscopy (KPFM) is a unique technique that can provide two dimensional potential profiles inside a working device. A procedure is described to obtain high-resolution KPFM results on ultra-high vacuum (UHV) cleaved III-V MOSCAPs. Two tip preparation methods: field emission and Cr coating show reproducible high spatial and energy resolution KPFM images. A unique sample design has been developed which is compatible with UHV cross-sectional KPFM (x-KPFM). Key design features are high density of devices on the cleave face, a buried device interface, and a cleavable gate contact. Using x-KPFM, the first UHV cleaved MOSCAP surface potential mapping is demonstrated.

In this paper a quantitative determination of the elemental distributions across a ~10nm Ga"2O"3/GdGaO layer with a Pt metal gate cap on top of an InGaAs/AlGaAs/GaAs substrate is presented. Some effects of annealing on the elemental distribution across the Ga"2O"3/GdGaO oxide layer are described. The paper also discusses the analysis of the interface GaAs/Ga"2O"3/GGO at a sub-nm level by high-resolution HAADF STEM imaging.

This paper reviews some of the recent work at the Nanoelectronics Research Centre at the University of Glasgow on the optimisation of 50 nm metamorphic GaAs and InP HEMTs. Typical DC and RF figures of merit obtained from 50 nm metamorphic GaAs HEMTs include I dss of 800 mA/mm, g m of 1100 mS/mm, threshold voltage standard deviation of 5 mV across a 25 mm × 25 mm area, f T of 440 GHz and f max of 400 GHz, all at a drain bias of 1.0 V. To our knowledge, these are the highest operating frequency GaAs-based transistors to date. At V d = 0.8 V and V g = − 0.6 V, a NF min and G ass of 0.7 dB and 13 dB respectively at 26 GHz have been demonstrated. For similar geometry InP HEMTs, DC and RF figures of merit are the following: I dss of 900 mA/mm, g m of 1600 mS/mm, f T of 550 GHz, f max of 440 GHz, and NF min and G ass of 0.9 dB and 14 dB respectively at 26 GHz. The highest performance 50 nm HEMTs reported to date. Using these technologies, single stage MMMICs with gain of at least 7 dB and a return loss of better than − 5 dB across a 24 GHz bandwidth from 71 GHz to 95 GHz have been realised. Noise figure of 2.5 dB and associated gain of 7.3 dB at 90 GHz have been achieved with a DC power consumption of 20 mW.

This paper investigates reactive ion etching (RIE) of sputtered tungsten films, a suitable candidate for gate metallization in compound semiconductor based high mobility channel devices, with the aim of developing a detailed understanding of the effects of etching parameters vital to reducing etch-induced damage and improving etching performance, yield, uniformity and repeatability. An Oxford Instruments PlasmaLab System 100 RIE etch tool and SF"6 based chemistry in combination with various functional gases, such as N"2, O"2 and CHF"3 was used in this study. To evaluate plasma-induced damage caused by the RIE process, GaAs based HEMT (high electron mobility transistor) type layer structures with channels buried 18nm from the surface were grown by molecular beam epitaxy (MBE). Subsequently, Van der Pauw structures were fabricated on this material and used to assess the effects of the RIE process on sheet resistivity, carrier concentration and mobility in the device channel. Etched tungsten line widths down to 25nm were obtained by electron beam lithography with Sumitomo NEB31 resist as an etch mask. The effects of etching gases of SF"6+N"2, SF"6+O"2, and SF"6+CHF"3, RF power, and etching temperature on etching profile and etching-induced damage were investigated.

Whilst high performance p-channel Ge MOSFETs have been demonstrated [1–4], Ge n-channel MOSFET drive current has been lagging behind mainly hampered by high access resistance and poor gate stack passivation [5–9]. In this work, we address these issues on a module level and demonstrate Ge enhancement mode nMOS FinFETs fabricated on 300mm Si wafers implementing optimized gate stack (D it 1×1020 cm−3) and metallization (ρ c = 1×10−7 Ωcm2) modules. L G ∼ 40 nm devices achieved I on = 50 µA/µm at I off = 100 nA/um, S ∼ 124 mV/dec, at V DD = 0.5V. The same gate stack and contacts were deployed on planar devices for reference. Both FinFET and planar devices in this work achieved the highest reported g m /S sat at 0.5 V to date for Ge nMOS enhancement mode transistors to the best of our knowledge at shortest gate lengths.

A model that simulates the behaviour of group III atoms of various migration lengths is presented. The program operates under As rich conditions typical for MBE, so a group V atom will be placed immediately above a group III atom once that group III atom has bonded into the crystal. The model has no information about bond angles. Growth is controlled by the interaction of the group III atoms through their migration length and a requirement to migrate to a position to increase the number of their nearest neighbours.

Planar Gunn diodes operating above 100 GHz fabricated in GaAs/AlGaAs heterojunction structures with single and double δ-doping layers on each side of GaAs channel are numerically studied and experimentally demonstrated. The results show enhanced RF power and oscillation frequency when double δ-doping technique was used. By using a two-dimensional numerical simulation tool, the conduction band profile, electron concentration in the epitaxy layers and current-voltage characteristics are investigated. Simulation results indicate that extra δ-doping layers increase electron confinement in the conducting channel, therefore higher current levels are obtained. Simulated current-voltage characteristics in both cases agree well with experimental results. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26071

In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried-channel In0.53Ga0.47As devices employing an atomic layer-deposited Al2O3 gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm2/V · s and 6600 cm2/V · s at a carrier density of 3 × 1012 cm-2 were determined for the surfaceand buried-channel structures, respectively. In contrast to similarly scaled inversion-channel devices, we find that the mobility in surface channel flatband structures does not drop rapidly with the electron density, but rather high mobility is maintained up to carrier concentrations around 4 × 1012 cm-2 before slowly dropping to around 2000 cm2/V · s at 1 × 1013 cm-2. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for the future low-power highly scaled CMOS.

Contacts to planar Gunn devices on the semiconductor surface suffer from high electric field stress and current crowding leading to premature burn out. We have developed a new composite contact design using a Schottky extension of the conventional Ohmic contact. The composite contact structures have been fabricated and tested to mitigate the effects of high concentrations of charge and high electric fields at the anode edge of the planar Gunn diode. Monte Carlo simulations confirm these experimental results in composite contacts. These results suggest a mechanism of increased lifetime when using composite contacts as compared to conventional Ohmic contacts. This is of significant importance for planar Gunn device operation at millimetre wave and terahertz frequencies where high doping density (∼1017cm- 3) and short cathode to anode separation (1µm or less) is required. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and Lg = 130 nm operating at 0.5 V, on-current as high as Ion = 601 μA/μm (at fixed Ioff = 100 nA/μm) is achieved. This record performance is enabled by gm, ext = 2.72 mS/μm and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm2/V.s at ns = 6.7×1012 cm-2. Device simulations further elucidate the performance potential of III-V N-MOSFETs.

We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak gm, ext=2.7mS/μm (gm, int=3.3mS/μm), Q (≡gm, ext/SSsat) = 32.4 and Ion= 497μA/μm at Ioff = 100nA/μm, all at Vds= -0.5V. The high performance is a result of successful integration of oriented, highly scaled Ge fins on silicon substrates and of a low Dit gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (gm/SS metric) and ~2× (Ion/Ioff metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.

In this paper, a subnanometer characterization of the Ga"2O"3/GdGaO dielectric gate stack grown on top of InGaAs lattice matched to n^+ InP substrate is presented. The paper shows the analysis of two samples grown using different substrate temperature. This clearly affects the electrical characteristics as well as the photoluminescence properties. The paper also describes how the growth conditions of oxide stack affect the elemental distribution across the interface region.

We have measured the magnitude of the potential modulation below gated one-dimensional lateral surface superlattices fabricated with periods between 60 and 600 nm on a range of GaAs/AlGaAs heterostructures. The magnitude of the modulation was obtained by studying the amplitude of the commensurability oscillations in magnetoresistance, and confirmed by analysis of the low field positive magnetoresistance step. Without gate bias applied, the modulation is generated by strain in the gates, coupled piezoelectrically to the two-dimensional electron gas. Both magnitude and harmonic content of the potential are in reasonable agreement with a recent theoretical calculation of this coupling, over the full range of periods and for all the structures studied. Away from zero gate bias electrostatic modulation adds to the piezoelectric component. This differs according to the sign of the applied bias. In depletion it increases roughly linearly with bias and is in good agreement with theoretical estimates, whereas in positive bias it tends to saturate as strong screening in the donor layers develops.

We show the experimental realization of a 108-GHz planar Gunn diode structure fabricated in GaAs/AlGaAs. There is a considerable interest in such devices since they lend themselves to integration into millimeter-wave and terahertz integrated circuits. The material used was grown by molecular beam epitaxy, and devices were made using electron beam lithography. Since the frequency of oscillation is defined by the lithographically controlled anode-cathode distance, the technology shows great promise in fabricating single chip terahertz sources.

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies.

The capacitance of a single-electron wire at high quantizing magnetic fields is studied. We demonstrate that the capacitance spectroscopy allows us to study the formation of compressible and incompressible stripes directly. The electron wire is field induced in a metal insulator semiconductor heterostructure beneath a center gate. The electrostatic potential defining the wire edge is controlled by a tuning-fork-shaped electrode that encloses the center gate. It is found that the capacitance spectra are very sensitive to the wire edge potential and show a clear asymmetry of the capacitance minimum at filling factor n52. The experimental results are well described by a simple model considering the contribution of compressible and incompressible stripes in the electron channel, to the capacitance signal. The capacitance minima are thus determined in our experiments by the geometry of the compressible and incompressible stripes in the channel and not by the defect-induced density of states. @S0163-1829~96!02143-1#

A recently introduced lithographic tool employing an atomic force microscope is improved and utilized to fabricate nanometer-scale antidot arrays. The AFM periodically creates holes in a thin photoresist, covering a conventional mesa-etched GaAsAlGaAs heterostructure. To minimize the period of produced holes in the resist we now use carbon AFM supertips, prepared in a scanning electron microscope. To create holes or lines in the resist, a mechanical force of typically 1 μ N is exerted at ambient conditions. We thus succeed in fabricating hole arrays with a periodicity down to 15 nm and a hole diameter of only few nanometers. The resist mask is transferred onto the two-dimensional electron gas either by a shallow wet chemical etch step or by an ion beam irradiation technique, respectively. In magneto-resistance studies at T = 4.2 K on antidot-devices with periods down to 85 nm, we clearly observe commensurability oscillations of the longitudinal resistance R xx , demonstrating the successful pattern transfer to the electron system. Resistance fluctuations measured at T = 25 mK indicate a clear dependence on the period of the antidots.

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/μm at 1V, 1.05 mS/μm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest g m /SS at V dd =1V reported for non-planar unstrained Ge pFETs to date.

The high mobility of electrons in AlGaAs-GaAs heterostructures relies on the concept of modulation doping. As a sample is cooled down to Τ = 4.2 K under a fixed gate bias the number of ionized donors can be frozen and is then independent on the gate potential. We discuss the consequences of this procedure on the electron density and mobility in a two-dimensional electron gas. For a laterally patterned sample we find that the amplitude of the potential modulation can be maximized for a given carrier density by a suitably chosen cool-down voltage. PACS numbers: 73.20.Dx, 03.65.Sq, 73.50.Jt

We have investigated periodic arrays of dry etched 150 nm and 175 nm wide, (110) oriented GaAs/AlAs quantum wires and quantum dots by means of reciprocal-space mapping using triple-axis X-ray diffractometry. From the X-ray data the lateral periodicity of wires and dots, the etch depth and the angle of misorientation of the wires with respect to the (110) direction are extracted. The reciprocal-space maps reveal that, after the fabrication process the lattice constant along the growth direction increases slightly for the wires and even more so for the dots.

In this paper we present a comparative study of the high frequency performance of 80-200 mm gate length Al/sub 0.25/GaAs/GaAs/(GaAs:AlAs) superlattice buffer quantum well (QW) HEMTs, Al/sub 0.3/GaAs/In/sub 0.15/GaAs/GaAs pseudomorphic HEMTs and In/sub 0.52/AlAs/In/sub 0.65/GaAs/InP pseudomorphic HEMTs. From an experimental determination of the delays associated with transiting both the intrinsic and parasitic regions of the devices, effective electron velocities in the intrinsic channel region under the gate of the HEMT's were extracted. This analysis showed no evidence of any systematic increase in the effective channel velocity with reducing gate length in any of the devices. The effective electron velocity in the channel of the pseudomorphic In/sub 0.65/GaAs/InP HEMTs, determined to be at least 2.5/spl times/10/sup 5/, was was around twice that of either the Al/sub 0.25/GaAs/GaAs quantum well or pseudomorphic In/sub 0.15/GaAs/GaAs HEMTs, resulting in 80 nm gate length devices with f/sub T/'s of up to 275 GHz. We also show that device output conductance is strongly material dependent. A comparison of the different buffer layers showed that the (GaAs:AlAs) superlattice buffer was most effective in confining electrons to the channel of the Al/sub 0.25/GaAs/GaAs HEMTs, even for 80 nm gate length devices. We propose this may be partly due to the presence of minigaps in the superlattice which provide a barrier to electrons with energies of up to 0.6 eV. The output conductance of pseudomorphic In/sub 0.65/GaAs/InP HEMTs was found to be inferior to the GaAs based devices as carriers in the channel have greater energy due to their higher effective velocity and so are more difficult to confine to the 2DEG.

A stacked gate technique is applied to study electronic excitations in electron quantum wire, quantum dot and antidot arrays in GaAs/AlAs MISFET-type heterojunctions at far-infrared frequencies. The gate configuration consists of a finely (period a ⩾ 250 nm) patterned bottom electrode on the surface of the heterostructure, a dielectric spacer and a homogeneous top gate. An electron grating is induced at the heterostructure interface either beneath the strips or beneath the gaps of the grating gate. With the fields induced by the top gate the confining potential can be controlled nearly independently of the electron density in quantum wires below the bottom gate. This is demonstrated by far-infrared studies of the dimensional resonances in the wires. In a perpendicular magnetic field we observe a very pronounced splitting of the dimensional resonance. We study this behaviour as a function of wire separation and potential form and find this splitting to reflect the anharmonicity of the confining potential.

We report various flatband III–V MOSFETs with an In 0.3 Ga 0.7 As channel and Ga 2 O 3 /GaGdO (GGO) (κ=20) gate dielectric stack. Lithographically aligned devices display sub-threshold slope (S) of 60–70 mV/dec for gate lengths down to 100 nm, the lowest values reported to date. We also present the first 100 nm gate length enhancement mode, fully self-aligned III–V MOSFETs realized using critical geometry modules compatible with silicon VLSI manufacturing.

In this paper a quantitative determination of the elemental distribution across a GaAs/Ga2O3/GGO dielectric gate stack is presented and the analysis discussed. The EELS spectrum imaging technique is described and the data analysis discussed.

Planar Si MOSFET technology using Si(ON) is rapidly approaching its theoretical limit and the search for new material is essential. n-type GaAs has a mobility 5 times higher than Si [1]. This makes it a suitable candidate for MOSFETs devices. So far, GaAs has not been used for practical MOSFETs because of the difficulties of making a good dielectric oxide layer in terms of leakage current and unpinned Fermi Level. Using processes pioneered by Passlack et al. [2], dielectric gate stacks consisting of a template layer of amorphous Ga2O3 followed by amorphous GdGaO have been grown on GaAs substrates. Careful deposition of Ga2O3 can leave the Fermi Level unpinned. The introduction of Gd is important in order to decrease the leakage of current.

This paper summarises the current state of the art in GaAs MOSFETs, and argues that the 4 decade search for a device quality compound semiconductor oxide is over. Under suitable growth conditions, a GaO/GaGdO high-k (~20) gate dielectric has been shown to have a mid-gap density of states of 2.5 x 1011 cm-2 eV-1 [1], and vitally, an unpinned oxide-semiconductor interface [2]. With a scalable vertical architecture, enhancement mode implant-free III-V MOSFETs [3] with an In0.25GaAs channel layer, have yielded electron transport metrics comp25GaAs channel layer, have yielded electron transport metrics comparable to GaAs pHEMTs of similar materials compositions-namely mobility of above 5000 cm2/Vs for carrier concentration above 2 x 1012 cm-2 [4]. From these material structures, 1 μm gate length GaAs MOSFETs with a 10 nm gate oxide have been realised with threshold voltage of +0.26 V, saturation drive current, Id,sat = 407 mA/mm,arable to GaAs pHEMTs of similar materials compositions-namely mobility of above 5000 cm2/Vs for carrier concentration above 2 x 1012 cm-2 [4]. From these material structures, 1 μm gate length GaAs MOSFETs with a 10 nm gate oxide have been realised with threshold voltage of +0.26 V, saturation drive current, Id,sat = 407 mA/mm, maximum extrinsic transconductance, gm = 477 mS/mm, output conductance, gd = 11 mS/mm , gate leakage current, Ig = 60 pA for gate voltages up to + 2.0 V, subthreshold swing, S = 102 mV/dec, on resistance, Ron = 1.920 Ωmm, and Ion/Ioff ratio = 6.3 x 104 [4]. A gate voltage swing of +2 V can easily be accommodated with these devices, making them attractive as a single supply III-V technology. Enhancement mode operation can be sustained to 300 nm with this oxide thickness, with peak intrinsic transconductance increasing to 600 mS/mm, indicative of the on-set of non-equilibrium transport effects, similar to short gate length pHEMTs [5]. Initial RF data from 0.8 μm gate length III-V MOSFETs with a threshold voltage of +0.4 V, resulted in fT and fmax of 14 GHz and 40 GHz respectively. (5 pages)

The prospect for the introduction of III-V semiconductors into the channel of n-type MOSFETs and thus replace Si with a high mobility material for 22 nm technology generation and beyond is examined in detail. The so-called implantfree (IF) III-V MOSFET architecture option is presented showing a fabricated n-type IF demonstrator suitable for scaling. We then focus on a prediction of the potential performance of III-V MOSFETs through physically-based Monte Carlo (MC) device simulations. An implanted, n-type III-V MOSFETs based on In0.3Ga0.7As channel is investigated when scaled from a gate length of 30 nm to 20 nm and 15 nm. The impact of decisive scattering mechanisms operative at the dielectric/semiconductor interface is discussed. We also simulate the IF devices with low (In0.3Ga0.7As) and high (In0.75Ga0.25As) Indium content channel scaled to gate lengths of 30, 20 and 15 nm with equivalent layer thicknesses. The IF architecture is found to deliver a high drive current because of the highly efficient injection of electrons into the channel and because of very low access resistances. However, the low Indium content channel IF transistor is not able to further increase its drive current when scaled to the 15 nm gate length. Therefore, we examine also the performance of high indium channel transistors which delivers a steady increase in the device performance down to the 15 nm gate length.

We have fabricated lateral surface superlattices by etching a strained layer of In0.2Ga0.8As near the surface of a heterostructure. This provides strong modulation of the electron gas while retaining a high electron mobility. The potential arises mainly from strain and the piezoelectric effect, which depends on orientation, and from the change in the surface profile. The fundamental components of these two contributions cancel in one orientation to leave a dominant second harmonic. This effectively halves the period of the superlattice from its lithographic value and provides a promising technique for creating potentials with a period comparable to the Fermi wavelength.

We report well-scaled 50 nm GaAs metamorphic HEMTs (mHEMTs) with DC power consumption in the range 1-150 muW/mu demonstrating fT of 30-400 GHz. These metrics enable the realisation of ultra-low power (

We report on the experimental realization of a quantum point contact in a semiconductor heterostructure by lithography with an atomic force microscope (AFM). A thin, homogeneous titanium film on top of the chip surface was patterned by local anodic oxidation, induced by a current applied to an n-doped AFM tip. We demonstrate that self-aligned gate structures in the sub-micron regime can be fabricated with this technique.

The 50 nm m-HEMT exhibits extremely high f/sub T/, of 440GHz, low F/sub min/ of 0.7 dB, associated gain of 13 dB at 26 GHz with an exceptionally high Id of 200 mA/mm and gm of 950 ms/mm at low noise biased point.

In this paper, we review a range of nanofabrication techniques which enable the realization of uniform, high yield, high performance 50 nm T-gate III-V high electron mobility transistors (HEMTs). These technologies have been applied in the fabrication of a range of lattice matched and pseudomorphic InP HEMTs and GaAs metamorphic HEMTs with functional yields in excess of 95%, threshold voltage uniformity of 5 mV, DC transconductance of up to 1600 mS/mm and f/sub T/ of up to 480 GHz. These technologies and device demonstrators are key to enabling a wide range of millimeter-wave imaging and sensing applications beyond 100 GHz, particularly where array-based multi-channel solutions are required.

We report the performance of 50 nm gate length metamorphic GaAs HEMTs with maximum transconductance (g/sub m/) of 1520 mS/mm and current cut-off frequency(f/sub T/) of 350 GHz, to our knowledge the highest g/sub m/ and f/sub T/ of a GaAs-based HEMT transistor. The devices were fabricated with a novel UVIII/PMMA T-gate resist stack and a non-selective "digital" wet etch gate recess technology which results in a highly uniform, high yield sub-100 nm HEMT technology.

We demonstrate single electron charging in fully controllable nanoscale quantum devices at temperatures above 4 K. Hitherto, single electron devices operating at ‘‘high’’ temperatures have been two‐terminal, having no control electrode, whereas fully tunable structures such as quantum dots have only shown charging effects at temperatures of 4 K or less. We have fabricated ultrasmall quantum dots on modulation doped heterostructures where the two‐dimensional electron gas is less than 30 nm from the surface. Dots with lithographic diameter 150 nm show Coulomb oscillations up to temperatures of 7 K. Higher temperature operation allows potential applications to be considered without the need, for example, of a dilution fridge.

The authors report the input referred low-frequency noise (2 – 100 kHz) spectra of 0.2 µm-gate-length GaAs MESFETs which were gate-recess-etched using a selective Freon 12 based dry-etching process. For comparison, the noise spectra of nonselective wet-chemical, ammonia-based gate-recess-etched devices are also presented. Little change in low-frequency noise performance is observed for devices dry-etched for 30 – 50 s, demonstrating the latitude of the dry-etch process. Additionally, the input referred noise of the wet-etched devices was greater than that of 30, 40 and 50 s dry-etched devices, suggesting that the dry-etching process may passivate traps contributing to the low-frequency noise component of the MESFETs.

Periodic arrays of 150 and 175 nm‐wide GaAs–AlAs quantum wires and quantum dots were investigated, fabricated by electron beam lithography, and SiCl4/O2 reactive ion etching, by means of reciprocal space mapping using triple axis x‐ray diffractometry. From the x‐ray data the lateral periodicity of wires and dots, and the etch depth are extracted. The reciprocal space maps reveal that after the fabrication process the lattice constant along the growth direction slightly increases for the wires and even more so for the dots.

We report the design, fabrication and measurement of a three stage W-band amplifier with up to 22 dB gain at 94 GHz and a single stage D-band amplifier with 5 dB gain at 150 GHz. Circuits were designed and fabricated in coplanar waveguide technology using a 0.121 /spl mu/m T-gate lattice matched InP HEMT technology.

We describe a novel technique using an atomic force microscope (AFM) for integrated nanometer‐scale lithography on various mask materials such as photoresist or gold covering a mesa‐etched GaAs‐AlGaAs heterostructure at ambient conditions. The generated patterns can be transferred to the two‐dimensional electron gas by wet chemical etching or by ion beam irradiation. We succeed in fabricating hole arrays with a periodicity down to 35 nm and a hole diameter of only a few nanometers. In magnetoresistance studies on so‐called antidot devices with 95 nm period at T=4.2 K we can clearly observe commensurability oscillations, demonstrating the successful pattern transfer to the electron system. With the AFM we can also pattern lines of varying width and depth into prefabricated devices.

We study the photocurrent of quantum capacitor devices consisting of an electron wire array induced in an undoped AlAs/GaAs heterojunction with an interdigitated gate electrode. The photocurrent measures the collective one‐dimensional intersubband resonance in the electron wires. The new technique to measure fundamental excitations of nanostructured electron systems yields strong signals even at very low electron densities so that only a single one‐dimensional subband is occupied. Compared to previous far‐infrared transmission studies the length and the number of the wires averaged in our technique is substantially smaller. The intersubband resonance in our devices is tunable in a wide range of energies up to 10.5 meV.

A GaAs pseudomorphic HEMT process has been optimised for high performance and yield at W-band. Several key nano-fabrication techniques are explored for performance, manufacturability and process sensitivity. The molecular beam epitaxially grown pHEMT layer is optimised for reduced short channel effects, high transconductance (690 mS/mm) and reliability. Electron-beam lithography produces ultra short T-gates with high reproducibility. Selective reactive ion etching enables both the depth and width of the gate recess to be accurately controlled. 0.2 /spl mu/m pHEMTs with two 50 /spl mu/m gate fingers exhibit average values for f/sub T/ and f/sub max/ of 121 and 157 GHz with low standard deviations of 4.6 and 2.9 GHz respectively. >