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128 results on '"Man Young Sung"'

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1. Optimized Designing to Improve Electrical Characteristics of 4H–SiC Wide Trench Junction Barrier Schottky Diode

2. Investigation of the layout and optical proximity correction effects to control the trench etching process on 4H-SiC

3. Improving Current Density of 4H–SiC Junction Barrier Schottky Diode with Wide Trench Etching

4. Edge Termination for Optimized Silicon Carbide MOSFET Breakdown Voltage

6. 67-3: Bottom-Gate ELA Poly-Si TFT for High-Resolution AMOLED Mobile Displays

7. Post-annealing processes to improve inhomogeneity of Schottky barrier height in Ti/Al 4H-SiC Schottky barrier diode

8. A Study of Post Annealing Effects in the Repair of High Resistance Failures with Unstable Schottky Barrier Height in 4H-SiC Schottky Barrier Diode

10. New Design Rule for High Voltage Field Ring Structure

11. Analysis of Lattice Temperature in Super Junction Trench Gate Power MOSFET as Changing Degree of Trench Etching

12. The effect of carbon-doped In3Sb1Te2ternary alloys for multibit (MLC) phase-change memory

13. A Study on the Design and Electrical Characteristics Enhancement of the Floating Island IGBT with Low On-Resistance

14. A Study on the MDTF for Uncooled Infrared Ray Thermal Image Sensors with High Thermal Coefficient of Resistance

15. Study on Design of 60 V TDMOSFET for Protection Circuit Module

16. A Study on the Electrical Characteristics with Design Parameters in 1,200 V Trench Gate Field Stop IGBT

17. Electrical Characteristics of Floating Island IGBT Using Trench Gate Structure

18. A Study on the Design of a ROIC for Uncooled Infrared Ray Detector Using Differential Delta Sampling Technique

19. Dual Field Communication Scheme for UHF (860–960 MHz) Gen2 RFID Chip

20. Liquid Lens Module with Wide Field-of-View and Variable Focal Length

21. A Study on the Electrical Characteristics with Design Parameters in GaN Power Static Induction Transistor

22. BIDIRECTIONAL FLOATING-BASE BJT ESD PROTECTED RFID CHIP

23. The Research on Trench Etched Field Ring with Dual Ion-Implantation for Power Devices

25. A Study on Double Sampling Design of CMOS ROIC for Uncooled Bolometer Infrared Sensor using Reference Signal Compensation Circuit

26. FLOATING-BASE BJT TYPE ESD DEVICE FOR RFID CHIP

27. A Study on the Design of a ROIC for Uncooled Bolometer Thermal Image Sensor using Reference Resistor Compensation

28. Design of field limiting ring employing trench structure for high power devices

29. A Design Method on Power Sense FET to Protect High Voltage Power Device

30. CRYPTO BASED EPC C1G2 UHF (860 MHz–960 MHz) PASSIVE RFID TAG CHIP

31. An Analysis of IGBT(Insulator Gate Bipolar Transistor) Structure with an Additional Circular Trench Gate using Wet Oxidation

32. A Study on the 1,700 V Rated NPT Trench IGBT Analysis by PIN Diode - PNP Transistor Model

33. A New CMOS Read-out IC for Uncooled Microbolometer Infrared Image Sensor

34. Design and Analysis of 16 V N-TYPE MOSFET Transistor for the Output Resistance Improvement at Low Gate Bias

35. A Readout IC Design for the FPN Reduction of the Bolometer in an IR Image Sensor

36. Effects of bottom electrode and environmental insulator on thermal distribution of edge contact-type PRAM cell

37. A Study on the Breakdown Voltage Characteristics with Process and Design Parameters in Trench Gate IGBT

38. A FERROELECTRIC BASED PASSIVE RFID TAG FOR UHF (860–960 MHz) BAND

39. Improvements of Defects by Patterning Using Thermal Nanoimprint Lithography

40. Piezoelectric and Dielectric Properties of 0.05Pb(Al.0.5Nb0.5)O3–0.95Pb(Zr0.52Ti0.48)O3Ceramics Doped with Nb2O5and MnO2

41. Low Temperature Sintering of ZnO-Doped 0.01Pb(Mg1/2W1/2)O3–0.41Pb(Ni1/3Nb2/3)O3–0.35PbTiO3–0.23PbZrO3Ceramics

42. Characteristics of PMW-PNN-PT-PZ thick films on various bottom electrodes

43. Temperature-Dependent Gate Effect of Sintered HgTe Nanoparticles

44. Design of Low Power Sigma-delta ADC for USN/RFID Reader

45. Electrical characteristics of single-silicon TFT structure with symmetric dual-gate for kink-effect suppression

46. Electrical Characteristics of SRAM Cell with Stacked Single Crystal Silicon TFT Cell

47. Improved Defect Control Problem using Scaled Down Silicon Oxide Stamps for Nanoimprint Lithography

48. Wafer Burn-in Method for SRAM in Multi Chip Package

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