128 results on '"Man Young Sung"'
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2. Investigation of the layout and optical proximity correction effects to control the trench etching process on 4H-SiC
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Man Young Sung, Eun Sik Jung, and Sinsu Kyoung
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010302 applied physics ,Materials science ,business.industry ,Pillar ,Process (computing) ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,Process conditions ,Test element ,Optical proximity correction ,Etching (microfabrication) ,0103 physical sciences ,Trench ,Forensic engineering ,Optoelectronics ,Power MOSFET ,0210 nano-technology ,business - Abstract
Although trench gate and super-junction technology have micro-trench problems when applied to the SiC process due to the material characteristics. In this paper, area effects are analyzed from the test element group with various patterns and optical proximity correction (OPC) methods are proposed and analyzed to reduce micro-trenches in the SiC trench etching process. First, the loading effects were analyzed from pattern samples with various trench widths (Wt). From experiments, the area must limited under a proper size for a uniform etching profile and reduced micro-trenches because a wider area accelerates the etch rate. Second, the area effects were more severely unbalanced at corner patterns because the corner pattern necessarily has an in-corner and out-corner that have different etching areas to each other. We can balance areas using OPC patterns to overcome this. Experiments with OPC represented improved micro-trench profile from when comparing differences of trench depth (Δdt) at out corner and in corner. As a result, the area effects can be used to improve the trench profile with optimized etching process conditions. Therefore, the trench gate and super-junction pillar of the SiC power MOSFET can have an improved uniform profile without micro-trenches using proper design and OPC.
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- 2017
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3. Improving Current Density of 4H–SiC Junction Barrier Schottky Diode with Wide Trench Etching
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Tai Young Kang, Man Young Sung, Sinsu Kyoung, and Eun Sik Jung
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010302 applied physics ,Materials science ,business.industry ,Schottky barrier ,Biomedical Engineering ,Schottky diode ,Bioengineering ,02 engineering and technology ,General Chemistry ,021001 nanoscience & nanotechnology ,Condensed Matter Physics ,Metal–semiconductor junction ,01 natural sciences ,Etching (microfabrication) ,0103 physical sciences ,Trench ,Optoelectronics ,General Materials Science ,0210 nano-technology ,business ,Current density - Published
- 2016
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4. Edge Termination for Optimized Silicon Carbide MOSFET Breakdown Voltage
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Sola Woo, Man Young Sung, Sinsu Kyoung, and Jongmin Geum
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chemistry.chemical_compound ,Materials science ,chemistry ,business.industry ,MOSFET ,Silicon carbide ,Optoelectronics ,Breakdown voltage ,Electrical and Electronic Engineering ,Edge (geometry) ,business ,Electronic, Optical and Magnetic Materials - Published
- 2016
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5. Study of Electrical Characteristics of a 4H–SiC Merged/PiN Schottky Adding a Low-Doped P-Barrier
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Man Young Sung, Jae Hyun Lee, Jongmin Geum, and Sinsu Kyoung
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Materials science ,business.industry ,Schottky barrier ,Doping ,Schottky diode ,Optoelectronics ,Electrical and Electronic Engineering ,Metal–semiconductor junction ,business ,Electronic, Optical and Magnetic Materials - Published
- 2016
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6. 67-3: Bottom-Gate ELA Poly-Si TFT for High-Resolution AMOLED Mobile Displays
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Kwon-Shik Park, Man Young Sung, Kum-Mi Oh, In-Byeong Kang, Jung-Il Lee, and Shun-Young Yang
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Reliability (semiconductor) ,AMOLED ,Bottom gate ,Materials science ,Thin-film transistor ,business.industry ,020208 electrical & electronic engineering ,0202 electrical engineering, electronic engineering, information engineering ,Breakdown voltage ,High resolution ,Optoelectronics ,02 engineering and technology ,business - Abstract
We developed bottom-gate poly-Si TFTs (BGPs) using ELA for high resolution AMOLED. The BGPs based on our novel process to solve the disconnection of poly-Si during ELA crystallization have better reliability characteristics such as breakdown voltage (BV) and kink effect compared with the conventional top-gate poly-Si TFTs.
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- 2016
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7. Post-annealing processes to improve inhomogeneity of Schottky barrier height in Ti/Al 4H-SiC Schottky barrier diode
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Eun-Sik Jung, Man Young Sung, and Sinsu Kyoung
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010302 applied physics ,Interface layer ,Materials science ,Annealing (metallurgy) ,business.industry ,Schottky barrier ,Schottky diode ,02 engineering and technology ,021001 nanoscience & nanotechnology ,Condensed Matter Physics ,Metal–semiconductor junction ,01 natural sciences ,Atomic and Molecular Physics, and Optics ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,Post annealing ,0103 physical sciences ,Breakdown voltage ,Optoelectronics ,Electrical and Electronic Engineering ,0210 nano-technology ,business ,Tem analysis - Abstract
To improve the high resistance and low breakdown voltage (BV) of a 4H-SiC Schottky barrier diode (SBD), the metal annealing process is conventionally used; this process stabilizes the Schottky barrier height (SBH). In this paper, we apply a post-metal annealing process to 4H-SiC Ti-SBD chips and verify the effect of the changes on electrical characteristics based on the post-annealing process. The results of experiments show that the condition of 873K/30min annealing created a stable SBH and a low value of on-resistance (Ron), which improved inhomogeneity. Based on the results of EDX and TEM analysis, the cause of improved SBH at the condition of 30min was attributed to the generation of TiSix (which has a higher SBH than Ti). On the other hand, the improved value of Ron at the condition of 30min was attributed to the change to γ-phase Ti3Al (which has a low resistance because diffused Al is present) caused by proper annealing. However, when more heat is applied in the cases of 773K/60min and 873K/60min, Ron increased and the SBH decreased. The results of EDX and TEM analysis showed that the low SBH was caused by Al spiking, which created an Al Schottky junction with a lower SBH than that of the Ti Schottky junction. Higher Ron resulted from the change to α-TiAl phase at the Al-Ti interface layer because of excessive diffusion of Ti and Al, which is due to the overly applied heat.From the results produced by this work, we can enhance the Al-Ti 4H-SiC SBD electrical characteristics by applying a suitable post-annealing process. Display Omitted
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- 2016
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8. A Study of Post Annealing Effects in the Repair of High Resistance Failures with Unstable Schottky Barrier Height in 4H-SiC Schottky Barrier Diode
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Sin Su Kyoung, Eun Sik Jung, Chang Heon Yang, Man Young Sung, and Tai Young Kang
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Materials science ,Annealing (metallurgy) ,Mechanical Engineering ,Schottky barrier ,chemistry.chemical_element ,Schottky diode ,Condensed Matter Physics ,Post annealing ,Metal ,chemistry ,Mechanics of Materials ,Aluminium ,visual_art ,visual_art.visual_art_medium ,Electronic engineering ,Breakdown voltage ,General Materials Science ,Composite material ,Titanium - Abstract
To improve the high resistance and low Breakdown Voltage (BV) of 4H-SiC SBD, the metal annealing process is usually used to to stabilize SBH. We confirmed that post metal annealing after the chip process also stabilizes SBH by the post annealing experiment of applying failure chips (4H-SiC Ti/Al SBD) that have a forward current (IF) under 1 [A] with high resistance, because of the metal annealing process error. The result of experiments showed that the IFincrement and BV decrement are proportional to the applied temperatures over 450 °C, and the second additional post annealing shows a decrease of IFand BV. Aluminum and Titanium transformation with post metal annealing made a decrease of SBH, so that the on-resistance is decreased and BV is decreased (in severe cases, the intense post annealing generates Aluminum spiking). From a result of this work, using a suitable post metal annealing, we can improve the IFof SiC SBD with a high resistance failure from the metal process event.
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- 2015
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9. A Study on Electrical Characteristic Improvement & Design Parameters of Power MOSFET with Single Floating Island Structure
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Yu Seup Cho and Man Young Sung
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Materials science ,business.industry ,Electrical engineering ,Breakdown voltage ,Power semiconductor device ,Power MOSFET ,business ,Engineering physics ,Floating island - Published
- 2015
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10. New Design Rule for High Voltage Field Ring Structure
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Jongmin Geum, Man Young Sung, and Sinsu Kyoung
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Materials science ,Condensed matter physics ,Field (physics) ,Biomedical Engineering ,Structure (category theory) ,General Materials Science ,Bioengineering ,High voltage ,General Chemistry ,Condensed Matter Physics ,Ring (chemistry) - Published
- 2016
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11. Analysis of Lattice Temperature in Super Junction Trench Gate Power MOSFET as Changing Degree of Trench Etching
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Jong Min Geum, Byeong Il Lee, Yong Tae Kim, Eun Sik Jung, Ey Goo Kang, and Man Young Sung
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Materials science ,Lattice temperature ,business.industry ,Electrical engineering ,Electronic, Optical and Magnetic Materials ,Degree (temperature) ,Etching (microfabrication) ,Shallow trench isolation ,Trench ,Breakdown voltage ,Optoelectronics ,Electrical and Electronic Engineering ,Power MOSFET ,business ,Trench gate - Abstract
Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance [1]. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don’t have a great effect on temperature change.
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- 2014
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12. The effect of carbon-doped In3Sb1Te2ternary alloys for multibit (MLC) phase-change memory
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Hyun Soo Kim, Yong Tae Kim, Ha Sub Hwang, and Man Young Sung
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Materials science ,Alloy ,Thermodynamics ,engineering.material ,Condensed Matter Physics ,law.invention ,Amorphous solid ,Phase-change memory ,Crystallography ,law ,Vacancy defect ,Phase (matter) ,engineering ,General Materials Science ,Crystallization ,High-resolution transmission electron microscopy ,Ternary operation - Abstract
One of the candidate materials for phase-change memory, In3Sb1Te2 (IST), shows multilevel phase transformations from amorphous to several crystalline materials of IST, intermediate phases such as InSb, SbTe and InTe. However, its volume can change abruptly in the multilevel phase transformation, and this change can lead to vacancy movement and atomic migration, which are related to failures and reliability issues. We propose the carbon-incorporated In3Sb1Te2 (IST-C) alloy, which has higher retention ability than the IST ternary alloy. Carbon atoms delay crystallization and prevent volume change during the set/reset operation. The carbon concen- tration is 12.5%, and the activation energy increases from 5.1 eV to 5.4 eV. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
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- 2014
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13. A Study on the Design and Electrical Characteristics Enhancement of the Floating Island IGBT with Low On-Resistance
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Eun Sik Jung, Man Young Sung, Yu Seup Cho, Ey Goo Kang, and Yong Tae Kim
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Switching time ,Materials science ,business.industry ,Bipolar junction transistor ,Electrical engineering ,Breakdown voltage ,Insulated-gate bipolar transistor ,Electrical and Electronic Engineering ,business ,Thermal conduction ,Voltage drop ,Floating island ,Voltage - Abstract
Insulated Gate Bipolar Transistors(IGBTs) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the onstate voltage drop should be lowered and the switching time should be shortened. However, there is trade-off between the breakdown voltage and the on-state voltage drop. The FLoatingIsland(FLI) structure can lower the on-state voltage drop without reducing breakdown voltage. In this paper, The FLI IGBT shows an on-state voltage drop that is 22.5% lower than the conventional IGBT, even though the breakdown voltages of each IGBT are almost identical.
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- 2012
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14. A Study on the MDTF for Uncooled Infrared Ray Thermal Image Sensors with High Thermal Coefficient of Resistance
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Ey-Goo Kang, Man-Young Sung, Se-Jin Jeong, and Eun-Sik Jung
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Materials science ,Infrared ,business.industry ,Analytical chemistry ,chemistry.chemical_element ,Germanium ,Vacuum deposition ,chemistry ,Optoelectronics ,Wafer ,Thin film ,Fourier transform infrared spectroscopy ,Absorption (electromagnetic radiation) ,business ,Temperature coefficient - Abstract
In this paper, fabricated by MEMS uncooled micro-bolometer detector for the study in the infrared sensitivity enhancement. Absorption layer SiOx-Metal series MDTF (metal-dielectric thin film) by high absorption rate and has a high thermal coefficient of resistance, low noise characteristics were implemented. Then MDTF were made in a vacuum deposition method. And MDTF for the analysis of the physical properties of silicon wafers were fabricated, TCR (temperature coefficient of resistance) value was made in order to measure the glass wafer and FT-IR (Fourier Transform Infrared spectroscopy) values were made in order to measure the germanium window. The analyzed results of MDTF -3 [%/K] has more characteristics of the TCR. And 8~12 um wavelength region close to 70% in the absorption characteristic.
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- 2012
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15. Study on Design of 60 V TDMOSFET for Protection Circuit Module
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Eun-Sik Jung, Man-Young Sung, Hyun-Woong Lee, and Reum Oh
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Materials science ,business.industry ,Electrical engineering ,Battery (vacuum tube) ,Hardware_PERFORMANCEANDRELIABILITY ,On resistance ,Switching time ,Hardware_GENERAL ,MOSFET ,Hardware_INTEGRATEDCIRCUITS ,Breakdown voltage ,State (computer science) ,Power MOSFET ,business ,Voltage drop - Abstract
Protected Circuit Module protects battery from over-charge and over-discharge, also prevents accidental explosion. Therefore, power MOSFET is essential to operate as a switch within the module. To reduce power loss of MOSFET, the on state voltage drop should be lowered and the switching time should be shorted. However there is trade-off between the breakdown voltage and the on state voltage drop. The TDMOS can reduce the on state voltage drop. In this paper, effect of design parameter variation on electrical properties of TDMOS, were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get 65% higher breakdown voltage and 17.4% on resistance enhancement.
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- 2012
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16. A Study on the Electrical Characteristics with Design Parameters in 1,200 V Trench Gate Field Stop IGBT
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Jong-Min Geum, Ey-Goo Kang, Eun-Sik Jung, and Man-Young Sung
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Switching time ,Optimal design ,Planar ,Materials science ,business.industry ,Electrical engineering ,Gate driver ,Breakdown voltage ,Insulated-gate bipolar transistor ,Thermal conduction ,business ,Voltage drop - Abstract
IGBT (insulated gate bipolar transistor) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the on state voltage drop should be lowered and the switching time should be shorted. However, there is Trade-off between the breakdown voltage and the on state voltage drop. To achieving good electrical characteristics, field stop IGBT (FS IGBT) is proposed. In this paper, 1,200 V planar gate non punch-through IGBT (planar gate NPT IGBT), planar gate FS IGBT and trench gate FS IGBT is designed and optimized. The simulation results are compared with each three structures. In results, we optain optimal design parameters and confirm excellence of trench gate FS IGBT. Experimental result by using medici, shows 40% improvement of on state voltage drop.
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- 2012
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17. Electrical Characteristics of Floating Island IGBT Using Trench Gate Structure
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Eun-Sik Jung, Man-Young Sung, Yu-Seup Cho, and Kum-Mi Oh
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Materials science ,business.industry ,Hardware_INTEGRATEDCIRCUITS ,Electrical engineering ,JFET ,Breakdown voltage ,Power semiconductor device ,Field-effect transistor ,Insulated-gate bipolar transistor ,business ,Trench gate ,Voltage ,Floating island - Abstract
Department of Electrical Engineering, Korea University, Seoul 136-701, Korea(Received March 16, 2012; Revised March 21, 2012; Accepted March 22, 2012)Abstract: IGBT (insulated gate bipolar transistor) has been widely used around the power industry as it has good switching performance and its excellent conductance. In order to reduce power loss during switch turn-on state, it is essential to reduce its resistance. However, trade off relationship between breakdown voltage and device conductance is the greatest obstacle on the way of improvement. Floating island structure is one of the solutions. Still, under optimized device condition for the best performance, improvement rate is negligible. Therefore, this paper suggests adding trench gate on floating island structure to eliminate JFET (junction field effect transistor) area to reduce resistance and activate floating island effect. Experimental result by 2D simulation using TCAD, shows 20% improvement of turn-on state voltage drop.Keywords: Floating island, Trench gate, IGBT, Power semiconductor device
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- 2012
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18. A Study on the Design of a ROIC for Uncooled Infrared Ray Detector Using Differential Delta Sampling Technique
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Oh-Sung Kwan, Eun-Sik Jung, Po Lee, Se-Jin Jeong, and Man-Young Sung
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Microelectromechanical systems ,Process variation ,Offset (computer science) ,Materials science ,Optics ,Infrared ,business.industry ,Detector ,Infrared thermal imaging ,Sampling (statistics) ,Astrophysics::Cosmology and Extragalactic Astrophysics ,business - Abstract
A uncooled infrared ray sensor used in an infrared thermal imaging detector has many advantages. But because the uncooled infrared ray sensor is made by MEMS (micro-electro-mechanical system) process variation of offset is large. In this paper, to solve process variation of offset a ROIC for uncooled infrared ray sensor that has process variation of offset compensation technique using differential delta sampling and reference signal compensation circuit was proposed. As a result of simulation that uses the proposed ROIC, it was possible to acquire compensated output characteristics without process variation of offsets.
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- 2011
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19. Dual Field Communication Scheme for UHF (860–960 MHz) Gen2 RFID Chip
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Hee Bok Kang, Bok Gil Choi, Jin-Yong Chung, and Man Young Sung
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RF front end ,Materials science ,business.industry ,Electrical engineering ,Insulator (electricity) ,Hardware_PERFORMANCEANDRELIABILITY ,Condensed Matter Physics ,Chip ,Electronic, Optical and Magnetic Materials ,law.invention ,Capacitor ,Ultra high frequency ,CMOS ,Hardware_GENERAL ,Control and Systems Engineering ,law ,Ferroelectric RAM ,Process integration ,Hardware_INTEGRATEDCIRCUITS ,Materials Chemistry ,Ceramics and Composites ,Electrical and Electronic Engineering ,business - Abstract
The proposed UHF Gen2 RFID chip expands its applications to both FFC and NFC through dual field communication scheme with the dual antenna ports. An RF front end circuit with dual field communication antenna ports and the embedded FeRAM technology on the passive UHF Gen2 RFID chip enables the excellent operating performances and the low cost chip for the tag chip applications from the item level to pallet. The metal-ferroelectric-metal (MFM) capacitor, which is the replacement capacitor device for metal-insulator-metal (MIM) or poly-insulator-poly (PIP), is composed of the ferroelectric material as a dielectric insulator. The MFM capacitor is made simultaneously during the FeRAM memory cell process integration without any additional process integration cost. The MFM capacitor of PZT with the thickness of 0.15μm has the high capacitance value of 20–40 fF at unit μm2 area size. The MFM can be stacked over the CMOS layout area, which saves dramatically the capacitor layout area. The MFM capacitor also has th...
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- 2011
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20. Liquid Lens Module with Wide Field-of-View and Variable Focal Length
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Seung Oh Han, Jun-Ho Seo, Sangwon Seo, Man Young Sung, and Woo Bum Choi
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Microelectromechanical systems ,Capsule Endoscopes ,Materials science ,business.industry ,35 mm equivalent focal length ,Biasing ,Electronic, Optical and Magnetic Materials ,law.invention ,Lens (optics) ,Variable (computer science) ,Optics ,law ,Focal length ,Focus (optics) ,business - Abstract
A novel wide angle and variable-focus imaging module based on a miniaturized liquid lens is presented for capsule endoscopy applications. For these applications, it is desirable to have features such as a wide field of view (FOV), variable focus, small size, and low power consumption, thereby taking full advantage of the miniaturized liquid lens. The proposed imaging module has three aspheric plastic lenses for a wide FOV, and one liquid lens that can change the focal length by as much as 24.5 cm with a bias voltage difference of 23 Vrms for variable focusing. The assembled lens module has an overall length of 8.4 mm and a FOV of 120.5°. The realized imaging module including the proposed lenses is small enough to be inserted into a capsule endoscope, and it is expected to improve the diagnostic capability of capsule endoscopes.
- Published
- 2010
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21. A Study on the Electrical Characteristics with Design Parameters in GaN Power Static Induction Transistor
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Ju-Hyun Oh, Man-Young Sung, Sung-Min Yang, and Eun-Sik Jung
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Materials science ,Silicon ,business.industry ,Wide-bandgap semiconductor ,chemistry.chemical_element ,Gallium nitride ,On resistance ,Power (physics) ,chemistry.chemical_compound ,chemistry ,Breakdown voltage ,Optoelectronics ,business ,Static induction transistor - Abstract
Gallium nitride (GaN), wide bandgap semiconductor, has attracted much attention because they are projected to have much better performance than silicon. In this paper, effects of design parameters change of GaN power static induction transistor (SIT) on the electrical characteristics (breakdown voltage, on resistance) were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get power GaN SIT that has 600 V class breakdown voltage. As a result, we could get optimized 600 V class power GaN SIT that has higher breakdown voltage and lower On resistance with a thin (a several micro-meters) thickness of the channel layer.
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- 2010
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22. BIDIRECTIONAL FLOATING-BASE BJT ESD PROTECTED RFID CHIP
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Bok-Gil Choi, Jinseog Choi, Man Young Sung, Young-Jin Park, Sang-Hyeon Kwak, Hee-Bok Kang, Jin-Yong Chung, Jeong-Ok Ki, Miseok Lee, and Youngwug Kim
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Materials science ,business.industry ,Bipolar junction transistor ,Condensed Matter Physics ,Chip ,Signal ,Electronic, Optical and Magnetic Materials ,Threshold voltage ,Control and Systems Engineering ,Materials Chemistry ,Ceramics and Composites ,Optoelectronics ,Radio frequency ,Electrical and Electronic Engineering ,Antenna (radio) ,business ,Common emitter ,Voltage - Abstract
The maximum peak-to-peak radio frequency (RF) signal antenna voltage level can be extended to reach to over 12 Vpp, −6 V to +6 V. Thus it is desirable that the electro-static discharge (ESD) device does not turn on at the normal operating RF antenna signal voltage level. The turn-on threshold negative voltage of the ESD device of the PN diode type is around −0.5 V in the conventional radio frequency identification (RFID) chip. The asymmetric threshold voltage characteristics of the ESD device of the RFID chip makes the distortion of the RF antenna signal at the high intensity RF input field. In the proposed floating base vertical PNP ESD device, N-type doped N-WELL floating base is sandwiched between two p-type P+ emitter and P-WELL collector. Floating base BJT ESD device enhances the performance of parasitic BJT current in the ESD mode. During the negative voltage phase of RF antenna input signal, the negative voltage of RF antenna input is extended to around −10 V. This extension of RF antenna ...
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- 2010
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23. The Research on Trench Etched Field Ring with Dual Ion-Implantation for Power Devices
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Young-Seok Bae, Man-Young Sung, Sung-Min Yang, and Ju-Hyun Oh
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Ion implantation ,Materials science ,Field (mathematics) ,Atomic physics ,Ring (chemistry) - Abstract
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- 2010
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24. A Study on the Novel TIGBT with Trench Collector
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Young-Seok Bae, Jae-In Lee, Man-Young Sung, and Sung-Min Yang
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Materials science ,Trench ,Breakdown voltage ,Engineering physics - Published
- 2010
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25. A Study on Double Sampling Design of CMOS ROIC for Uncooled Bolometer Infrared Sensor using Reference Signal Compensation Circuit
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Ju-Hyun Oh, Eun-Sik Jung, Man-Young Sung, and Young-Seok Bae
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Materials science ,business.industry ,Noise (signal processing) ,Noise reduction ,Fixed-pattern noise ,Bolometer ,Electrical engineering ,Signal ,law.invention ,Readout integrated circuit ,CMOS ,Sampling (signal processing) ,law ,Electronic engineering ,business - Abstract
A bolometer sensor used in an infrared thermal imaging system has many advantages on the process because it does not need a separate cooling system and its manufacturing is easy. However the sensitivity of the bolometer is low and the fixed pattern noise(FPN) is large, because the bolometer sensor is made by micro electro mechanical systems (MEMS). These problems can be fixed-by using the high performance readout integrated circuit(ROIC) with noise reduction techniques. In this paper, we propose differential delta sampling circuit to remove the mismatch noise of ROIC itself, the FPN of the bolometer. And for reduction of FPN noise, the reference signal compensation circuit which compensate the reference signal by using on-resistance of MOS transistor was proposed.
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- 2010
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26. FLOATING-BASE BJT TYPE ESD DEVICE FOR RFID CHIP
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Bok Gil Choi, Jin-Yong Chung, Gyu-Han Yoon, Man Young Sung, Suk Kyoung Hong, and Hee Bok Kang
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Materials science ,business.industry ,RF power amplifier ,Bipolar junction transistor ,Condensed Matter Physics ,Electronic, Optical and Magnetic Materials ,Human-body model ,Parasitic capacitance ,Control and Systems Engineering ,Materials Chemistry ,Ceramics and Composites ,Optoelectronics ,Electrical and Electronic Engineering ,business ,NMOS logic ,Diode ,Common emitter ,Voltage - Abstract
N-WELL floating base is sandwiched between P+ emitter and P-WELL collector in the proposed floating base vertical PNP electro-static discharge (ESD) protection device. Floating base bipolar junction transistor (BJT) ESD protection device increases the current performance of the parasitic BJT in the ESD mode. During the negative voltage phase of RF antenna signal, the negative voltage range of RF antenna signal is extended to around −10 V at the high RF power field without latch-up failure. The minimum P+ anode layout area of the floating base type BJT ESD device is 400 μm2 for the target ESD voltage of 2000 V in human body model (HBM) mode. The parasitic capacitance of the floating base type BJT ESD protection device is about 0.4 pF. The layout area of the proposed floating base type BJT ESD protection device is 50% smaller that of the conventional NMOS diode type ESD protection device for the target ESD voltage of 2000 V in HBM mode. The rewards of the floating base type BJT ESD device will come...
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- 2009
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27. A Study on the Design of a ROIC for Uncooled Bolometer Thermal Image Sensor using Reference Resistor Compensation
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Seung-Woo Yu, Eun-Sik Jung, Sang-Hyeon Kwak, and Man-Young Sung
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Materials science ,Comparator ,business.industry ,Fixed-pattern noise ,Bolometer ,Electrical engineering ,Microbolometer ,law.invention ,Process variation ,CMOS ,law ,Resistor ,Image sensor ,business - Abstract
As infrared light radiates, the CMOS Readout IC (ROIC) for the microbolometer typed infrared sensor detects voltage or current which is caused by the variation of resistance in the bolometer sensor. A serious problem we may have in designing the ROIC is the value of bolometer and reference resistors will be changed due to process variation. Since each pixel does not have the same value of resistance, fixed pattern noise problems happen during the sensor operations. In this paper, we propose a novel technique to compensate the fluctuation of reference resistance with taking account of process variation. By using a comparator and a cross coupled latch, we will make the value of reference resistor same as the bolometer`s.
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- 2009
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28. Design of field limiting ring employing trench structure for high power devices
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Jong-Seok Lee and Man Young Sung
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Materials science ,Field (physics) ,business.industry ,Electrical engineering ,Condensed Matter Physics ,Curvature ,Electronic, Optical and Magnetic Materials ,Reliability (semiconductor) ,Electric field ,Trench ,Optoelectronics ,Breakdown voltage ,Power semiconductor device ,Electrical and Electronic Engineering ,business ,Voltage - Abstract
Excellent voltage blocking capability and reliability can be obtained by trenching the field-limiting ring site which would be implanted. The trench etch step makes the junction depth deeper so that junction curvature effect and surface breakdown are less happened. The numerical analyses reveal two facts that the trenched field limiting ring has smaller maximum electric field and the electric field peak is deeper from the substrate surface, hence silicon dioxide layer can be protected. Therefore the voltage blocking capability and reliability of the new structure can be improved. The simulated results show that the trenched field limiting ring can have smaller critical electric field and accomplish near 30% increase of breakdown voltage in comparison with the conventional structure.
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- 2009
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29. A Design Method on Power Sense FET to Protect High Voltage Power Device
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Jongmin Lee, Ey-Goo Kang, Yo-Han Kim, Sinsu Kyoung, Jun-Ho Seo, and Man-Young Sung
- Subjects
Materials science ,FET amplifier ,business.industry ,Process (computing) ,Electrical engineering ,High voltage ,Hardware_PERFORMANCEANDRELIABILITY ,Sense (electronics) ,Power (physics) ,Hardware_INTEGRATEDCIRCUITS ,Power semiconductor device ,Power MOSFET ,business ,Hardware_LOGICDESIGN ,Voltage - Abstract
Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration , size of with , and off-state leakage current below . We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.
- Published
- 2009
- Full Text
- View/download PDF
30. CRYPTO BASED EPC C1G2 UHF (860 MHz–960 MHz) PASSIVE RFID TAG CHIP
- Author
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Suk Kyoung Hong, Hee Bok Kang, Jin-Yong Chung, Jong Wook Lee, Bok Gil Choi, Yong Wook Song, and Man Young Sung
- Subjects
Digital electronics ,Magnetoresistive random-access memory ,Materials science ,business.industry ,Electrical engineering ,Hardware_PERFORMANCEANDRELIABILITY ,Condensed Matter Physics ,Chip ,Capacitance ,Electronic, Optical and Magnetic Materials ,law.invention ,Capacitor ,Ultra high frequency ,Hardware_GENERAL ,Control and Systems Engineering ,law ,Ferroelectric RAM ,Hardware_INTEGRATEDCIRCUITS ,Materials Chemistry ,Ceramics and Composites ,Electrical and Electronic Engineering ,business ,EEPROM - Abstract
The metal-ferroelectric-metal (MFM) capacitor in ferroelectric random access memory (FeRAM) security embedded RFID chip is used not only in the memory cell region but also used in the analog and digital circuit area for low cost capacitance device and high security algorithm. MFM based security FeRAM braces for a wide range of security threats such as reverse engineering, cloning, and tampering. High security performance solution of on-chip FeRAM based register key is implemented to prepare against security attacking. RF transferring sensitivity properties with MFM capacitor are almost same or better than that with poly-insulator-poly (PIP) capacitor and metal-insulator-metal (MIM), and MOS capacitor. The measured power consumption of FeRAM embedded RFID chip without crypto processor engine is about 10μ W with the write sensitivity of -18dBm.
- Published
- 2008
- Full Text
- View/download PDF
31. An Analysis of IGBT(Insulator Gate Bipolar Transistor) Structure with an Additional Circular Trench Gate using Wet Oxidation
- Author
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Sinsu Kyoung, Man-Young Sung, and Sang-Hyeon Kwak
- Subjects
Materials science ,business.industry ,Electric field ,Trench ,Bipolar junction transistor ,Electrical engineering ,Optoelectronics ,Breakdown voltage ,JFET ,Insulator (electricity) ,Insulated-gate bipolar transistor ,business ,Voltage drop - Abstract
The conventional IGBT has two problems to make the device taking high performance. The one is high on state voltage drop associated with JFET region, the other is low breakdown voltage associated with concentrating the electric field on the junction of between p base and n drift. This paper is about the structure to effectively improve both the lower on state voltage drop and the higher breakdown voltage than the conventional IGBT. For the fabrication of the circular trench IGBT with the circular trench layer, it is necessary to perform the only one wet oxidation step for the circular trench layer. Analysis on both the on state voltage drop and the breakdown voltage show the improved values compared to the conventional IGBT structure. Because the circular trench layer disperses electric field from the junction of between p base and n drift to circular trench, the breakdown voltage increase. The on state voltage drop decrease due to reduction of JFET region and direction changed of current path which pass through reversed layer channel. The electrical characteristics were studied by MEDICI simulation results.
- Published
- 2008
- Full Text
- View/download PDF
32. A Study on the 1,700 V Rated NPT Trench IGBT Analysis by PIN Diode - PNP Transistor Model
- Author
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Jongmin Lee, Ey-Goo Kang, Man-Young Sung, and Sinsu Kyoung
- Subjects
Transistor model ,Materials science ,business.industry ,Trench igbt ,PIN diode ,Electrical engineering ,Insulated-gate bipolar transistor ,law.invention ,Turn off time ,Qualitative analysis ,Hardware_GENERAL ,law ,Modelling methods ,Trench ,Hardware_INTEGRATEDCIRCUITS ,business - Abstract
This paper presents a comprehensive mathematical analysis and simulation of trench IGBT with the help of PIN-PNP combinational model. Since trench IGBT is characteristically influenced by PIN diode, it may be almost impossible to analyze the trench IGBT using PNP-MOS modeling methods, even PIN-MOS techniques which neglect the hole current components coming into p-base region. A new PIN-PNP complementary cooperational model is developed in order to make up the drawbacks of existing models. It would allow us to make qualitative analysis as well as simulation about switching and on-state characteristics of 1,700 V trench IGBT. Moreover, if we improve the PIN diode effects through the optimization of trench structure, trench IGBT is expected to be one of the most promising devices in the not only high-voltage but also high speed switching device field.
- Published
- 2008
- Full Text
- View/download PDF
33. A New CMOS Read-out IC for Uncooled Microbolometer Infrared Image Sensor
- Author
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Sang Joon Hwang, Ho Hyun Shin, and Man Young Sung
- Subjects
Radiation ,Materials science ,business.industry ,Microbolometer ,Integrated circuit ,Condensed Matter Physics ,Computer Science::Other ,law.invention ,Process variation ,Computer Science::Emerging Technologies ,CMOS ,Sensor array ,law ,Hardware_INTEGRATEDCIRCUITS ,Optoelectronics ,Electrical and Electronic Engineering ,Resistor ,Image sensor ,business ,Instrumentation ,Electronic circuit - Abstract
An uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems (MEMS) process, so the value of the microbolometer resistor has a process variation. Also, the reference resistor, which is used to connect to the microbolometer, is fabricated by a standard CMOS process, and the difference between the values of the microbolometer resistor and the reference resistor generates an unwanted output signal for the same input from the sensor array. In order to minimize this problem, a new CMOS read-out integrated circuit (ROIC) was designed. Instead of a single input mode, a differential input mode scheme and a simple method to compensate the resistor value are proposed. Using results from a computer simulation, it is observed that the output characteristic of the ROIC was improved and the effect of the process variation was decreased without using complex compensation circuits. Based on the simulation results, a prototype device including an ROIC that was fabricated by a standard 0.25um CMOS process and a microbolometer with a 16 x 16 sensor array was fabricated and characterized.
- Published
- 2008
- Full Text
- View/download PDF
34. Design and Analysis of 16 V N-TYPE MOSFET Transistor for the Output Resistance Improvement at Low Gate Bias
- Author
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Man-Young Sung, Y. Kim, and Han-Sin Lee
- Subjects
Materials science ,business.industry ,Electrical engineering ,NAND gate ,Time-dependent gate oxide breakdown ,Hardware_PERFORMANCEANDRELIABILITY ,Gate oxide ,MOSFET ,Hardware_INTEGRATEDCIRCUITS ,Gate driver ,business ,Low voltage ,Hardware_LOGICDESIGN ,Electronic circuit ,Leakage (electronics) - Abstract
In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.
- Published
- 2008
- Full Text
- View/download PDF
35. A Readout IC Design for the FPN Reduction of the Bolometer in an IR Image Sensor
- Author
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Man Young Sung, Sang Joon Hwang, Seung Woo Yu, Eun Sik Jung, and Ho Hyun Shin
- Subjects
Microelectromechanical systems ,Materials science ,business.industry ,Fixed-pattern noise ,Bolometer ,Electrical engineering ,Integrated circuit design ,Chip ,Signal ,Electronic, Optical and Magnetic Materials ,law.invention ,Readout integrated circuit ,law ,Optoelectronics ,Electrical and Electronic Engineering ,Resistor ,business - Abstract
In this paper, we propose and discuss the design using a simple method that reduces the fixed pattern noise(FPN) generated on the amorphous Si() bolometer. This method is applicable to an IR image sensor. This method can also minimize the size of the reference resistor in the readout integrated circuit(ROIC) which processes the signal of an IR image sensor. By connecting four bolometer cells in parallel and averaging the resistances of the bolometer cells, the fixed pattern noise generated in the bolometer cell due to process variations is remarkably reduced. Moreover an bolometer cell, which is made by a MEMS process, has a large resistance value to guarantee an accurate resistance value. This makes the reference resistor be large. In the proposed cell structure, because the bolometer cells connected in parallel have a quarter of the original bolometer`s resistance, a reference resistor, which is made by poly-Si in a CMOS process chip, is implemented to be the size of a quarter. We designed a ROIC with the proposed cell structure and implemented the circuit using a 0.35 um CMOS process.
- Published
- 2007
- Full Text
- View/download PDF
36. Effects of bottom electrode and environmental insulator on thermal distribution of edge contact-type PRAM cell
- Author
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Yong Tae Kim, Min-Soo Youm, and Man Young Sung
- Subjects
Materials science ,General Engineering ,chemistry.chemical_element ,Dielectric ,GeSbTe ,Amorphous solid ,Phase-change memory ,chemistry.chemical_compound ,Thermal conductivity ,Heat flux ,chemistry ,Electrode ,Electronic engineering ,Composite material ,Tin - Abstract
Thermal characteristics of edge contact-type phase change random access memory cells have been investigated with different combinations of bottom electrode and insulator such as Ti and SiO"2, Ti and AlN, and TiN and AlN. At the same melting temperature on the programmable point of Ge"2Sb"2Te"5, we have determined heat flux for each combination: for the Ti and SiO"2, the heat flux is 3.5x10^5J/mm^2s, for the Ti and AlN, and the TiN and AlN, they are 1.7x10^6 and 1.9x10^4J/mm^2s, respectively. These simulated results mean that the combination of TiN and AlN is the most effective for the fast response of phase changing from the amorphous to the crystalline and vice versa since the TiN has lower thermal conductivity than the Ti and the AlN has higher thermal conductivity than SiO"2.
- Published
- 2007
- Full Text
- View/download PDF
37. A Study on the Breakdown Voltage Characteristics with Process and Design Parameters in Trench Gate IGBT
- Author
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Man-Young Sung, Han-Sin Lee, and Ho-Hyun Shin
- Subjects
Materials science ,business.industry ,Electric field ,Trench ,Doping ,Process (computing) ,Electrical engineering ,Breakdown voltage ,Optoelectronics ,Insulated-gate bipolar transistor ,Diffusion (business) ,business ,Trench gate - Abstract
In this paper, effects of the trench angle() on the breakdown voltage according to the process parameters of p-base region and doping concentrations of n-drift region in a Trench Gate IGBT (TIGBT) device were analyzed by computer simulation. Processes parameters used by variables are diffusion temperature, implant dose of p-base region and doping concentration of n-drift region, and aspects of breakdown voltage change with change of each parameter were examined. As diffusion temperature of the p-base region increases, depth of the p-base region increases and effect of the diffusion temperature on the breakdown voltage is very low in the case of small trench angle() but that is increases 134.8 % in the case of high trench angle(). Moreover, as implant dose of the p-base region increases, doping concentration of the p-base region increases and effect of the implant dose on the breakdown voltage is very low in the case of small trench angle() but that is increases 232.1 % in the case of high trench angle(). These phenomenons is why electric field concentrated in the trench is distributed to the p-base region as the diffusion temperature and implant dose of the p-base increase. However, effect of the doping concentration variation in the n-drift region on the breakdown voltage varies just 9.3 % as trench angle increases from to . This is why magnitude of electric field concentrated in the trench changes, but direction of that doesn`t change. In this paper, respective reasons were analyzed through the electric field concentration analysis by computer simulation.
- Published
- 2007
- Full Text
- View/download PDF
38. A FERROELECTRIC BASED PASSIVE RFID TAG FOR UHF (860–960 MHz) BAND
- Author
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Man Young Sung, Young Kwon Sung, Hae Chan Park, Joong Sik Kih, Suk Kyoung Hong, Heon Yong Chang, Kun Woo Park, Jin Hong Ahn, and Hee Bok Kang
- Subjects
Materials science ,business.industry ,High voltage ,Condensed Matter Physics ,Ferroelectric capacitor ,Electronic, Optical and Magnetic Materials ,law.invention ,Capacitor ,Ultra high frequency ,Hardware_GENERAL ,Control and Systems Engineering ,law ,Ferroelectric RAM ,Hardware_INTEGRATEDCIRCUITS ,Materials Chemistry ,Ceramics and Composites ,Optoelectronics ,Electrical and Electronic Engineering ,business ,EEPROM ,Voltage ,Transponder - Abstract
For a longer working distance between passive tags and the reader, the ferroelectric based technologies are proposed in UHF (860–960 MHz) band transponder. The small ferroelectric capacitor layout area with a stacked capacitor structure over circuit region and a large dielectric permittivity of 250 to 500 and small 1T1C cell array layout area with simple 2T2C based reference scheme allow small chip size. The low operation voltage of 1.5 V to 2.0 V without high voltage boosting scheme also contribute to small power consumption and low cost.
- Published
- 2007
- Full Text
- View/download PDF
39. Improvements of Defects by Patterning Using Thermal Nanoimprint Lithography
- Author
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Seung Woo Choi, Woo Beom Choi, Ho Hyun Shin, Hyung Seok Park, Man Young Sung, and Sang Yong Park
- Subjects
chemistry.chemical_classification ,Materials science ,Physics and Astronomy (miscellaneous) ,General Engineering ,General Physics and Astronomy ,Nanotechnology ,Polymer ,Free space ,Nanoimprint lithography ,law.invention ,Compensation effect ,chemistry ,law ,Thermal ,Composite material ,Shrinkage - Abstract
Achieving excellent reliability for imprint patterns molded by stamps for the industrial application of nanoimprint lithography (NIL) is an important challenge. Usually, defects are produced by incomplete filling of negative patterns and the shrinkage phenomenon of polymers in conventional NIL. In our research, we investigated patterns that undergo varied temperature or varied pressure periods during thermal NIL with the goal of resolving issues dealing with the shrinkage and defective filling of polymers. The effects on the formation of polymer patterns in several profiles of imprint processes were also studied. Consequently, we observed that more precise patterns were formed with varied temperature (VT)-NIL and varied pressure (VP)-NIL. NIL has a free space compensation effect on the polymers in the stamp cavities. From the results of the experiments, the polymer's filling capability was improved. The VT-NIL was merged with the VP-NIL for a better filling property. The patterns imprinted using the merged NIL were compared with the results of the conventional NIL. In this study, an improvement in reliability from the results of thermal NIL was achieved.
- Published
- 2007
- Full Text
- View/download PDF
40. Piezoelectric and Dielectric Properties of 0.05Pb(Al.0.5Nb0.5)O3–0.95Pb(Zr0.52Ti0.48)O3Ceramics Doped with Nb2O5and MnO2
- Author
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Hyun Jai Kim, Sang Jong Kim, Man Young Sung, Chong Yun Kang, Ji-Won Choi, Jong Yoon Ha, Dae-Yong Jeong, and Seok-Jin Yoon
- Subjects
Materials science ,Physics and Astronomy (miscellaneous) ,Transition temperature ,Doping ,General Engineering ,Analytical chemistry ,General Physics and Astronomy ,Curie temperature ,Sintering ,Dielectric ,Acceptor ,Piezoelectricity ,Solid solution - Abstract
The solid solution system of 0.05Pb(Al.0.5Nb0.5)O3–0.95Pb(Zr0.52Ti0.48)O3 (PAN–PZT) has been studied for the piezoelectric ultrasonic motor with its high Tc. In this article, we doped the Nb2O5 and MnO2 into the 0.05PAN–0.95PZT ceramics as donor and acceptor respectively and reported the doping effect on the piezoelectric properties. Apparently, Nb2O5 induced the "soft" piezoelectric characteristics. However, as Nb2O5 also affected the sintered density, which is closely related with the piezoelectric properties, it is quite difficult to identify the role of Nb2O5, which might act as the "donor" and/or sintering enhancer. The optimized piezoelectric properties were obtained d33=430 pC/N, kp=59%, Qm=79, and e3T/e0=1690, when PAN–PZT+0.7 wt % Nb2O5 sintered at 1200 °C for 1 h. When MnO2 was doped, Mn4+ ions induced the distortion of perovskite structure and Tc shifted to lower temperature. In addition, d33 and kp decreased and Qm dramatically increased with the addition of MnO2. From these results, it was believed that MnO2 mainly acted as acceptor in PAN–PZT ceramics. The optimized piezoelectric properties were obtained d33=340 pC/N, kp=61.6%, Qm=1725, Tc=392 °C, and e3T/e0=1250, when PAN–PZT+0.7 wt % Nb2O5 with 0.5 wt % MnO2 ceramics sintered at 1200 °C for 1 h.
- Published
- 2007
- Full Text
- View/download PDF
41. Low Temperature Sintering of ZnO-Doped 0.01Pb(Mg1/2W1/2)O3–0.41Pb(Ni1/3Nb2/3)O3–0.35PbTiO3–0.23PbZrO3Ceramics
- Author
-
Seok-Jin Yoon, Sang Jong Kim, Ji-Won Choi, Chong Yun Kang, Hyun Jai Kim, and Man Young Sung
- Subjects
Materials science ,Physics and Astronomy (miscellaneous) ,Scanning electron microscope ,Doping ,General Engineering ,General Physics and Astronomy ,Sintering ,Dielectric ,Piezoelectricity ,Tetragonal crystal system ,Chemical engineering ,visual_art ,X-ray crystallography ,visual_art.visual_art_medium ,Ceramic - Abstract
ZnO was added to 0.01Pb(Mg1/2W1/2)O3–0.41Pb(Ni1/3Nb2/3)O3–0.35PbTiO3–0.23PbZrO3 (0.01PMW–0.41PNN–0.35PT–0.23PZ) ceramics to reduce their sintering temperatures to below 900 °C. The effects of the ZnO additive on the densification and piezoelectric properties of the PMW–PNN–PT–PZ + 0.1 wt % Y2O3 + x wt % ZnO (0≤x≤2.5) ceramics were investigated. The structure of the PMW–PNN–PT–PZ ceramics was found to change from pseudocubic to tetragonal as their ZnO content was increased. The piezoelectric constant, the mechanical quality factor, and the electromechanical factor of the ceramics increased as their ZnO content increased. The optimum piezoelectric properties were found to be d33=594 pC/N, kp=57%, and Qm=64, for PMW–PNN–PT–PZ + 0.1 wt % Y2O3 + 1.5 wt % ZnO sintered at 900 °C for 2 h.
- Published
- 2007
- Full Text
- View/download PDF
42. Characteristics of PMW-PNN-PT-PZ thick films on various bottom electrodes
- Author
-
Chong Yun Kang, Man Young Sung, Ji-Won Choi, Hyun Jai Kim, Sang Jong Kim, and Seok-Jin Yoon
- Subjects
Materials science ,Scanning electron microscope ,Metallurgy ,Condensed Matter Physics ,Microstructure ,Piezoelectricity ,Electronic, Optical and Magnetic Materials ,Mechanics of Materials ,Sputtering ,Electrode ,Screen printing ,Materials Chemistry ,Ceramics and Composites ,Electrical and Electronic Engineering ,Electroceramics ,Composite material ,Polarization (electrochemistry) - Abstract
Characteristics of piezoelectric thick films on various bottom electrodes prepared by screen printing method were investigated. The composition of the ceramics used in this study was 0.01Pb(Mg1/2W1/2)O3–0.41Pb(Ni1/3Nb2/3)O3–0.35PbTiO3–0.23PbZrO3 + 0.1wt% Y2O3 +2.0 wt.%ZnO(PMW-PNN-PT-PZ). The Ag and the Ag-Pd electrodes were coated on SiO2/Si substrate by screen printing method and Pt electrode was deposited on Ti/ SiO2/Si substrate by DC sputtering system. The piezoelectric PMW-PNN-PT-PZ thick films were fabricated on each electrode and annealed by rapid thermal annealing (RTA). The PMW-PNN-PT-PZ piezoelectric thick films on Ag/SiO2/Si has higher remanent polarization (P r) of 22.4 μC/cm2.
- Published
- 2006
- Full Text
- View/download PDF
43. Temperature-Dependent Gate Effect of Sintered HgTe Nanoparticles
- Author
-
Byung Moo Moon, Dongwon Kim, Man Young Sung, Sangsig Kim, Hyun-Suk Kim, and Kyoungah Cho
- Subjects
Colloid ,Materials science ,Physics and Astronomy (miscellaneous) ,Gate effect ,General Engineering ,Analytical chemistry ,General Physics and Astronomy ,Nanoparticle ,Charge carrier ,Gate voltage ,Drain current ,Electronic properties ,Voltage - Abstract
In this study, the electronic properties of sintered HgTe nanoparticles are characterized to determine the type of charge carrier within them, and to investigate their gate effects as a function of temperature. HgTe nanoparticles synthesized by the colloidal method were first deposited on thermally oxidized Si substrates by spin-coating, and then sintered at 150 °C. The sintered nanoparticles were determined to be p-type by analyzing the drain current and drain–source voltage (Id–Vds) relationship as a function of the gate voltage (Vg). The field-effect mobilities of the holes in the sintered HgTe nanoparticles are estimated to be 0.041, 0.036, and 0.022 cm2/(Vs) at 60, 180, and 300 K, respectively. The variation in the slope of the Id–Vds curve as a function of Vg becomes more distinctive as temperature decreases. At temperatures lower than 140 K, an inversion mode was observed for the channel of the sintered nanoparticles.
- Published
- 2006
- Full Text
- View/download PDF
44. Design of Low Power Sigma-delta ADC for USN/RFID Reader
- Author
-
Deuk-Chang Hyun, Jongmin Lee, Ey-Goo Kang, Seung Woo Hong, and Man-Young Sung
- Subjects
Digital electronics ,Materials science ,business.industry ,Clock rate ,Successive approximation ADC ,Hardware_PERFORMANCEANDRELIABILITY ,Data_CODINGANDINFORMATIONTHEORY ,Delta-sigma modulation ,Power (physics) ,Least significant bit ,Hardware_GENERAL ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,business ,Electronic circuit ,Voltage - Abstract
To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is . The averaged power consumption is 1.7 mW.
- Published
- 2006
- Full Text
- View/download PDF
45. Electrical characteristics of single-silicon TFT structure with symmetric dual-gate for kink-effect suppression
- Author
-
Ey Goo Kang, Man Young Sung, Jang Woo Ryu, and Dae Yeon Lee
- Subjects
Transistor channel ,Materials science ,Silicon ,business.industry ,Transistor ,Electrical engineering ,Conductance ,chemistry.chemical_element ,Condensed Matter Physics ,Dual gate ,Molecular physics ,Electronic, Optical and Magnetic Materials ,law.invention ,chemistry ,law ,Thin-film transistor ,Electric field ,Materials Chemistry ,Electrical and Electronic Engineering ,business ,Saturation (magnetic) - Abstract
In this paper, a symmetric dual-gate single-Si TFT, which is composed of three split floating n+ zones, is simulated. This structure remarkably reduces the kink-effect and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by the floating n+ region. This structure allows effective reduction in the kink-effect, depending on the length of the two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA, while that of the conventional dual-gate structure is 0.5 mA, at both 12 V drain and 7 V gate. This result demonstrates 80% enhancement in on-current. In addition, the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction in output conductance in the saturation region, is observed. In addition, the reduction of hole concentration in the channel region, in order to effectively reduce the kink-effect, is confirmed.
- Published
- 2006
- Full Text
- View/download PDF
46. Electrical Characteristics of SRAM Cell with Stacked Single Crystal Silicon TFT Cell
- Author
-
Jin-Ho Kim, Man-Young Sung, Chang-Hun Kim, Jang-Woo Yu, and Ey-Goo Kang
- Subjects
Hardware_MEMORYSTRUCTURES ,Materials science ,business.industry ,Transistor ,Hardware_PERFORMANCEANDRELIABILITY ,PMOS logic ,law.invention ,CMOS ,Memory cell ,Thin-film transistor ,law ,Optoelectronics ,Static random-access memory ,business ,NMOS logic ,Dram - Abstract
There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is , which is too large compared to of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.
- Published
- 2006
- Full Text
- View/download PDF
47. Improved Defect Control Problem using Scaled Down Silicon Oxide Stamps for Nanoimprint Lithography
- Author
-
Woo-Beom Choi, Hyung-Seok Park, and Man-Young Sung
- Subjects
chemistry.chemical_classification ,Materials science ,Silicon ,Silicon dioxide ,business.industry ,chemistry.chemical_element ,Nanotechnology ,Polymer ,Nanoimprint lithography ,law.invention ,chemistry.chemical_compound ,chemistry ,law ,Stress relaxation ,Optoelectronics ,X-ray lithography ,Silicon oxide ,business ,Next-generation lithography - Abstract
We have investigated pattern scaling down of silicon stamps through the oxidation technique, During oxidizing the silicon stamps, silicon dioxide that has 300 nm and 500 nm thickness was grown, and critical deformations were not observed in the patterns. There was positive effect to reduce size of patterns because vertical and horizontal patterns have different orientation. We achieved pattern reduction rate of . In addition, the formation of polymer patterns had been investigated with varied temperature and pressure conditions to improve the filling characteristics of polymers during nanoimprint lithography when pattern sizes were few micrometers. In these varied conditions, polymers had been affected by free space compensation and elastic stress relaxation for filling the cavities. Based on the results, defect control which is an important issue in the nanoimprint lithography were facilitated.
- Published
- 2006
- Full Text
- View/download PDF
48. Wafer Burn-in Method for SRAM in Multi Chip Package
- Author
-
Jang-Woo Ryu, Man-Young Sung, Hoo-Sung Kim, and Jee-Young Yoon
- Subjects
Hardware_MEMORYSTRUCTURES ,Materials science ,Reliability (semiconductor) ,Burn-in ,Process (computing) ,Wafer ,Hardware_PERFORMANCEANDRELIABILITY ,Static random-access memory ,Chip ,Flash memory ,Dram ,Reliability engineering - Abstract
This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.
- Published
- 2005
- Full Text
- View/download PDF
49. Single-silicon TFT Structure for Kink-effect Suppression with Symmetric Dual-gate by Three Split floating N+ Zones
- Author
-
Dae-Yeon Lee, Sang Won Park, Sang-Jun Hwang, and Man Young Sung
- Subjects
Materials science ,Silicon ,chemistry ,business.industry ,Thin-film transistor ,Electrical engineering ,Structure (category theory) ,Optoelectronics ,chemistry.chemical_element ,business ,Dual gate - Published
- 2005
- Full Text
- View/download PDF
50. Design and fabrication of the Built-in Testing Circuit for Improving IC Reliability
- Author
-
Jang-Woo Ryu, Man Young Sung, Sang-Joon Hwang, Jee-Young Yoon, and Hoo-Sung Kim
- Subjects
Materials science ,Reliability (semiconductor) ,Fabrication ,Built in current sensor ,Iddq testing ,Testability ,Reliability engineering - Published
- 2005
- Full Text
- View/download PDF
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