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This study designs a CMOS-MEMS probe chip and fabricates it using the [email protected] CMOS process of the Taiwan Semiconductor Manufacturing Company (TSMC). The post-CMOS procedure is a Micro-electromechanical system (MEMS) technology that involves steps such as lithography, electroless nickel (EN) plating, grinding and dry etching. The probe chip has a through-silicon-via (TSV) package structure combination with the multi-layer interconnections within CMOS processes, which simplifies the wiring layout and improves the connectivity between the probe heads and external devices. In addition, passive components or circuits are inherently integrated with CMOS chips to increase the frequency bandwidth and measurement quality. Finite element analysis is used to design the probe shape and the LIGA-like thick photoresist process using EN plating techniques is used to fabricate the probes. The Ni-P alloy is applied to the probe to thicken and strengthen the cantilever part of the probe. The different deposition areas for several types of cantilever probes on the same chip fabricated by EN plating using different growth rates result in unequal probe heights. Therefore, polishing each plated layer of the probe is a necessary step to guarantee the co-planar surfaces. Finally, the probe structures are suspended using dry etching (RIE, ICP-RIE) and the probe cantilevers have no warp.

In response to the essential role probe cards play in the semiconductor testing industry, a CMOS-MEMS force sensing devices capable of simultaneously monitoring the probe reacting force and electrical test signals is designed for probe cards. The probe reacting force can assist operators immediately to identify a broken, deformed, or worn-out probe and recognize that the measured electrical signals are erroneous. The debug time and cost of the IC test can therefore be effectively reduced. Array-type CMOS-MEMS force sensors are capable of monitoring the status of vertical probe cards on-line in the case of both die-level and wafer-level applications. The force sensor essentially is a Wheatstone-bridge-based piezoresistive force sensor with a small surface area and can be easily fabricated. It consists of a membrane composed of metal, silicon oxide, and a piezoresistive layer made of polycrystalline silicon. Moreover, as the conventional back-etch process can barely handle the increasingly smaller probe pitch, we use front etching to etch out a cavity under the membrane on the silicon substrate in order to deform the membrane during the post-process. For measuring the output signals of the sensors, on-chip circuits to scan and amplify the output signals of the sensors are integrated in the design process. Furthermore, a finite element method is adopted to analyze the structure of the sensors and to find the optimal piezoresistive sensor design. The TSMC 0.35 μm 2P4M process is used to fabricate the force sensors and the circuits. According to the measurement results, the designed sensor reports a sensitivity of 3.114 mV/N/V while a load-bearing force is 0.0294 N.

Thus far, no any effective countermeasure against plating-induced poor uniformity exists in the global packaging market. In this paper, we aim to develop an effective polishing process to improve the poor uniformity existing in advanced double-layer copper pillars. After polishing, the wafer and chip uniformities of copper pillars could be reduced from the original values of 6.8-3.5% and 2.9-0.9%; after reflow, the wafer and chip uniformities of copper pillars reached 3.0% and 1.7%. Excellent uniformity in copper pillars ensures accurate joints, good reliability, high yields, and flexible layouts.

Electroplating is the best process for the manufacture of fine pitch flip chip solder bumps. However, certain unstable electroplating parameters usually cause poorer coplanarity, which affects packaging reliability and yield. This paper attempts to utilize a CMP-like polisher to reduce the nonuniform height deviation after electroplating. The optimization of three major polishing parameters—pad hardness, loading pressure, and polishing speed—enables the polisher to have a higher material removal rate (MRR) and an easier manipulation as compared with chemical mechanical polishing (CMP). After polishing at a pitch size of 100 μm, the overall coplanarity could be decreased sharply from 33±2.5 μm (coplanarity=7.5%) to 28±1 μm (coplanarity=3%) and it even reached 26±0.5 μm (coplanarity=1%) after reflow.

This paper presents an innovative polishing process aimed at leveling rough surface of plating-based flip chip solder bumps so as to get uniform coplanarity across the whole substrate after both electroplating and reflow processes. This polishing mechanism is characteristic of combining mechanical-dominated polishing force with slight chemical reaction together. A large number of extremely but inevitably rugged mushroom-like structures after electroplating are drastically smoothed down with the help of this newly-developed polishing process. Nearly 70@mm solder bumps in height with two different profiles as square and circle on the substrates reach as flatly as +/-3@mm between different substrates after reflow process; +/-2.5@mm in single substrate; and even +/-1@mm in die, respectively. Besides, surface roughness among the solder bumps is simultaneously narrowed down from Ra 0.6 to Ra 0.03 along with the coplanarity improvement. Excellent uniformity and smooth surface roughness in solder bumps are absolutely beneficial to pile up and deposit in the following steps in MEMS and semiconductor fields.

In recent years, as mobile equipment such as cellular phones and PDAs become drastically higher performance and downsized, semiconductor devices are rapidly becoming more integrated and higher speed. As a result of high integration, the pitches of electrode pads in chips are becoming smaller than 100 µm. In some devices, pad pitches are as small as 40 µm.

This paper presents a common platform for packaging micromachined devices, such as motion sensors, microphones, actuator RF switches etc. The method utilizes the semiconductor process, MEMS technique and Electroless technique to build the CMOS-MEMS chip and the second chip, which are then bonded together face to face. Herein, the second chip can further contain Micro Controller Unit (MCU) or antenna system, which can efficiently enhance the performances of CMOS-MEMS sensor without occupying extra packaging area and increasing the process cost. Moreover, the second chip is designed to a common platform which can serve different size or several micromachined components of CMOS-MEMS chip in a single platform.

In this study, we use the standard TSMC 0.35 μm 2P4M process to design CMOS-MEMS probe chip. MEMS technology involves the following steps such as lithography process, electroless nickel (EN) plating process, grinding process and dry etching process. The probe chip has through silicon via (TSV) package structure, and the combination of CMOS process within the multi-layer interconnections, which could assist the connection between the probes head the external devices, and reduce the difficulty of wiring layout. In addition, passive components or circuits could be integrated with the CMOS chip to improve the frequency bandwidth and measuring quality. So far, MEMS probe exist a shortcomings that are not able to be integrated with the CMOS process, and the testing cost. The finite element method was adapted to design of probe shapes and sizes. The LIGA-like thick photoresist process and EN plating technique was used in this study, Ni-P alloy to increase the thickness of the cantilever probe to strengthen its support strength were also applied. When the probe cantilever through the EN plating of deposition time, the uneven surface was appeared, each layer structure is used by polishing process to achieve the surface coplanarity. Finally, the probes structure were suspended by the dry etching process (RIE, ICP-RIE), and this study successfully fabricated chips forming one of the probe.

This paper relates to the method of formation and structure of pillar bump with shape and dimension controllable, it specifically relates to a technique that uses polishing and planarization technique to let all pillar bumps have dimension and shape matching the design.

This paper presents the Carbon Nano-coils (CNCs) which were coated with nickel (Ni) and gold (Au) using electro-less plating method. The property of products was observed by Scanning Electron Microscope (SEM) and Energy Dispersive Spectrometer (EDS) and X-ray diffraction (XRD) and Fourier transformed infrared spectroscopy (FTIR), which shows formation of oxygen containing groups such as OH and COOH. We modified the CNCs by using acid wash and electro-less plating, and tested their magnetic property. The nickel film was deposited on the surface of the CNCs by electro-less plating for 10 mins at PH 7.0, and bath-temperature was 70°C. And we found the CNCs with surface coated by high ratio of Ni were attracted by the external magnetic field. The thickness of the deposit and the deposition rate may be controlled through careful variation of the coating time and plating bath temperature.

The miniaturization of components and systems has been progressing rapidly due to the developments in Micro-Electro-Mechanical (MEMS). The greatest advantage of micro injection molding is that it can massively produce micro-components rapidly with low-cost. Due to the poor flow capability of melting plastics into micro channel, and the additions of the engineering-plastics and fibers, it is difficult to inject the melted plastics into the cavities of the mold. In order to apply the microinjection technique in the fabrication of microfluidic chip, raising cavity surface temperature will be one of the solutions and reduce the cycle-time. High mold temperature not only improves the replication capacity of micro-structures but also effectively reduces molecular orientation. Therefore, developing systems for rapidly heating and cooling for injection of microfluidic chip is the main objective of this study. Numerical computations of eddy currents and heat conduction have been carried out by using the finite-element method (FEM). A simulation tool is also developed by integration of both thermal and electromagnetic analysis modules of ANSYS. Coil current, coil to plate distance and heating time are varied for both experiments and simulations. Several modifications, such as spacing in between coil turns, the distance of the workpiece and the coils, and dimensional parameters, are carried out. The capability and accuracy of simulations on the induction heating are verified from experiments, the simulated temperature distributions show reasonable agreement with measured results. To evaluate the feasibility and efficiency of induction heating on the mold surface temperature control. The size of mold plate heated by induction heating is 80×70×10 mm3. The mold plate can be rapidly heated from room temperature to about 120°C in 20 s. The simulation of the mold surface temperature with respect to time is consistent with measured results.

In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the UIW (Uniformity in Wafer) could be sharply decreased from 6.37% after plating to 1.7% after polishing and even to 1.7% after reflow throughout the entire 4 inch wafer.

This paper aims to provide a fine-pitch Sn/0.7Cu lead-fee solder bumps fabrication process that is characterized by using a novel plating-friendly polishing mechanism to transform the plated-based Sn/0.7Cu lead-free solder bumps with huge height deviation into smooth and uniform ones. The final experimental results showed that the UIW (uniformity in wafer) of Sn/0.7Cu solder bumps at 50 mum pitch size could be sharply decreased from 9.19% after plating to 3.54% after polishing and even 1.9% after reflow throughout the entire 4 inch silicon wafer. Most importantly, after reflow uniformity could be controlled as accurately as within 1.25% in each dies (10 mm times 10 mm) respectively. This proposed polishing mechanism could assist the plating-based fine-pitch solder bumps in precisely getting better coplanarity so as to enhance packaging reliability and yield.

This thesis aims to apply a standard CMOS process to develop a Wheatstone-bridge- based piezoresistive force sensor. This CMOS-compatible piezoresistive force sensor with small area and easy fabrication consists of a thin-film receiver made by passivation, silicon oxide and a piezoresistive layer made by the polycrystalline silicon respectively. Additionally, utilize the RLS etching process offered by CIC to conduct its post-process. Combining MEMS with the electroforming process enables us to fabricate vertical spring probes featuring strength feedback function, making it possible to monitor wafer-level probe card either on-line or off-line. In traditional, the working probe naturally sustaining repeated bending actions and wear, absolutely needs a mechanism to prevent it from being damaged, caused by the change of the probe's geometry and the increase of the contact resistance. Therefore, in this study, we develop a CMOS-based chip in connection with the electroformed probes to detect each of their counterforce, contact resistance to evaluate if their contact force and coplanarity are controlled within safe range. This breakthrough technology of installing a piezoresistive force sensor to fully monitor the working probe cards helps to save time and manpower for broken probes repair.

This study presents a new type of cobra probe by using MEMS technology for IC testing. The fabrication includes photolithography, electroforming and polishing process. Mechanical properties of the cobra probe are measured and no fracture or deformation is found after applying a force of 3 g for as many as 20,000 times. Its contact resistance averages nearly 680 mOmega and overdrive is approximately up to 30 um.

Commonly used in forming high aspect ratio structures, thick-layer polymers generally differ in surface uniformity due to relatively higher viscosity. This problem would become even worse along with the increase of substrate diameter. Non-uniform coated photoresist surface would cause bonding failure and dimensional error in advanced three-dimensional packaging and WLP (wafer level packaging). Using traditional CMP (chemical mechanical polishing) to polish such a huge height deviation is time-consuming, high-cost and low-efficiency. This paper aims to provide an innovative polishing mechanism that is particularly suitable to polish wider height deviation in microstructures. Predominately in mechanical polishing force entails it surpassing CMP in MRR (material removal rate) by 300 times. The final experimental result indicates that the polishing rate could reach as fast as 20 um/min. Most importantly, the whole uniformity after polishing could be sharply decreased from 105plusmn3 mum (uniformity: 2.8%) to 95plusmn1 mum (uniformity: 1%). This proposed polishing mechanism could assist sticky polymers in precisely getting better uniformity so as to enhance packaging accuracy, reliability and yield.

In order to get better electrical performance and layout flexibility, adopting different profiles of solder bumps in flip chip packaging is inevitable. In this study, we mainly compare the effects of reflowed solder bumps coplanarity by altering their contours, magnitudes and volumes. By using Surface Evolver simulating software, we could further analyze and compare the differences in coplanarity between the practical plating-based solder bumps and their final simulating results. Since the plating-based solder bumps are usually prone to suffer rugged mushroom-like structures after plating, extremely influencing their coplanarity after reflow, we thus utilize an extra polishing mechanism after plating to eliminate those annoying mushroom-like structures in order to promote coplanarity after reflow. Utilizing this uniform coplanarity enables us to obtain optimization in solder bumps layout. The final results indicate that the volumes and magnitudes of solder bumps have great impact on bumps' height and fatigue after reflow, while the shapes have relatively minor influence. Finally, combining the simulation results with the practical fabrication models gives us the benefits of getting better design and layout in solder bumps used in the future advanced flip chip packaging.

Electroplating is by far the most promising process to fabricate fine pitch solder bumps in flip chip. However, rugged surface and poor coplanarity resulted from numerous variable plating parameters generally cause short circuit and broken circuit to affect packaging reliability. With the great demand for decreasing pitch size below 100 um, solder bumps' coplanarity would become more and more important as considering alignment in advanced three-dimensional packaging and WLP (Wafer Level Packaging). This paper aims to provide a creative solder bump fabrication process that is characterized by using a polishing mechanism to transform the plated solder bumps with huge height deviation into smooth and uniform ones. Predominately in mechanical polishing force enables it to polish much wider height deviation, typically affected by poor current distribution in tiny area plating. Equipped with a specific soft non-woven polishing pad and a self-designed substrate holder, the polisher features large MRR (Material Removal Rate), easy manipulation and high efficiency. The final experimental results indicate that the polishing rate in lead-free Sn-Cu solder bumps could reach as fast as 4~5 um/min, almost 50 times faster than CMP (Chemical Mechanical Polishing). The whole coplanarity of solder bumps at 80 um pitch size could be sharply decreased from 33plusmn2.5 um (7.5%) after plating to 28plusmn1 um (3%) after polishing and even 26plusmn0.5 um (1%) after re flow. Most importantly, each single die (6 mmtimes6 mm) after re flow could be controlled as accurately as within 0.5%. This proposed polishing mechanism could assist the plating-based solder bumps in precisely getting better coplanarity so as to enhance packaging reliability and yield.

The plating-based gold solder bumps with ultra-high average uniformity across the entire 4 inch wafer by using an unprecedented polishing process are fabricated in this paper. This sophisticated polisher uses the same two polishing mechanisms, mechanical and chemical forces, as those traditionally applied to polish wafer surface with the chemical mechanical polishing (CMP) equipment, but has relatively far less cost than it. Not only can we acquire uniform surface among the solder bumps after plating, but we are able to largely improve the bumps' surface roughness, both of which are two key elements for enhancing assembly yield rate and solving the difficulty in stripping thick photoresist as well. Meanwhile, we employ some compatible measuring instruments such as a surface profile instrument (alpha-Step), an optical microscope (OM) with convertible magnification and a scanning electron microscope (SEM) to identify and evaluate the solder bumps' thickness and surface morphology after each procedure for the sake of strictly controlling their quality. The final results indicate that the poor solder bumps with approximately 9.24% in deviation after plating is narrowed down as accurate as within 3.98% across the entire wafer after polishing, representing the uniformity significantly improved to 2.5 times in comparison with those without using any treatment after electroplating. Even on some local area (die), the uniformity can be accurately controlled up to 1.5%. The surface roughness, on the other hand, has been advanced from the original Ra 0.6 after electroplating to near Ra 0.03 after polishing

In this paper, we present a microelectromechanical systems (MEMS) probe chip compatible with the standard complementary metal–oxide–semiconductor (CMOS) process for testing RF devices and bumps. Using the standard CMOS process to fabricate in advance the multilayer interconnections between metal layers can conveniently facilitate the layout of the space transformer. In a limited area, we design two probe structures of meander shape and spiral shape. The probe cantilever consists of a CMOS membrane and the probe pitch is 150 µm. The probe tip is fabricated successfully by electroless nickel (EN) plating process and the height of the probe tip approaches 106 µm. In particular, grinding and polishing processes are employed to level the rough surface of the probe tip so as to obtain uniform coplanarity. Moreover, in the photoresist SU-8 removal process, the plasma removal process is used instead of the stripper solutions to protect the probe tip from being damaged. The meander shape and spiral shape of probe cantilevers are successfully suspended by an inductively coupled plasma (ICP) etch system and the probe cantilevers have no warpage.

In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the uniformity in wafer (UIW) could be sharply improved from 4.31% after plating to 2.88% after polishing and even to 2.54% after reflow throughout the entire 4 inch wafer.