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We fabricated bismuth (Bi) nanowires with low energy electron beam lithography using silver (Ag) nanocrystal shadowmasks and a subsequent chlorine reactive ion etching. Submicron-size metal contacts on the single Bi nanowire were successfully prepared by in situ focused ion beam metal deposition for transport measurements. The temperature dependent resistance measurements on the 50 nm wide Bi nanowires showed that the resistance increased with decreasing temperature, which is characteristic of semiconductors and insulators.

The relationships of the electrical properties of irradiated MOS structures to processed-induced surface defects have been investigated. It has been found that the radiation-induced perturbations in oxide space-charge and interface states relate directly to the density of oxidation-induced stacking faults and edge dislocations. The density of such surface defects depends on both the structural properties of the starting silicon and the fabrication procedures. Oxidation-induced stacking faults are strongly related to the oxidation conditions, such as temperature, time, and ambiance. High-frequency CV, quasi-static CV, and ac conductance techniques were used to determine the interface state densities and flat-band voltage distributions. It has been found that, in addition to interface states, exposure to ionizing radiation causes gross non-uniformities in trapped positive space-charge. Using secondary ion mass spectrometry (SIMS) on an MOS sample possessing a high density of stacking faults, it has been shown that positive charge-species drift to the SiO2/Si interface and form clusters in a random fashion similar to that of the defects delineated by differential etching. Based on the known relationship of surface generation lifetime on surface defects pre-irradiation lifetime has been demonstrated as an effective electrical parameter for the prediction of the total-dose radiation sensitivity of MOS devices.

Several versions of the 1802 CMOS microprocessor were subjected to Co-60 irradiations. Total dose data is provided for production line parts from two vendors, a specially processed radiation hard lot, and one developmental SOS unit. The increase in total dose failure level from 1 x 104 to 5 x 105 rads(Si) for the specially processed Parts proves the feasibility of hardening the Si-gate LSI technology used for the 1802.

Transient nuclear radiation responses of integrated circuits can be simulated by irradiating the backside of the silicon die with a pulsed infrared laser. This technique facilitates the implementation of an effective, low cost, nondestructive, 100 percent transient radiation screen at wafer probe. Analytic predictions are shown to correlate closely with experimental results on an operational amplifier and its test cell components.

A long-term transient response mechanism has been discovered in certain GaAs FETs and FET logic circuits exposed to low level (~ 100 rad) ionizing radiation pulses. Recovery times ranging from 1 to 70 seconds have been measured following room temperature exposures. Charge trapping within the semiinsulating GaAs substrate appears to be a mechanism responsible for the observed behavior. Experiments conducted between 0° and 200°C have identified an acceptor level characterized by an activation energy in the 0.7 to 0.8 eV range.

The long-term transient radiation response in ion implanted GaAs FETs induced by flash x-ray or electron pulses has been reduced by the incorporation of a deep buried p-layer beneath the active n-layer. Reductions in the change in drain current of up to two orders of magnitude were measured in FETs with the buried p-layer compared to FETs with only an n-implanted channel following a 100 rad x-ray pulse. This improvement in radiation tolerance is attributed to shielding of the active n-layer by the conducting p-layer from the effects of radiation induced trapped substrate charge.

Flash x‐ray measurements have been made on GaAs metal semiconductor field effect transistor structures fabricated in both Cr‐doped and undoped semi‐insulating substrate material in order to characterize the levels responsible for long term transients in these devices. Prominent electron and hole traps with activation energies in the 0.76–0.90‐eV range have been identified. The main electron trap, which is present in both Cr‐doped and undoped substrates, appears to be primarily responsible for the observed transient response. However, traps related to Cr‐doping also contribute to the transient behavior.

Complete radiation sensitivity assessments of integrated circuits can now be performed at the wafer level using a new system, the Hardness Assurance Wafer Probe, HAWP. This system utilizes a pulsed Nd: YAG infrared laser impinging on the backside of the wafer to evaluate the transient behavior of the circuits. A low energy X ray source collimated to a single die site actually performs total dose irradiations. Finally, special electrical measurements are used to enable a prediction of the neutron sensitivity of bipolar devices. The HAWP System is described and correlations of wafer probe results to conventional radiation tests for a digital part type are provided.

The radiation dose dependence of the energy profile of the interface state density, NFS(E), has been monitored for the first time by using quasistatic MOS C-V techniques. The surprising result is that the radiation-induced increases in the interface state density are proportional to the pre-irradiation density regardless of the energy position in the band gap (away from the band edges) and in spite of the differences in the nature of the pre-and post-irradiation interface states. Both undoped and aluminum-implanted silicon dioxide films were used in the MOS devices investigated in this effort. Also, the dose dependence of the capture crosssection for carriers, ?, has been determined for the first time by combining quasistatic MOS capacitance measurements with gate-controlled IEBO measurements. Initial cross section values were consistent with those determined by different techniques, ~6×10-16 cm2. Contrary to the results that have been reported by other workers, ? was found to be relatively constant with respect to changes in NFS. Consequently, the radiation-induced rise in the surface recombination velocity is interpreted as being primarily due to an increase in NFS.

Additional process controls which have been implemented by semiconductor manufacturers in order to produce low threshold voltage CMOS integrated circuits are shown to significantly improve the radiation hardness of such devices. In particular, this improvement is directly correlated with reduced concentrations of the sodium impurity which results in smaller threshold voltage shifts for the p-channel (negatively biased) transistors. Further, it has been shown that n-channel devices can be hardened by the technique of ion implantation on production line integrated circuits. Thus, digital CMOS devices hard to greater than a Mrad(Si) have been realized.

The amplitude of long term, pulse-radiation-induced transients in ion implanted GaAs FET's has been reduced by up to two orders of magnitude by the addition of a deep buried p-layer beneath the active n-layer. The p-layer was formed by ion implantation of Be to depth of 0.8 µm below the Si implanted n-active channel. Backgating was also greatly reduced as indicated by a much smaller amplitude transient response following application of a positive gate pulse and by the absence of light sensitivity and looping in the current/ voltage (I-V) characteristics.

Two types of devices representative of very-largescale-integration, 64k dynamic RAMs and 68000 microprocessors, have been studied in a total dose ionizing radiation environment. Both types of parts show an improved hardness compared to earlier test results for large-scale-integrated dynamic RAMs and microprocessors. This indicates that the previously developed downward trend of radiation hardness versus circuit complexity may not continue to prevail.