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We evaluated the limit of scaling bottom electrode contact (BEC) heater size and high resistivity heater to reduce writing current. It was found that the resistivity of heater should be increased for reducing writing current below the heater size of about 50 nm without any undesirable increase of resistance of the crystalline state (SET state, Rset). It was shown in the numerical simulations that the dissipated heat loss through BEC during melting GST was decreased in the increase of resistivity of heater. In addition, we analyzed the resistance components contributing to the total set resistance. It was observed that the undesired sharp increase of Rset as the BEC size decreases below 50 nm was attributed to the resistance component of GST–BEC interface. In the case of high resistivity heater, the contributions of both incomplete crystallization and heater itself were enhanced.

In this paper, we propose a novel cell transistor using retracted Si/sub 3/N/sub 4/-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-/spl mu/m technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si/sub 3/N/sub 4/-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-/spl mu/m technology and beyond.

In this paper, a 0.15 /spl mu/m embedded DRAM technology is described which provides a cost-effective means of delivering high bandwidth, low power consumption, noise immunity, and a small foot print chip. The key technologies for high performance transistors are dual thickness gate oxide, dual work-function gate with Si/sub 3/N/sub 4/ capped Ti polycide, and selective Co silicidation of source/drain diffusion by Si/sub 3/N/sub 4/ liner. In order to increase the memory cell efficiency, all memory cell contacts in DRAM arrays are formed by self-aligned contact (SAC) etching. Low temperature Al/sub 2/O/sub 3/ stacked cell capacitor with hemispherical grain (HSG) makes it possible to realize the sufficient storage capacitance in DRAM arrays and the high performance transistor. The CMP planarization of interlayer dielectric enlarges the depth of focus for lithography and enables the multilevel metallization. These integration technologies can be fairly extendible to the future embedded DRAM in 0.13 /spl mu/m technology node and beyond.

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction.

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.