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Three homoleptic Pt(II) metal complexes [Pt(imPz)2] (1), [Pt(imiz)2] (2), and [Pt(imMz)2] (3) were synthesized from the treatment of Pt(DMSO)2Cl2 and functional imidazolyl pyrazole in refluxing tetrahydrofuran (THF). Alternatively, the heteroleptic Pt(II) complexes [Pt(imPz)(fppz)] (4), [Pt(imiz)(fppz)] (5), and [Pt(imMz)(fppz)] (6) were obtained from the treatment of a common intermediate [Pt(fppzH)Cl2] with a corresponding imidazolyl chelate. Pt(II) complexes 1, 2, and 5 were studied by single-crystal X-ray diffraction to reveal the corresponding packing arrangement in their crystal lattices, among which both homoleptic complexes 1 and 2 formed monomeric species, while heteroleptic 5 aligned as a dimer with a nonbonding Pt···Pt contact of 3.574 A. Subsequent photophysical examinations showed that the homoleptic 1-3 and heteroleptic 4-6 exhibited the structured sky-blue ππ* emission and structureless light-green-emitting metal-metal-to-ligand charge transfer (MMLCT) emission in the solid state, respectively. A shortened Pt···Pt interaction of approximately 0.34-0.35 nm was confirmed in thin films of all heteroleptic Pt(II) complexes 4-6 by grazing-incidence X-ray diffraction (GIXD) analyses. Finally, Pt(II) complex 6 was employed as a dopant in the fabrication of organic light-emitting diode (OLED) devices with varied doping ratios, among which OLEDs with only 1 wt % 6 in the SimCP host exhibited a maximum external quantum efficiency (EQE) of 5.8% and CIEx,y values of 0.20, 0.31. In contrast, OLEDs using a nondoped architecture (i.e., 100% of 6 in the emitting layer (EML)) achieved a maximum EQE of 26.8%, current efficiency (CE) of 91.7 cd A-1, and power efficiency (PE) of 80.1 lm·W-1 and CIEx,y values of 0.41, 0.55, manifesting their versatility in various degrees of stacking assemblies and hence facile color-tuning capability on OLEDs.

For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or few-layer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. The monolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design.

This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics of highly-scaled tri-gate n-MOSFETs with InGaAs channel based on ITRS 2021 technology node through numerical simulation corroborated with theoretical calculation. This paper indicates that, when studying short-channel effects in III-V FETs, one has to account for quantum-confinement, or else predictions will be pessimistic. Due to 2-D quantum-confinement, the DIBL of the InGaAs tri-gate devices can be significantly suppressed and be comparable to the Si counterpart. Besides, for highly-scaled InGaAs tri-gate NFETs, the impact of buried-oxide thickness on DIBL becomes minor, and the DIBL sensitivity to the fin-width and gate-length variations can also be suppressed by the quantum-confinement effect. This paper may provide insights for tri-gate device design using III-V high-mobility channel materials.

This letter evaluates and analyzes the impacts of random variations on cell stability and write-ability of low-voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) node with the aid of atomistic TCAD mixed-mode simulations. Our study indicates that, for 6T SRAM, the monolayer/bilayer TMD devices may fail to provide the $6\sigma $ yield requirement for read static noise margin (RSNM) due to severe metal-gate work function variation in spite of their excellent electrostatics, and hence circuit techniques, such as bootstrapped dynamic power rails or the standard 8T cell, are needed. Besides, $R_{\mathrm {SD}}$ as a major concern of TMDs should be less of an issue for near-/sub-threshold SRAMs for ultra low-power applications. For the standard 8T cell structure, the RSNMs of both monolayer and bilayer 8T SRAMs improve significantly, and the bilayer 8T SRAM exhibits better write static noise margin (WSNM). In addition, write-assist techniques (including negative bit-line, boosted word-line, and lower cell supply) for improving WSNM are examined and shown to be more effective for monolayer 8T SRAMs than the bilayer counterparts.

For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is more suitable for relaxed channel length and high-performance SRAM applications.

This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics for tri-gate germanium-on-insulator (GeOI) p-MOSFETs through theoretical calculation by analytical solution of 3-D Poisson’s equation corroborated with TCAD numerical simulation. It is found that, relative to the silicon-on-insulator counterpart, there exists a build-in negative substrate bias in the GeOI PFET. This built-in substrate bias, stemming mainly from the large discrepancy in bandgap between Ge and Si, pulls the carriers toward the channel/BOX interface and thus degrades the DIBL of the GeOI PFET beyond what permittivity predicts. This new mechanism has to be considered when designing or benchmarking tri-gate GeOI p-MOSFETs.

We investigate the analog performance of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) MOSFETs. The device analog metrics including the transconductance (g m ), output resistance (R o ) and intrinsic gain (g m × R o ) for TMD device are investigated using 3D atomistic TCAD simulations. It is shown that bilayer TMD devices exhibit better analog performance compared with monolayer TMD devices. The impacts of different mobility ratios of bilayer TMD devices to monolayer TMD devices are examined.

We comprehensively evaluate and benchmark the performance of pass-transistor logic (PTL) circuits using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 node. Our study indicates that the higher V T of bilayer TMD devices significantly degrades the performance of single pass-transistor based circuits compared with the monolayer counterparts despite the higher mobility of bilayer TMD devices. The effect can be mitigated by using full transmission gate or providing a complementary path.

This paper investigates the impact of backgate bias (Vbg) on the sensitivity of threshold voltage (Vth) to process and temperature variations for ultra-thin-body (UTB) GeOI and InGaAs-OI MOSFETs. Our study indicates that the quantum-confinement effect significantly suppresses the Vbg dependence of the Vth sensitivity to process and temperature variations. Since Si, Ge, and InGaAs channels exhibit different degrees of quantum confinement, the impact of quantum confinement has to be considered when one-to-one comparisons among hetero-channel UTB devices regarding variability are made. Our study is crucial to the robustness of multi- Vth designs with advanced UTB technologies.

2-D transition metal dichalcogenides (TMDs) such as MoS 2 and WSe 2 (Fig. 1(a)) are very attractive for future ultimately scaled low-power CMOS devices owing to their atomic-scale thickness, adequate band-gap, and pristine surface (without dangling bonds) [1–3]. Our previous study [4] has evaluated the stability of MoS 2 -n/WSe 2 -p SRAMs with planar technology. However, the process complexity of heterogeneous integration of distinct materials for n/p-FETs can become a concern. Monolithic 3-D integration [5] offers the possibility to independently optimize the n-FETs and p-FETs at distinct tiers. It has also been envisioned [6] that monolithic 3-D integration combined with the extremely scaled TMD devices may offer the ultimate solution for future ultra-high density ICs and SRAMs (Fig. 1(c)).

We evaluate and benchmark the performance of logic circuits and stability/performance of 6T SRAM cells using monolayer and bilayer TMD devices based on ITRS 2028 (5.9nm) technology node. For the performance benchmarking of logic circuits, the tradeoff between electrostatic integrity (monolayer favored) and carrier mobility (bilayer favored), and the issues regarding the uncertainties in the mobility ratio and source/drain series resistance, the underlap device design, and the off-current spec., etc. are comprehensively addressed. In the evaluation of SRAM cells, the cell immunity to random variations is focused. Besides, the impact of high RSD of TMD materials on RSNM variability is also investigated. The source/drain underlap design is shown to alleviate the larger variability of bilayer SRAM cells. Finally, with superior electrostatics and immunity to random variations, the monolayer TMD devices are favored for low-power logic and SRAM applications; while the bilayer devices, with higher carrier mobility, are more suitable for high-performance logic and SRAM applications.

Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.

This paper investigates the impact of quantum confinement (QC) on the backgate-bias (Vbg) modulated subthreshold and threshold-voltage (Vth) characteristics of ultra-thin-body germanium-on-insulator (UTB GeOI) MOSFETs using an analytical solution of the Schrodinger equation verified with TCAD numerical simulation. Our study indicates that the QC effect reduces the sensitivity of the subthreshold swing to Vbg. In addition, the sensitivity of Vth to Vbg can be enhanced by the QC effect particularly for electrostatically well-behaved UTB MOSFETs with triangular potential well. Aside from that, the sensitivity of Vth roll-off to Vbg is reduced by the QC effect. Since Ge and Si channels exhibit different degrees of QC due to different quantization effective mass, the impact of QC has to be considered when one-to-one comparisons between GeOI and SOI MOSFETs regarding the backgate-bias modulated threshold-voltage and sub-threshold characteristics are made. Our study may provide insights for multi-Vth device/circuit designs using advanced UTB GeOI technologies.

This paper investigates the electrostatic integrity (EI) of ultra-thin-body (UTB) germanium-on-insulator (GeOI) and InGaAs-OI n-MOSFETs considering quantum confinement (QC) using a derived analytical solution of Schrodinger equation verified with TCAD numerical simulation. Although the electron conduction path of the high-mobility channel device can be far from the frontgate interface due to high channel permittivity, our study indicates that the quantum confinement effect can move the carrier centroid toward the frontgate and, therefore, improve the subthreshold swing (SS) of the UTB device. Since InGaAs, Ge, and Si channels exhibit different degrees of quantum confinement due to different quantization effective mass, the impact of quantum confinement has to be considered when one-to-one comparisons among UTB InGaAs-OI, GeOI, and SOI MOSFETs regarding the subthreshold swing and electrostatic integrity are made.

This letter reports a built-in effective body-bias effect in ultra-thin-body (UTB) hetero-channel III-V-on-insulator n-MOSFETs. This effect results from the discrepancies in elec- tron affinity and the effective density-of-states of conduction band between the III-V and conventional Si channels. Our study indicates that, in addition to permittivity, it is the built- in effective body-bias effect that determines the drain-induced- barrier-lowering characteristics of the hetero-channel devices. This intrinsic effect has to be considered when one-to-one comparisons among various UTB hetero-channel MOSFETs regarding the electrostatic integrity are made.

The intrinsic drain-induced-barrier-lowering (DIBL) characteristics of ultra-thin-body (UTB) MOSFETs with various III–V channel materials (such as GaAs, In0.53Ga0.47As, In0.7Ga0.3As, InAs, In0.2Ga0.8Sb, InSb, etc.) has been investigated and benchmarked with the Si device. Our results indicate that the DIBL of the III–V-on-insulator devices can be worse than what permittivity predicts. The underlying mechanism is proposed. We also show that, with the aid of quantum confinement (along the channel-thickness direction), the DIBL of the III–V devices can be comparable to the Si device.

This work investigates the quantum-capacitance induced drain-current loss for multi-gate In 0.53 Ga 0.47 As n-MOSFETs with tri-gate structure (fin aspect-ratio AR=1) and double-gate FinFET-like structure (AR>>1) through ITRS 2018-2024 technology nodes using quantum-mechanical simulation corroborated by model calculation. The quantum capacitance stemming from the small electron effective mass of InGaAs channel significantly degrades the intrinsic inversion capacitance and thus induces drain-current loss for multi-gate InGaAs devices. Our study indicates that the mobility enhancement of InGaAs devices (against Si counterparts) should be at least ∼3X and ∼2.5X, respectively, for tri-gate and FinFET-like structures to compensate the quantum-capacitance induced drain-current loss.

We have reported anomalous electrostatic behaviors in drain-induced-barrier-lowering (DIBL), threshold voltage (V T ) roll-off, subthreshold swing (SS), and intrinsic V T variability in GeOI p-MOSFET. The underlying mechanism responsible for these anomalous electrostatic characteristics is attributed to the valence-band offset between Ge channel and Si substrate due to their significant discrepancy in bandgap. This band offset results in an effective built-in forward body bias in GeOI pFET, and leads to different carrier profiles between GeOI pFET and nFET.

Variability of nanoscale MOSFETs has been an obstacle to CMOS scaling. For future CMOS devices, hetero-channel using Ge or III-V compounds such as InGaAs have been proposed as performance boosters [1-2]. The variability, however, is further aggravated for these high-mobility materials due to their higher permittivity. The ultra-thin body (UTB) structure has been considered as a promising solution to improve device electrostatic integrity (EI) [3-4]. Using the UTB with thin buried oxide (BOX) structure also enables efficient threshold voltage (Vth) modulation via backgate bias (Vbg) [3-4] for power-performance optimization. In addition, the adaptive body bias (ABB) technique has been widely used to compensate the die-to-die variation [5-6], whereas the within-die Vth variation also changes with Vbg. With the scaling of device dimensions, the quantum confinement (QC) effect may become significant and impact the pertinent Vbg-dependence of Vth variability for the UTB hetero-channel devices. In this work, using TCAD atomistic simulation, we investigate the impact of Vbg on the intrinsic variability of gate line-edge-roughness (LER) for UTB SOI, GeOI, and InGaAs-OI MOSFETs considering quantum confinement.