Search

This paper presents an experimental investigation of the turn-ON of nanoscale T-RAM cells under the transient conditions given by the depletion of the $p$ -base from holes. Data reveal that hole depletion increases the dynamic turn-ON voltage of the device for a stretch of time depending on the gate and anode bias during the hold phase and on the gate voltage used for device sensing. The results are explained considering that the gate and anode biases during hold affect the rate of hole generation bringing the device back to its equilibrium condition, while the gate voltage applied to sense the state of the gated-thyristor determines the $p$ -base potential and, therefore, the amount of holes in the $p$ -base required to turn the device on.

This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated p-base. In particular, with proper selection of the low and high gate levels, the stationary hole concentration in the p-base leads the thyristor to its high current state while hole depletion results in an orders-of-magnitude lower anode current. This opens the possibility for a DRAM technology with a simple back-end process and fast WRITE and READ operations with low voltage requirements.

This letter presents a detailed experimental investigation of the current-voltage characteristics of deca-nanometer gated-thyristors, highlighting that strong differences exist between the static and the dynamic operation of these devices. In particular, results reveal that the forward-breakover voltage determining thyristor turn-on does not depend only on the applied gate voltage, but also on the rise time of the applied gate pulse, decreasing for fast pulse fronts. This is explained in terms of a higher electron injection from the cathode to the anode triggering device turn-on when the gate switching time is shorter than that required for holes to leave the p-base.

This work investigates the performance of the statistical impedance field method in the analysis of the amplitude of random telegraph noise fluctuations in nanoscale MOS devices. Considering different channel doping profiles, we show that this method offers a practical compromise between accuracy and computational loads, allowing a good assessment of the RTN amplitude statistics while resulting in non-negligible errors on the single microscopic samples where atomistic doping strongly contributes to non-uniformities of channel inversion and to percolative source-to-drain conduction.

The paper proposes an extended majority-carrier dc and ac two-dimensional physical model for the simulation of ion-implanted MESFETs on semi-insulating and p-type substrates, including the static and dynamic treatment of partly ionized impurity levels. The numerical implementation of the model is discussed, and it is shown how numerical ill-conditioning problems suggest the implementation of a full two-carrier model for the simulation of devices with un-depleted p-type substrates. A discussion is presented on the interpretation of rate-dependent anomalies related to the frequency behaviour of the small-signal parameters, and the importance of simulating a backgate electrode is stressed. Finally, comparisons are given with ac and dc data measured on p-buried layer Siemens devices.