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A boost LED driver featuring a high PWM dimming ratio and optimized efficiency is presented. This LED driver, which has a low dropout voltage and is able to drive 3–7 LEDs in series with constant output current and fast PWM dimming, provides an alternative technique for brightness adjustment. A dual-path control scheme with automatic switching and state maintenance is proposed. Meanwhile, a cascode current mirror structure is applied with the output transistor multiplexed as an LED PWM dimming transistor. Implemented in 0.5 μm 25 V BCD process, the measurement results show that a voltage conversion range of 5 V input to 6–24 V output with constant output current is obtained. With automatically switching dual-path control and an optimized current mirror, the response time during PWM dimming is reduced to as low as 240 ns and the efficiency keeps above 89% over a wide PWM dimming ratio @ 250 mA output current.

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48.

A stable LDO using VCCS (voltage control current source) is presented. The LDO is designed and implemented on GF 2P4M 0.35 μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR (equivalent series resistance) of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 μs is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.

A broadband programmable gain amplifier (PGA) with a small gain step and low gain error has been designed in 0.13 μm CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error. The proposed PGA shows a decibel-linear variable gain from −4 to 20 dB with a gain step of 0.1 dB and a gain error less than ±0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.

This paper describes a low-power portable sensor interface dedicated to sensing and processing electrocardiogram (ECG) signals. Dry electrodes were employed in this ECG sensor, which eliminates the need of conductive gel and avoids complicated and mandatory skin preparation before electrode attachment. This ECG sensor system consists of two ICs, an analog front-end (AFE) and a successive approximation register analog-to-digital converter (SAR ADC) containing a relaxation oscillator. This proposed design was fabricated in a 0.18 μm 1P6M standard CMOS process. The AFE for extracting the biopotential signals is essential in this ECG sensor. In measurements, the AFE obtains a mid-band gain of 45 dB, a bandwidth from 0.6 to 160 Hz, and a total input referred noise of 2.8 μV rms while consuming 1 μW from the 1.8 V supply. The noise efficiency factor (NEF) of our design is 3.4. After conditioning, the amplified ECG signal is digitized by a 12-bit SAR ADC with 61.8 dB SNDR and 220 fJ/conversion-step. Finally, a complete ECG sensor interface with three dry copper electrodes is demonstrated in real-word setting, showing successful recordings of a capture ECG waveform.

A wideband receiver RF front-end for IR-UWB applications is implemented in 0.13 μm CMOS technology. Thanks to the direct sub-sampling architecture, there is no mixing process. Both LNA and VGA work at RF frequencies. To optimize noise as well as linearity, a differential common-source LNA with capacitive cross-coupling is used, which only consumes current of 1.8 mA from a 1.2 V power supply. Following LNA, a two-stage current-steering VGA is adopted for gain tuning. To extend the overall bandwidth, a three-stage staggered peaking technique is used. Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6–7 GHz, a minimum noise figure of 4.5 dB and a largest IIP3 of −11 dBm. The core receiver (without test buffer) consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm2 area.

A gated ring oscillator (GRO) based time-to-digital converter (TDC) is presented. To enhance the resolution of the TDC, a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2. The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm2. According to the measurement results, the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range, the maximum clock frequency of this circuit is larger than 200 MHz. Under a 1 V power supply, with a 200–800 ps input time difference, the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

A 10 MHz ripple-based on-time controlled buck converter is presented. A novel low-cost dual ripple compensation, which consists of coupling capacitor compensation and passive equivalent series resistance compensation, is proposed to achieve a fast load transient response and robust stability simultaneously. Implemented in a 2P4M 0.35 μm CMOS process, the converter achieves fix-frequency output with a ripple of below 10 mV and an overshoot of 10 mV at 400 mA step load transient response. With width optimization of the power transistors in an ultra-heavy load and PFM control in a light load, the efficiency stays at over 83% for a load range from 20 mA to 1.5 A and the peak efficiency reaches 90.16%.

A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented. It features a selectable interpolation rate (2x/4x/8x) with a programmable interpolation filter. To improve the high-frequency performance, a "fast switching" technique that adds additional biasing to the current-switch is adopted. The data-dependent clock loading effect is also minimized with an improved switch control by using a double latch. This DAC is implemented in 65 nm CMOS technology with an active area of 1.56 mm2. The measured SFDRs are 70.05 dB at 250 MS/s for 120.65 MHz input sine-wave signal and 64.24 dB at 960 MS/s for 56.3 MHz input sine-wave signal, respectively.

A high efficiency class-I linear audio power amplifier (PA) with an adaptive supply is presented. Its efficiency is improved by a dynamic supply to reduce the power transistors' voltage drop. A gain compression technique is adopted to make the amplifier accommodate a single positive supply. Circuit complicity and chip area are reduced because no charge pump is necessary for the negative supply. A common shared mode voltage and a symmetric layout pattern are used to minimize the non-linearity. A peak efficiency of 80% is reached at peak output power. The measured THD+N before and after the supply switching point are 0.01% and 0.05%, respectively. The maximum output power is 410 mW for an 8 Ω speaker load. Unlike switching amplifiers, the class-I amplifier operates as a linear amplifier and hence has a low EMI. The advantage of a high efficiency and low EMI makes the class-I amplifier suitable for portable and RF sensitive applications.

A fully integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented. It supports SAW-less operation for WCDMA. To improve the linearity in terms of both IP3 and IP2, the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization, current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs. A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO. In addition, a constant-gm biasing with an on-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance. This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13 m CMOS. The measurement results show that owing to this high-linearity RF front-end, the receiver achieves 6 dBm IIP3 and better than C60 dBm IIP2 for all modes and bands.

A wideband variable gain amplifier (VGA) implemented in 0.13 μm CMOS technology is presented. To optimize noise performance, an active feedback amplifier with 15 dB fixed gain is put in the front, followed by modified Cherry—Hooper amplifiers in cascade providing variable gain, which adopt dual loop feedback for bandwidth extension. Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation, respectively. Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of −29 dBm at the lowest gain state, while the minimum noise figure is 9 dB at the highest gain state. The core VGA (without test buffer) consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.

A low-phase-noiseU-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 m CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 s, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.

A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130-nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return-to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.

A 1500 mA, 10 MHz self-adaptive on-time (SOT) controlled buck DC—DC converter is presented. Both a low-cost ripple compensation scheme (RCS) and a self-adaptive on-time generator (SAOTG) are proposed to solve the system stability and frequency variation problem. Meanwhile a self-adaptive power transistor sizing (SAPTS) technique is used to optimize the efficiency especially with a heavy load. The circuit is implemented in a 2P4M 0.35 μm CMOS process. A small external inductor of 0.47 μH and a capacitor of 4.7 μF are used to lower the cost of the converter and keep the output ripple to less than 10 mV. The measurement results show that the overshoot of the load transient response is 8 mV @ 200 mA step and the dynamic voltage scaling (DVS) performance is a rise of 16 μs/V and a fall of 20 μs/V. With a SAPTS technique and PFM control, the efficiency is maintained at more than 81% for a load range of 20 to 1500 mA and the peak efficiency reaches 88.43%.

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm2. It achieves 35 dB conversion gain across 4.9–5.1 GHz, a noise figure of 7.2 dB and an IIP3 of −16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.

A dual-mode analog baseband with digital-assisted DC-offset calibration (DCOC) for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13 μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm2.

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13- m CMOS process for W-CDMA application is presented. The transformer not only accomplishes output impedance matching, but also acts as a balun for converting differential signals to single-ended ones. Under a supply voltage of 3.3 V, the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%. The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB, respectively. The die size is 0.91 1.12 mm 2 .

A highly linear, high output power, 0.13 μm CMOS direct conversion transmitter for wideband code division multiple access (WCDMA) is described. The transmitter delivers 6.8 dBm output power with 38 mA current consumption. With careful design on the resistor bank in the IQ-modulator, the gain step accuracy is within 0.1 dB, hence the image rejection ratio can be kept below −47 dBc for the entire output range. The adjacent channel leakage ratio and the LO leakage at 6.8 dBm output power are −44 dBc @ 5 MHz and −37 dBc, respectively, and the corresponding EVM is 3.6%. The overall gain can be programmed in 6 dB steps in a 66-dB range.

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier (THA) in 0.13 m CMOS for an impulse radio ultra-wideband (IR-UWB) receiver is presented. The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency. This paper presents, to our knowledge for the second time, a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz. In this design, a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz. A resistive averaging technique is carefully analyzed to relieve noise aliasing. A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed, power consumption and noise aliasing. The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s. The core power of the ADC is 30 mW, excluding all of the buffers, and the active area is 0.6 mm 2 . The ADC achieves a figure of merit of 3.75 pJ/conversion-step.

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented. The mathematical models for the behavior of the synthesizer's spur and phase noise are analyzed, and the optimization methodology is proposed. Measurement results exhibits that the frequency synthesizer's integrated phase noise is less than 1° (1 kHz to 100 MHz) with a 4.375 GHz carrier (after divide-by-2), and the reference frequency spur is below −60 dBc operating with a 33 MHz reference clock. The frequency synthesizer is fabricated on a standard 0.13 μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.

This paper presents a novel, fully integrated transmitter for 3–5 GHz pulsed UWB. The BPSK modulation transmitter has been implemented in SMIC CMOS 0.13 μm technology with a 1.2-V supply voltage and a die size of 0.8 × 0.95 mm2. This transmitter is based on the impulse response filter method, which uses a tunable R paralleled with a LC frequency selection network to realize continuously adjustable pulse parameters, including bandwidth, width and amplitude. Due to the extremely low duty of the pulsed UWB, a proposed output buffer is employed to save power consumption significantly. Finally, measurement results show that the transmitter consumes only 16.3 pJ/pulse to achieve a pulse repetition rate of 100 Mb/s. Generated pulses strictly comply with the FCC spectral mask. The continuously variable pulse width is from 900 to 1.5 ns and the amplitude with the minimum 178 mVpp and the maximum 432 mVpp can be achieved.

A dual mode charge pump to produce an adaptive power supply for a class G audio power amplifier is presented. According to the amplitude of the input signals, the charge pump has two level output voltage rails available to save power. It operates both in current mode at high output load and in pulse frequency modulation (PFM) at light load to reduce the power dissipation. Also, dynamic adjustment of the power stage transistor size based on load current at the PFM mode is introduced to reduce the output voltage ripple and prevent the switching frequency from audio range. The prototype is implemented in 0.18 μm 3.3 V CMOS technology. Experimental results show that the maximum power efficiency of the charge pump is 79.5% @ 0.5x mode and 83.6% @ 1x mode. The output voltage ripple is less than 15 mV while providing 120 mA of the load current at PFM control and less than 18 mV while providing 300 mA of the load current at current mode control. An analytical model for ripple voltage and efficiency calculation of the proposed PFM control demonstrates reasonable agreement with measured results.

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL). An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL. We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch. The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply. The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is −89 and −118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset, respectively; and the reference frequency spur is below −77 dBc. The chip size is 0.32 mm2 and the power consumption is 30.6 mW.

A speaker driver applied to class G/class I with a single phase power supply is presented. Gain expanding and compressing technology are employed in the signal processing circuit to optimize power dissipation. The circuit is implemented in 0.18 μm N-well CMOS. Experimental results show that the speaker driver has a good audio sound quality and power efficiency. Less than 0.006% THD at a low power range and less than 0.4% at a medium power range can be obtained with a 1 kHz sine wave signal. Maximum output power of 360 mW can be gained at a load of 8 Ω. The power efficiency is about twice that of a traditional class AB driver at the power range of 80 mW and shows more than 18% improvement at the higher output power range.

A low power 12-bit 200-kS/s SARADC is proposed. This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator. The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB, respectively, with a power consumption of 72 μW at a 200-kS/s sampling rate. The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.

A sigma—delta (ΣΔ) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio (SDR) system is presented. The conversion frequency, transfer function of the digital filter and the ΣΔ modulator, word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA, TD-SCDMA and GSM standards. The ΣΔ DAC fabricated in SMIC 0.13-μm CMOS process occupies a die area of 0.72 mm2, while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage. The measured SFDR is 62.8/60.1/75.5 dB for WCDMA/TD-SCDMA/GSM mode, respectively.

A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13-μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter (ADC) is presented. For power optimization, the voltage supply of the digital part is lowered, and the offset voltage of the latch is self-calibrated. Targeted for better linearity and lower noise, an improved digital-to-analog converter capacitor array layout strategy is presented, and a low kick-back noise latch is proposed. The chip was fabricated by using 0.18 μm 1P6M CMOS technology. The ADC achieves 61.8 dB SNDR and dissipates 455 nW only, resulting in a figure of merit of 220 fJ/conversion-step. The ADC core occupies an active area of only 674 × 639 μm2.

This paper presents the design and implementation of a 14-bit, 100 MS/s CMOS digital-to-analog converter (DAC). Analog background self-calibration based on the concept of analog current trimming is introduced. A constant clock load switch driver, a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance. The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33 × 0.97 mm2 of the core area. The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog, respectively. The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB, respectively. The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.

A novel toggled flip-flop (TFF) divide-by-two circuit (DTC) and its optimization method based on a large-signal analysis approach are proposed. By reducing the output RC constant in tracking mode and making it large in latching mode, compressing the internal signal swing as well as compensating the current leaked in the latching mode, the operating frequency range is greatly expanded. Implemented in a SMIC 0.13 μm RF CMOS process with a 1.2 V power supply, it can work under an ultra-wide frequency band ranging from 320 MHz to 29.6 GHz. Experimental results show that two phase-locked loops (PLLs) with the proposed DTC can achieve in-band phase noise of −94 dBc/Hz @ 10 kHz under 4224 MHz operating frequency and −84 dBc/Hz @ 10 kHz under 10 GHz operating frequency, respectively. The power consumption of the proposed DTC is reduced by almost 50% compared with the conventional counterparts.

A fully integrated VCO and divider implemented in SMIC 0.13-μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented. The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals for 802.11a WLAN in 5.8 GHz band or for 802.11b/g WLAN and Bluetooth in 2.4 GHz band can be obtained by a frequency division by 2 or 4, respectively. A 6 bit switched capacitor array is applied for precise tuning of all necessary frequency bands. The testing results show that the VCO has a phase noise of—113 dBc @ 1 MHz offset from the carrier of 5.5 GHz by dividing VCO output by two and the VCO core consumes 3.72 mW. The figure-of-merit for the tuning-range (FOMT) of the VCO is −192.6 dBc/Hz.

A low jitter, low spur multiphase phase-locked loop (PLL) for an impulse radio ultra-wideband (IR-UWB) receiver is presented. The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output. In this design, a noise and matching improved voltage-controlled oscillator (VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks. By good matching achieved in the charge pump and careful choice of the loop filter bandwidth, the reference spur is suppressed. A phase noise of -118.42 dBc/Hz at a frequency offset of 1 MHz, RMS jitter of 1.53 ps and reference spur of -66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement. The chip was manufactured in 0.13 m CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm 2 area.

A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and offset cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm2.

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of −94 dBc/Hz and −114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of −63 dB with the second order passive low pass filter.

A fast-hopping 3-band (mode 1) multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below –50 dBc, while the in-band spurious tones are below –34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 × 1.8 mm2.

An integrated single-inductor dual-output (SIDO) switching DC–DC converter is presented. The outputs are specified with 1.2 V/400 mA and 1.8 V/200 mA. A decoupling small signal model is proposed to analyze the multi-loop system and to design the on-chip compensators. An average current control mode is introduced with lossless, continuous current detection. The converter has been fabricated in a 0.25 μm 2P4M CMOS process. The power efficiency is 86% at a total output power of 840 mW while the output ripples are about 40 mV at an oscillator frequency of 600 kHz.

This paper presents an implementation for improving muti-level cell NOR flash memory program throughput based on the channel hot electron (CHE) temperature characteristic. The CHE Ig temperature characteristic is analyzed theoretically with the Lucky electron model, and a temperature self-adaptive programming algorithm is proposed to increase Ig according to the on-die temperature. Experimental results show that the program throughput increases significantly from 1.1 MByte/s without temperature self-adaptive programming to 1.4 MByte/s with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput in Ref. [1].

A fully integrated phase-locked loop (PLL) is presented for a single quadrature output frequency of 3.96 GHz. The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation. An adaptive frequency calibration loop is incorporated into the PLL. The capacitance area in the loop filter is largely reduced through a capacitor multiplier. Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area. Measurement results show that the PLL achieves a phase noise of–70 dBc/Hz at 10 kHz offset and −113 dBc/Hz at 1 MHz offset. The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps. The reference spur level is less than −68 dBc.

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented. The calibration and control system, which is adopted to ensure an achievable signal-to-noise ratio and bit error rate, consists of a digitally controlled, high resolution dB-linear automatic gain control (AGC), an inphase (I) and quadrature (Q) gain and phase mismatch calibration, and an automatic frequency calibration (AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer. The calibration system has a low design complexity with little power and small die area. Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB, respectively, which means the image rejection ratio is better than 60 dB. In addition, the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.

A receiver for SRDs implemented by the 0.35 μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR (image rejection ratio) so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of s−60 dBm and a control gain of 60 dB. The S11 reaches −20 dB at 433 MHz and −10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm2 including the bias circuit.

A novel low power RF receiver front-end for 3–5 GHz UWB is presented. Designed in the 0.13 μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below −8.5 dB across the 3.1–4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of −11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.

A 3–5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13 μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2 × 1.4 mm2.

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (ΣΔ) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of –3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm2.

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.