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This thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM array of eight four-bit words including refresh circuitry. In the last several years, there has been significant research investigating the possibilities of producing much faster, lower power and high density DRAM using GaAs. Thus far, this research has yielded success on a limited basis using special materials and fabrication techniques. This design, tested and simulated using HSPICE, supports a memory access time of approximately three nanoseconds, faster than present commercial Static Random Access Memory (SRAM). The logic circuits are designed using GaAs enhancement-mode and depletion-mode (E/ D) metal semiconductor field-effect transistors (MESFETs). Charge storage is facilitated by a single GaAs MESFET connected to a parallel plate capacitor and the required minimum time between refresh is approximately three milliseconds. Power consumption is acceptable and fabrication by Vitesse Semiconductor Corporation using the HGaAs3 process is in progress. The design techniques, power consumption and timing are discussed and demonstrated for the basic logic circuits and the memory array read, write and refresh cycles. A significant increase in DRAM memory bandwidth is gained narrowing the memory bandwidth differential between primary memory and the processor. http://archive.org/details/galliumrsenidedy1094539875 Lieutenant, United States Navy Approved for public release; distribution is unlimited.

Cache memories, which are the level of memory between the CPU and the main memory, hold small amounts of data and instructions, and allow the CPU to access the contents in them very quickly. This significantly reduces the read access time for the CPU if the required information is available in the cache. However, caches are small and can only hold the most commonly used data and instructions required by the CPU. When information requested does not appear in the cache, a "cache miss" occurs and the CPU must fetch the required data from the main memory. The Read Protection Buffer reduces this time=costly read access by attempting to predict the possible miss address, and pre-fetch the read data. http://archive.org/details/thedesignndimple1094523856 Lieutenant, United States Navy Approved for public release; distribution is unlimited.

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined within this thesis. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix. http://archive.org/details/anengineeringmet1094527024 Lieutenant Commander, United States Navy Approved for public release; distribution is unlimited.