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A hardware‐efficient slope‐error (SE) algorithm based four‐level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC‐768 JTOL mask by at least 0.35 UI at the bit error rate of 10−12. The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm2. [ABSTRACT FROM AUTHOR]

A 65 nm CMOS 20 Gb/s transmitter with a low‐voltage differential signalling (LVDS) driver is presented. A novel power‐efficient pre‐emphasis method that eliminates power wasting in conventional pre‐emphasis is proposed. The input to the driver is pre‐coded so that the pre‐emphasis taps only inject current to the output nodes upon voltage level transition of the output signal. Current does not flow through the pre‐emphasis taps when there is no transition. Simulation results show that the proposed pre‐emphasis achieves the same output waveform and pre‐emphasis capability as the conventional approach while consuming less power. [ABSTRACT FROM AUTHOR]

A deeper SSC estimator used as a CDR with a low power mechanism based on third‐order architecture is proposed to suppress the disadvantage of the conventional third‐order CDR happening at the switching points of SSC (spread spectrum clocking). For 10 Gbit/s data speed, the depth of its SSC tracking may be up to 10000ppm at 30 kHz which helps to reduce more EMI. [ABSTRACT FROM AUTHOR]