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The application of line-of-sight (LOS)- multiple-input multiple-output (MIMO) to the back-haul or fronthaul between a macro-cell and small cells is promising from the viewpoint of low-cost deployment in 4G and 5G cellular heterogeneous networks. This paper presents the bit error rate (BER) performance of low-density parity-check (LDPC)-coded single-carrier 2 × 2 LOS-MIMO using frequency domain equalization (FDE) in the 3rd generation partnership project (3GPP) tapped delay line (TDL) channel models. Computer simulation results show that the average BER of less than 10−8 is achieved with the LDPC coding rate of R = 1/2 or lower in TDL-D and E channel models with the number of non-line-of-sight (NLOS) delayed paths of L NLOS = 13 and 14, that suffer from independent Rayleigh fading. Moreover, we show that high quality such as the average BER of 10−8 is achieved for LDPC- coded 2 × 2 LOS-MIMO using FDE when L NLOS is equal to five or fewer even with the high coding rate of 8/9 in the TDL-E channel model.

This paper presents the bit error rate (BER) performance of frequency domain equalization (FDE) using low-density parity-check (LDPC) coding for single-carrier line-of-sight (LOS)-multiple-input multiple-output (MIMO) multiplexing. We use partial LDPC coding with double Gray mapping and collaborative decoding, which is suitable for a high coding rate such as 0.9. Computer simulation results show that partial LDPC coding decreases the required received signal-to-noise power ratio (SNR) at the bit error rate (BER) of $10^{-7}$ by approximately 1.0 dB compared to that for full LDPC coding for 256QAM in a Rummler fading channel. We show that the required received SNR at the BER of $10^{-7}$ using partial LDPC coding is decreased by more than 6.6 dB compared to that without LDPC coding even for the deep notch depth of -20dB regardless of the relationship between the notch frequencies in the direct and cross links for 2×2 LOS-MIMO in a Rummler fading channel. Therefore, we conclude that FDE using partial LDPC coding with double Gray mapping and collaborative decoding is effective in achieving a low BER for single-carrier LOS-MIMO in microwave radio backhaul channels.

Recently, we proposed a high-order circular quadrature amplitude modulation (QAM) constellation scheme with a high low-density parity-check (LDPC) coding rate that is suitable for partial LDPC coding associated with parallel double Gray mapping for microwave mobile backhaul. This paper presents the bit error rate (BER) performance of circular QAM when using a combination of Wiener filter based pilot symbol assisted (PSA) and phase locked loop (PLL) phase noise (PN) estimation and compensation methods. Computer simulation results show that the required received signal-to-noise power ratio (SNR) at the BER of 10−6 using the PSA and PLL PN estimation and compensation is decreased by approximately 0.3, 0.6, and 1.3 dB for the pilot symbol insertion interval of 25, 50, and 100 symbols, respectively, compared to that using only the PSA PN estimation for circular 1024QAM. Accordingly, we show that the PLL PN estimation is effective in decreasing the pilot symbol overhead of PSA PN estimation for circular QAM, which is robust against time-varying PN.

This paper proposes a design for a high-order circular quadrature amplitude modulation (QAM) constellation using partial low-density parity-check (LDPC) coding associated with parallel double Gray mapping aiming at the application to a microwave radio backhaul to deal with time-varying phase noise channels. In the proposed circular QAM constellation design, we first design the best constellation in which the same number of signal points is mapped to all concentric rings. Then, we decrease the number of signal points in the inner rings and remap the signal points to the newly added rings outside the original rings while maintaining high affinity to the double Gray mapping feature. Computer simulation results show that partial LDPC coding with double Gray mapping decreases the required received signal-to-noise power ratio (SNR) at the bit error rate (BER) of 10−6 by approximately 0.2 dB compared to full LDPC coding for a high LDPC coding rate such as 0.9. We also show that the proposed circular 1024QAM decreases the required received SNR at the average BER of 10−6 by approximately 0.5 dB compared to that for rectangular 1024QAM.

In this paper, we present a novel phase error estimation scheme for low-density parity-check (LDPC) coded high-order quadrature amplitude modulation (QAM) transmission systems, and we provide a theoretical analysis of its performance. The scheme uses known pilot symbols which are assumed to be placed at equally spaced positions, and phase errors occurred at these pilot symbol positions are first estimated. They are then interpolated over the other positions by using a Wiener filter (WF), and estimation accuracy is next refined by using an LDPC code-aided phase-locked loop (PLL). We present an efficient implementation of this two-stage, Pilot-Symbol-Assisted and Code-Aided (PSA/CA) scheme and evaluate its performance by means of power spectrum analysis. We determine the mean square error at each step of the PSA/CA scheme, and we find an optimal value of the noise equivalent loop bandwidth of the PLL under the assumption that local oscillator phase noise can be modeled as a single-pole single-zero model. We show through simulations that the PSA/CA scheme has a very high phase noise tolerance comparable to that of state-of-the-art phase estimation schemes and provides a computationally efficient alternative.

This paper shows that several attractive classes of quasi-cyclic (QC) low-density parity-check (LDPC) codes can be obtained from affine planes over finite fields. One class of these consists of duals of one-generator QC codes. Here, for codes contained in this class, the exact minimum-distance and a lower bound on the multiplicity of the minimum-weight codewords are presented. It is shown that the lower bound on the multiplicity provides a very accurate indication of the bit error performance at moderate and high signal-to-noise ratios, and thus error-floor behavior can be easily predicted. Also discussed is a class consisting of codes from circulant permutation matrices. An explicit formula for the rank of the parity-check matrix is presented for these codes. Furthermore, it is shown that each of these codes can be identified as a code constructed from a constacyclic maximum distance separable (MDS) code in a similar manner to the RS-based LDPC codes presented by Chen et al. and Djurdjevic et al. Experimental results show that a number of high rate QC-LDPC codes with excellent error performance are contained in these classes

This letter presents a class of quasi-cyclic (QC) low-density parity-check (LDPC) codes which are efficiently encodable and have better memory efficiency than other randomly constructed QC-LDPC codes. The parity-check matrix of the codes is obtained from a block circulant matrix that is generated from a self-reciprocal generator polynomial of a maximum distance separable (MDS) code by replacing some of its block entries by all zero matrices. We show by simulations that the codes can achieve excellent error performance.

We propose and investigate a novel FEC coding scheme based on a concatenation of QC-LDPC with single-parity-check codes. High performance of a Q-limit of 5.8 dB with 20.5% overhead has been achieved with FPGA-based simulations.

In this paper, we present an efficient systematic encoding algorithm for quasi-cyclic (QC) low-density parity check (LDPC) codes that are related to cyclic maximum-distance separable (MDS) codes. The algorithm offers linear time complexity, and it can be easily implemented by using polynomial multiplication and division circuits. We show that the division polynomials can be completely characterized by their zeros and that the sum of the respective numbers of their zeros is equal to the parity-length of the codes.

A novel decoder architecture is presented for quasi- cyclic low-density parity-check (QC-LDPC) codes. The architecture implements a min-sum algorithm and uses feedback shift-registers to store all the messages exchanged within the algorithm. This shift-register-based min-sum (SRMS) decoder does not require complex interconnections between processors and registers and is amenable to a simple, high throughput hardware implementation. A codec with the SRMS decoder for high-rate codes of length 4095 bits has been fabricated with a 0.15 mum, 1.5 V CMOS technology. The decoder has a gate count of 693 K gates and achieves a throughput of 155.52 Mbps (STM-1) using high-order QAM schemes. Measurement results show that a microwave radio system employing this LDPC codec exhibits good error performance.

In this paper, we investigate the properties of the point-line incidence matrix of a finite affine plane and present a construction of quasicyclic LDPC codes based on submatrices of the incidence matrix. The codes from the point-line incidence matrices of the affine and projective geometries perform very well with iterative decoding algorithms for low-density parity-check (LDPC) codes.