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We consider in this letter the problem of blind frame synchronization of Low Density Parity-Check (LDPC) codes. We present and compare new methods of blind frame synchronization based on the calculation of Likelihood functions of the syndrome. Simulation results show that the four proposed synchronization techniques are effective once applied to LDPC codes. The method that involves the maximization of the Likelihood Difference (LD) function of the parity-checks, presents the best results in terms of probability of false synchronization.

In non-cooperative communications, blind identification of the widely used LDPC codes is an emerging research hot spot. This is different from and more difficult than blind identification of channel coding in cooperative communications. Common disadvantages of the existing algorithms are poor fault tolerance, high number of iterations, and only being applicable to short codes. Our proposed algorithm is based on the idea presented by Sicot et al. (2009) for binary phase-shift keying (BPSK) signals over the additive white Gaussian noise (AWGN) channel. Firstly, to sort the codewords according to a proper threshold, we present a threshold function and derive its zero point, which is verified to be the optimal threshold through experiments. This threshold improves the fault tolerance of our algorithm. Secondly, an operation called bidirectional Gaussian column elimination (BGCE) is proposed to replace Gaussian column elimination (GCE). This operation speeds up the process of deriving parity-checks, and considerably reduces the number of iterations. Thirdly, we use an existing technique for finding low-weight codewords as proposed by Canteaut and Chabaud (1998) to make the linearly independent parity-checks sparse, thereby realizing reconstruction of the sparse parity-check matrix of the LDPC code. The results of comparative experiments demonstrate that our algorithm outperforms existing algorithms.

In his pioneering work on LDPC codes, Gallager dismissed codes with parity-check matrices of weight two after proving that their minimum Hamming distances grow at most logarithmically with their code lengths. In spite of their poor minimum Hamming distances, it is shown that quasi-cyclic LDPC codes with parity-check matrices of column weight two have good capability to correct phased bursts of erasures which may not be surpassed by using quasi-cyclic LDPC codes with parity-check matrices of column weight three or more. By modifying the parity-check matrices of column weight two and globally coupling them, the erasure correcting capability can be further enhanced. Quasi-cyclic LDPC codes with parity-check matrices of column weight three or more that can correct phased bursts of erasures and perform well over the AWGN channel are also considered. Examples of such codes based on Reed-Solomon and Gabidulin codes are presented.

An efficient compact encoding process with the pipelining design of Low Density Parity Check (LDPC) Encoder with a two stage, three stage and Maximal Rate Pipelining (MRP) structures are proposed in this work. Comparatively, LDPC encoding is more complex than decoding. The complexity mainly referred to the mathematical computation involved in the design of LDPC encoder. There are several methods used to design reduced parity check matrix, one of the methods involved is the Gauss Elimination method. Conventional and wave pipelining techniques are implemented to overcome the disadvantages of the area, latency, etc., The designed architectures are synthesized in SYNOPSYS tool and implemented in the XC3S-250E FPGA device. The overheads like power and area are efficiently reduced by wave pipelining and their efficiency can be proved by synthesis report. This showcases that the LDPC Encoders require less memory by using MRP structure.

In this paper, we propose a good decoding performance, low-complexity, and high-speed decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum-product decoding scheme. To reduce implementation complexity and hardware resource consumption, the messages in the iteration process are uniformly quantified and the function $\Psi (x)$ is approximated with second-order functions. The decoder architecture improves the decoding throughput by using partial parallel and pipeline structures. A modified construction method of parity check matrices was applied to prevent read&write conflicts and achieve high-speed pipeline structure. The simulation results show that our decoder architecture has good performance at signal-to-noise ratios (SNRs) as low as −0.6 dB. We have implemented our decoder architecture on a Virtex-7 XC7VX690T field programmable gate array (FPGA) device. The implementation results show that the FPGA-based LDPC decoder can achieve throughputs of 108.64 Mb/s and 70.32 Mb/s at SNR of 1.0 dB when the code length is 262,144 and 349,952, respectively. The decoder can find useful applications in those scenarios that require very low SNRs and high throughputs, such as the information reconciliation of continuous-variable quantum key distribution.

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

This paper proposes an algorithm to design rate-adaptive irregular LDPC codes with improved Bit error rate (BER) performance. It focuses on achieving better BER results for higher order coding rates which are in high demand for 5G mobile communications. The algorithm generates a parity check matrix based on the message block size. The encoding complexity of the irregular LDPC code is comparatively reduced due to the proposed parity check matrix. Simulation results compare the BER performances of irregular LDPC codes for various code rates and modulation schemes with the Parity check matrix (PCM) generated by the proposed algorithm. The BER performance of improved irregular LDPC code is analyzed in a real-time scenario using Software Defined Radio platform as well.

The manuscript presents the construction of a diagonally structured Parity check matrix using lower and upper (LU) decomposition for regular Quasi Cyclic-Low Density Parity Check Codes (QC-LDPC) with girth 12. This diagonally structured parity check matrix reduces the sparsity characteristics of QC-LDPC codes. The regular Quasi Cyclic-LDPC code has been constructed using circulant shifting and randomization method in which uniform distribution of non-zero elements, XOR operation, and pairing of row and column has been done. A Simplified Log Domain Sum-Product Algorithm (SLDSPA) is used for the decoding of the constructed code. To reduce the CPU run time of the constructed code, a column-wise loop optimization technique is applied. The frame error rate and CPU run time is calculated for different code lengths such as code1 (816, 408), code2 (1008, 504), code3 (1032, 516), code4 (1944, 972), code5 (672, 336) and code6 (504, 252). The construction of regular QC-LDPC codes on half code rate is obtained for the weight of each row is 6 and each column is given by 3. The results showing that the constructed code is better performing in terms of Low FER (10−1 to 10−7), Low SNR (0 to 3.5 dB) and Less CPU run time in milliseconds.

In this letter, sufficient conditions for the determination of the girth are studied from the perspective of matroid theory. The girth of a Tanner graph is at least $2(t_{1}+2)$ if $t_{1}$ specific conditions are simultaneously met. A novel method of constructing high-rate low-density parity-check (LDPC) codes is proposed based on the matroid theory. The parity-check matrices of the constructed LDPC codes are in the form of H = [I $\vert$ H2] with H2 constructed under the conditions of a given girth and a fixed column weight (e.g., $W_{c}=4$ or $W_{c}=6$ ). Simulation results verify that the proposed LDPC codes outperform those in the literature over additive white Gaussian noise channels in terms of bit error rate performance.

Neural Normalized MinSum (N-NMS) decoding delivers better frame error rate (FER) performance on linear block codes than conventional normalized MinSum (NMS) by assigning dynamic multiplicative weights to each check-to-variable message in each iteration. Previous N-NMS efforts have primarily investigated short-length block codes (N < 1000), because the number of N-NMS parameters to be trained is proportional to the number of edges in the parity check matrix and the number of iterations, which imposes am impractical memory requirement when Pytorch or Tensorflow is used for training. This paper provides efficient approaches to training parameters of N-NMS that support N-NMS for longer block lengths. Specifically, this paper introduces a family of neural 2-dimensional normalized (N-2D-NMS) decoders with with various reduced parameter sets and shows how performance varies with the parameter set selected. The N-2D-NMS decoders share weights with respect to check node and/or variable node degree. Simulation results justify this approach, showing that the trained weights of N-NMS have a strong correlation to the check node degree, variable node degree, and iteration number. Further simulation results on the (3096,1032) protograph-based raptor-like (PBRL) code show that N-2D-NMS decoder can achieve the same FER as N-NMS with significantly fewer parameters required. The N-2D-NMS decoder for a (16200,7200) DVBS-2 standard LDPC code shows a lower error floor than belief propagation. Finally, a hybrid decoding structure combining a feedforward structure with a recurrent structure is proposed in this paper. The hybrid structure shows similar decoding performance to full feedforward structure, but requires significantly fewer parameters., This paper has been accepted by ISTC2021

Field-programmable gate array are frequently used to implement high-speed Low-density Parity-check (LDPC) decoders. The conventional practice is to develop a register transfer level (RTL) description of a digital circuit, which requires considerable simulation and verification, resulting in a long development cycle. High-level synthesis (HLS) tools significantly accelerate the hardware design process by using software programming languages such as C/C++. Well optimized code can be synthesized by the HLS tools into efficient hardware circuits. In this paper, we designed a Xilinx FPGA-based LDPC decoder using Vivado HLS. The decoder takes advantage of the cyclic shift of the submatrix in the parity check matrix of the quasi-cyclic LDPC (QC-LDPC) codes and uses a wide-pipeline architecture to process one row/column of all non-zero submatrices per clock cycle, with decoding throughput of hundreds of Mbps. By using different arrays to store data on multiple diagonals in a submatrix can easily avoid the performance bottleneck caused by access conflicts. In addition, the decoder has strong generality and flexibility, which has a high practical value.

This paper presents an enhanced partially-parallel low-density parity-check (LDPC) decoder based on Consultative Committee for Space Data Systems (CCSDS) standard for high speed near Earth applications. Architectural level optimization is exploited to reduce hardware complexity and increase decoding throughput. To enchance the parallelism of the partially-parallel decoder, high circulant weight submatrix of the parity check matrix (PCM) are partitioned into several identity matrices with corresponding cyclic-shifted value and processed separately. Furthermore, messages corresponding to adjacent rows of the cyclic-shifted identity matrix are stored in one memory entry, and low-complexity data aligners are designed between memories and processing units to avoid memory access conflicts. Hardware implementation of a (8176,7154) LDPC code on Xilinx Virtex-5 XC5VLX330 FPGA shows that the proposed decoder can achieve a decoding throughput of 1.02 Gb/s at 10 iterations.

Motivated by applications in unsourced random access, this paper develops a novel scheme for the problem of compressed sensing of binary signals. In this problem, the goal is to design a sensing matrix $A$ and a recovery algorithm, such that the sparse binary vector $\mathbf{x}$ can be recovered reliably from the measurements $\mathbf{y}=A\mathbf{x}+\sigma\mathbf{z}$, where $\mathbf{z}$ is additive white Gaussian noise. We propose to design $A$ as a parity check matrix of a low-density parity-check code (LDPC), and to recover $\mathbf{x}$ from the measurements $\mathbf{y}$ using a Markov chain Monte Carlo algorithm, which runs relatively fast due to the sparse structure of $A$. The performance of our scheme is comparable to state-of-the-art schemes, which use dense sensing matrices, while enjoying the advantages of using a sparse sensing matrix., Comment: Accepted to Entropy Special Issue on "Information-Theoretic Aspects of Non-Orthogonal and Massive Access for Future Wireless Networks"

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

Aiming at the problem that quasi-cyclic low density parity check (QC-LDPC) codes may have the error floor in the high signal to noise ratio (SNR) region, a new construction method of the QC-LDPC codes with the low error floor is proposed. The basic matrix of the method is based on the progressive edge growth (PEG) algorithm and the improved eliminate elementary trapping sets (EETS) algorithm so as to eliminate the elementary trapping sets in the basic matrix, then the Zig-Zag method is used to construct the cyclic shift matrix which is used to extend the basic matrix in order to construct the parity check matrix. The method not only can improve the error floor in the high SNR region, but also can flexibly design the code length and code rate. The simulation results show that at the bit error rate of 10−6, the PEG-trapping-Zig-Zag (PTZZ)-QC-LDPC(3024,1512) codes with the code rate of 0.5, compared with the PEG-Zig-Zag (PZZ)-QC-LDPC(3024,1512) codes and the PEG-QC-LDPC(3024,1512) codes, can respectively improve the net coding gain of 0.1 dB and 0.16 dB. The difference among the bit error rate performance curves will become better with the increase of the SNR. In addition, the PTZZ-QC-LDPC(3024,1512) codes have no error floor above the SNR of 2.2 dB.

This paper considers the problem of source coding with side information at the decoder, also called Slepian-Wolf source coding scheme. In practical applications of this coding scheme, the statistical relation between the source and the side information can vary from one data transmission to another, and there is a need to adapt the coding rate depending on the current statistical relation. In this paper, we propose a novel rate-adaptive code construction based on LDPC codes for the Slepian-Wolf source coding scheme. The proposed code design method allows to optimize the code degree distributions at all the considered rates, while minimizing the amount of short cycles in the parity check matrices at all rates. Simulation results show that the proposed method greatly reduces the source coding rate compared to the standard LDPCA solution., Comment: 25 pages, 7 figures, submitted to IEEE Transactions on Communications

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient decoder implementation and flexible decoding flow control. Moreover, a two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 4.32 Gb/s with the chip area 3.376 mm2.

An algorithm for constructing parity-check matrices of non-binary quasi-cyclic low-density parity-check (NB QC-LDPC) codes is proposed. The algorithm finds short cycles in the base matrix and tries to eliminate them by selecting the circulants and the elements of GF(q). The algorithm tries to eliminate the cycles with the smallest number edges going outside the cycle. The efficiency of the algorithm is demonstrated by means of simulations. In order to explain the simulation results we also derive upper bounds on the minimum distance of NB QC-LDPC codes.

This paper presents a novel regular Quasi-Cyclic (QC) Low Density Parity Check (LDPC) codes with column-weight three and girth at least eight. These are designed on the basis of combinatorial design in which subsets applied for the construction of circulant matrices are determined by a particular subset. Considering the non-existence of cycles four and six in the structure of the parity check matrix, a bound for their minimum weight is proposed. The simulations conducted confirm that without applying a masking technique, the newly implemented codes have a performance similar to or better than other well-known codes. This is evident in the waterfall region, while their error floor at very low Bit Error Rate (BER) is expected. Keywords: Quasi-cyclic LDPC codes, Combinatorial design, Minimum weight, Girth

Day by day the internet traffic is increasing rapidly. Challenges to improve these internet traffic requirements leads to evolution of 5G NR LDPC (New Radio Low Density Parity Check) codes which provides high coding gain and energy efficiency. BER Vs Eb/No dB curve defines the energy efficiency and coding gain of the any error correcting codes. LDPC codes which are adopted by 5G Standard are called 5G NR LDPC codes.In the design of the decoder,Message Passing Approach reduces the decoding complexiyt due to the sparsity of the parity check matrix.. An efficient decoding algorithm is the key to the successful code. In this paper an iterative minsum approximation message passing decoding algorithm has been implemented for both BG1 and BG2. Results show that the coding gain can be improved up to 9dB.

The paper proposes hardware implementation of the LDPC decoder (Low Density Parity Check) as a serial architecture in the FPGA structure. The implemented decoder has 4-bit Log-Likelyhood Ratio messages precision and is dedicated for regular (3,6) code with 512 x 1024 parity check matrix. In order to reduce the complexity, the proposed decoder uses Min-Sum algorithm for check nodes (CNUs). In this article we present Bit Error Rate results that prove correctness of the decoder operation implemented in the Intel Cyclone IV. We also estimate power consumption of this implementation.

The Low Density Parity Check (LDPC) codes are linear block codes, which are Shannon Limit codes. These codes are attained least error floors of data bits for data transfer applications used in communication systems. However, the proposed LDPC codes are more beneficial than Turbo codes because of reduction in the decoding complexity and detection of the errors in less cycle time. This results the reduction of decoding time, low decoding latency and as well as least error floors in communication, when the transmitted data contains multiple error bits. This paper is proposed to represent the majority logic decoding/detecting of LDPC codes. This paper proposes the Generation of Generator and Parity Check matrices for both Binary and Non-Binary LDPC Codes. Here, the proposed Majority Logic Decoder/Detector (MLDD) is Hard decision decrypting scheme and it uses majority logic decoding based on the data transmission and reception in communication channel. This paper also elaborates the effective implementation of encoding and decoding of LDPC Codes.

Implementation of Low Density Parity Check (LDPC) decoders using conventional algorithms such as LLR BP or Min-Sum requires large amount of memory resources for storing the parity check matrix. This paper presents a soft implementation of irregular LDPC decoding for Wimax application, which achieve better BER performance and faster convergence with less memory requirement. The proposed construction reduce the memory required for loading the LDPC parity-check matrix by up to 98%, and subsequently reduce the decoding latency to 0.7 ms by iteration.

В даній роботі проаналізовано матриці перевірки на парність, які можуть бути використані в методі виправлення помилок на основі low density parity check (LDPC) матриць в системах квантового розподілу ключів. Система квантового розподілу ключів має неминучі помилки в просіяному ключі, які повинні бути виправлені алгоритмом виправлення помилок для створення захищеного ключа. У цьому аналізі 1000-бітні просіяні ключі розділяються на 50 частин, по 20 біт в кожній частині. Алгоритм створює 50 синдромів, по 10 біт в синдромі, що відповідають кожній частині, за допомогою перемноження матриць перевірки на парність розміром 10 × 20. Матриці перевірки на парність створюються алгоритмом, запропонованим Девідом Маккеєм та Редфордом Нілом. Процес створення синдрому складається з матричного перемноження 20-бітної частини просіяного ключа на матрицю перевірки на парність. Алгоритм посилає сформований синдром другій стороні. Під час передачі підслуховувач може перехопити синдром, але він не може дізнатись точне повідомлення з синдрому, навіть якщо він володіє матрицею перевірки на парність теж. Друга сторона також ділить її просіяний ключ на 50 частин, створює синдром з кожної частини і порівнює з отриманим синдромом. Якщо синдроми різні, ці частини просіяних ключів відкидають. Однак, через те, що довжина повідомлень складає 20 біт, а довжина синдромів 10 біт, можуть виникати ситуації, коли різні частини просіяного ключа матимуть однакові синдроми. Для даного випадку кожні 1024 повідомлень будуть мати один спільний синдром. Тому необхідно знайти таку оптимальну матрицю, яка знімає ймовірність отримання однакових синдромів від різних частин просіяного ключа. In this paper, the parity-check matrices that can be used in low density parity check (LDPC) based error correction method for quantum key distribution are analyzed. The quantum key distribution system has inevitable errors in sifted key that must be corrected by an error correction algorithm to create a secure key. In this analysis, 1000-bit sifted keys are divided into 50 parts. The algorithm creates 50 syndromes corresponding to each part by multiplying 10 × 20 bit parity-check matrices. The algorithm sends the generated syndrome to the other side, which also divides the sifted key into 50 parts, creates a syndrome from each part, and compares with the received syndrome. If the syndromes are different, these sifted key parts are discarded. However, there may be situations where different parts may have the same syndromes. Therefore, it is necessary to find such an optimal matrix that removes the probability of getting the same syndromes at different parts of the sifted key.

The paper presents the results of developing a decoder architecture of low-density parity check code of the DVB-S2 standard for field programmable gate array. It supports several code rates and codeword lengths described in the appendix of the standard. The proposed decoder architecture has a partially parallel structure, which allows to achieve high decoding performance and efficient use of chip area. The presence of double-diagonal submatrices in the structure of the parity check matrices was also confirmed, and a method for eliminating them was implemented. In the work, an analysis of parameters affecting the static and dynamic power consumption in the field programmable gate array was made. Based on it, algorithmic and architectural methods for reducing consumption are proposed. The paper describes the developed architectures and methods to reduce chip power consumption.

This paper proposes the use of systematic LDPC codes for hard decision Message Passing (hMP), which is a predecoder to Vector Symbol Decoding (VSD) for non-binary codes. VSD is a verification-based decoder whose outputs are decoded code words. LDPC are randomly generated and by nature, they are non-systematic codes. Using systematic instead of non-systematic codes allows the decoder to obtain the decoded data directly without a troublesome mapping step. In the simulations, 15 regular parity check matrices H are randomly generated and converted to their systematic forms. Results in a Gilbert-Elliot 2-state fading channel model with 6 different channel conditions show that hMP prefers codes with lower- weight H. For column weight of 9 bits and row weight of 18 bits, systematic H have lower weight after row operation and are better than the non-systematic ones for all channel conditions.

The communication method conveys information from the transmitter to the receiver over an intermediate medium. The competence of received information is determined by medium and clatter. There is a great need for robust error correction techniques with ever accumulative usage of wireless expedients such as portable electronic items and broadband modems. Wireless communication schemes depend on advanced error rectification techniques for their suitable functioning. Hence transferring and getting information with less or without error, while utilizing the accessible bandwidth is a foremost proposal, project necessities for present digital wireless communication systems comprising of high throughput, low power consumption, and less area. In this article, the functional analysis is performed for error control coding technique i.e., Low-Density-Parity-Check (LDPC) coding in terms of device utilization and power. The functional verification and the simulation are performed using Verilog HDL. Error correction techniques such as Linear block codes, RS codes, Convolutional codes are employed to implement forward error correction but as the constraint length increases the design of decoders becomes more complex. LDPC is a type of block code that is capable of correcting random errors. They are popular because of their eminent detection and correction capabilities. LDPC encoding technique provides high throughput and aims to improve BER when compared to conventional techniques. The decoding of LDPC codeword employs the Message Passing Algorithm, where each bit in a codeword is allocated to special nodes. The performance of these codes is hence better and easily attains Shannon’s limit than the previously used codes. Synthesis for the technique is performed and utilization reports are derived from the synthesis in Vivado.

Error correction is a significant step in postprocessing of continuous-variable quantum key distribution system, which is used to make two distant legitimate parties share identical corrected keys. We propose an experiment demonstration of high speed error correction with multi-edge type low-density parity check (MET-LDPC) codes based on graphic processing unit (GPU). GPU supports to calculate the messages of MET-LDPC codes simultaneously and decode multiple codewords in parallel. We optimize the memory structure of parity check matrix and the belief propagation decoding algorithm to reduce computational complexity. Our results show that GPU-based decoding algorithm greatly improves the error correction speed. For the three typical code rate, i.e., 0.1, 0.05 and 0.02, when the block length is $10^6$ and the iteration number are 100, 150 and 200, the average error correction speed can be respectively achieved to 30.39Mbits/s (over three times faster than previous demonstrations), 21.23Mbits/s and 16.41Mbits/s with 64 codewords decoding in parallel, which supports high-speed real-time continuous-variable quantum key distribution system., 8 pages, 2 figures

This paper presents a novel linear error detection and correction approach for single and multiple bit error codes called low complexity parity check (LCPC) code. The LCPC code detects and corrects consecutive and non-consecutive bit errors. It can be used as a forward error correction scheme in the data transmission system of green wireless networks and the green Internet of Things. The proposed code improves network performance in terms of throughput, end-to-end delay, and bit error rate (BER). LCPC codes also have less complexity and lower memory requirements than Reed Solomon (RS) and low-density parity check (LDPC) codes because they have less non-zero elements in the generator matrix and the parity check matrix. Unlike LDPC codes, LCPC codes do not require reiteration in the decoding process. Various code rates of the LCPC code are proposed to reduce the complexity of the encoding and decoding process, which in turn decreases energy consumption. Simulation results show that the proposed LCPC (9, 4) code outperforms the popular LDPC codes. Compared with the LDPC (8, 4) with the decode bit flip algorithm, LCPC (9, 4) offers a coding gain of nearly 3 dB at a BER equal to 10−5.

Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair “remedies” cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC’s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes—(585,512) and (683,512)—augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 10 2 (10 4 ) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.

In this paper, we propose a generalized minimum-sum decoding algorithm using a linear approximation (LAMS) for protograph-based low-density parity-check (PB-LDPC) codes with quasi-cyclic (QC) structures. The linear approximation introduces some factors in each decoding iteration, which linearly adjust the check node updating and channel output. These factors are optimized iteratively using machine learning, where the optimization can be efficiently solved by a small and shallow neural network with training data produced by the LAMS decoder. The neural network is built according to the parity check matrix of a PB-LDPC code with a QC structure which can greatly reduce the size of the neural network. Since, we optimize the factors once per decoding iteration, the optimization is not limited by the number of the iterations. Then, we give the optimized results of the factors in the LAMS decoder and perform decoding simulations for PB-LDPC codes in fifth generation mobile networks (5G). In the simulations, the LAMS algorithm shows noticeable improvement over the normalized and the offset minimum-sum algorithms and even better performance than the belief propagation algorithm in some high signal-to-noise ratio regions.

In this paper, we design an irregular low-density parity-check (LDPC) codes for unequal inter-symbol interference channels based on the modified extrinsic information transfer chart. During transmission, each LDPC codeword will be divided and transmitted to the different channels. The aim of this scheme is to avoid transmitting the whole codeword in a high error rate channel. The simulation results show that the proposed code optimized for both PR1 and PR2 channels can achieve a 0.2 coding gain over the codes designed specifically for each individual channel. When this simple code is applied to a perpendicular channel with these two targets, the coding gains of the proposed code is about 0.08 dB at the frame error rate of $10^{-3}$ .

In view of the problems that the encoding complexity of quasi-cyclic low-density parity-check (QC-LDPC) codes is high and the minimum distance is not large enough which leads to the degradation of the error-correction performance, the new irregular type-II QC-LDPC codes based on perfect cyclic difference sets (CDSs) are constructed. The parity check matrices of these type-II QC-LDPC codes consist of the zero matrices with weight of 0, the circulant permutation matrices (CPMs) with weight of 1 and the circulant matrices with weight of 2 (W2CMs). The introduction of W2CMs in parity check matrices makes it possible to achieve the larger minimum distance which can improve the error- correction performance of the codes. The Tanner graphs of these codes have no girth-4, thus they have the excellent decoding convergence characteristics. In addition, because the parity check matrices have the quasi-dual diagonal structure, the fast encoding algorithm can reduce the encoding complexity effectively. Simulation results show that the new type-II QC-LDPC codes can achieve a more excellent error-correction performance and have no error floor phenomenon over the additive white Gaussian noise (AWGN) channel with sum-product algorithm (SPA) iterative decoding.

The LDPC codes are Shannon Limit codes that can achieve low bit error rates for SNR applications. The features of LDPC Codes are reduction in the decoding time, latency and as well as no error-floors at high SNRs. The proposed algorithms are SBF, MSA, and MLDD. The various decoding algorithms have been compared for these codes. The parameters are describing the which algorithm further helps in selecting the better decoder used for Medical and Signal Processing Applications. These codes are also used in Generating the Barcodes depends on the size of the Parity Check matrix.

An improved extension method based on protograph extrinsic information transfer (PEXIT) charts is proposed to design rate-compatible quasi-cyclic low-density parity-check (QC-LDPC) codes with more flexible rates and better performance. The masking matrix of the highest-rate code can first be constructed column by column to own the lowest decoding threshold. Then, an extension algorithm is proposed to obtain the masking matrices of lower-rate codes with flexible rates. Finally, the base matrices with small amount of short cycles are designed and the parity-check matrices of rate-compatible QC-LDPC codes are obtained through matrix extension. Simulations show that compared with the existing codes, the proposed codes have more flexible rates while achieving better performance.

In this paper, new spectral optical codes based on the construction parity check matrix of LDPC codes were designed and implemented in an optical code-division multiple access communication system. Two types optical family codes can be obtained with respectively a cross correlation of λ c = 0 {\lambda _c} = 0 and λ c = 1 {\lambda _c} = 1 . In each case, the codes can either be decoded using the direct detection or the balanced detection. Performance was evaluated by referring to the Q factor, the bit error rate and the eye pattern diagrams using Optisystem 9.0.

LDPC is being enormously used these days in number of communication applications for its reliably and resourcefulness over a certain channel. LDPC decoding “Sum-Product Algorithm and Minimum Sum Algorithm” are implemented and compared in this paper. The parity check matrix used is unique in its construction; sparse method is used to generate the matrix. The decoder is simulated in MATLAB. Performance and effectiveness of algorithms is verified under the presence of noise.

As a recently proposed physical layer security scheme, the two-dimensional transmission scheme prevents eavesdropping, but the bit error rate (BER) of the receiver becomes high. A new coding scheme for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes to improve the performance of the receiver is proposed and named as dimension reduction coding. This new scheme constructs the base matrix, which is necessary to obtain the parity check matrix of QC-LDPC codes, from the channel coefficient matrix of two-dimensional transmission scheme. Then, by analyzing the relationship between the base matrix and the parity check matrix of QC-LDPC codes, we find out the conditions that the base matrix must satisfy so that the corresponding parity check matrix has no shortest cycle in Tanner graph. Furthermore, a dimension reduction algorithm is presented to modify the base matrix and obtain parity check matrices with good performance. Finally, simulation results are given and validate the feasibility of this method.

This paper presents a novel efficient encoding method and a high-throughput low-complexity encoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes for the 5th-generation (5G) New Radio (NR) standard. By storing the quantized value of the permutation information for each submatrix instead of the whole parity check matrix, the required memory storage size is considerably reduced. In addition, sharing techniques are employed to reduce the hardware complexity. The encoding complexity of the proposed method was analyzed, and indicated a substantial reduction in the required area as well as memory storage when compared with existing state-of-the-art encoding approaches. The proposed method requires only 61% gate area, and 11% ROM storage when compared with a similar LDPC encoder using the Richardson&ndash, Urbanke method. Synthesis results on TSMC 65-nm complementary metal-oxide semiconductor (CMOS) technology with different submatrix sizes were carried out, which confirmed that the design methodology is flexible and can be adapted for multiple submatrix sizes. For all the considered submatrix sizes, the throughput ranged from 22.1&ndash, 202.4 Gbps, which sufficiently meets the throughput requirement for the 5G NR standard.

Non-binary low-density parity-check (NB-LDPC) codes exhibit a much better performance than their binary counterparts, especially for moderate codeword length and high-order modulation. However, their decoding algorithms suffer from very high computational complexity. In this paper, a low-complexity algorithm is proposed, named parity-check erased algorithm (PCEA), where an additional parity check bit is added to each symbol of the codeword when encoding and a series of simple operations are performed based on these bits during decoding. As a universal joint coding and decoding algorithm, the PCEA can be combined with arbitrary NB-LDPC encoding schemes and decoding algorithms based on message passing. The proposed algorithm facilitates significant improvement of decoding performance with a small decrease of the code rate. Additionally, it usually has an even better performance than a nearly same-rate code constructed by the original method, and requires much lower decoding complexity due to smaller size of the parity check matrix.

This paper presents a novel method for constructing high performance unequal error protection (UEP) quasicyclic low-density parity-check (QC-LDPC) codes. These codes are highly efficient and designed with flexible rates, lengths and number of protection levels. The given QC-LDPC codes are based on the combinatorial design. Each circulant constituting the parity check matrix of the UEP code is determined from subsets with the distinct difference between elements. Simulation results indicate that proposed UEP codes have equivalent performance to UEP codes constructed with the higher girth and lower rate, while achieving superior performance than the codes constructed by conventional equal error protection (EEP) techniques.

Low density parity check (LDPC) codes are forward error-correction codes, invented by Robert Gallager in his MIT Ph.D. dissertation, 1960. The LDPC codes are ignored for long time due to their high computational complexity and domination of highly structured algebraic block and convolutional codes for forward error correction. A number of researchers produced new irregular LDPC codes which are known as new generalizations of Gallager’s LDPC codes that outperform the best turbo codes with certain practical advantages. LDPC codes have already been adopted in satellite-based digital video broadcasting and long-haul optical communication standards. This chapter discusses LDPC code properties, construction of parity check matrix for regular and irregular LDPC codes, efficient encoding and decoding of LDPC codes, and performance analysis of LDPC codes.