Search

In this study, hysteresis-free double-layer gate-all-around stacked poly-Si nanosheet channel ferroelectric HfxZr1-xO2 negative capacitance field-effect transistors (DL GAA NS FE-HZO NC-FETs) with an internal metal gate (IMG) and NH3 plasma nitridation were experimentally investigated and comprehensively discussed for the first time. The results revealed that NH3 plasma nitridation at both the ZrO2/TiN and TiN/HZO interfaces can effectively enhance the HZO ferroelectricity and quality by suppressing the generation of oxygen vacancies (${V}_{o}{)}$. Furthermore, the SiON interfacial layer quality can be enhanced by passivating bulk defects within the SiON interfacial layer through NH3 plasma nitridation at the ZrO2/TiN interface. When NH3 plasma nitridation is performed at both the ZrO2/TiN and TiN/HZO interfaces, the devices exhibit excellent electrical characteristics: 1) an extremely low subthreshold swing (SS) of 45.77 mV/decade; 2) an ultrasteep average SS (ASS) of 61.39 mV/decade; 3) a relatively high ON/OFF current ratio (${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}{)}$ of $ > 5\,\,\times \,\,10^{{7}}$ ; and 4) a quite high effective breakdown voltage (${V}_{\text {EBD}}$) of 6.7 V at ${V}_{D}$ = 0.1 V. Thus, these devices are promising candidates for low-power-consumption monolithic 3-D integrated circuit (IC) applications. [ABSTRACT FROM AUTHOR]

We demonstrated that channel mobility and cell current could be increased through Ge diffusion engineering and H2 plasma treatment in a poly-Si channel. Even though the Ge channel has a higher intrinsic mobility than the Si channel, a typical poly-SiGe channel has inferior channel characteristics due to high interface trap density (Dit) and bulk trap density caused by Ge. We propose a novel technique to control the Ge profile along the depth direction of the channel to realize lower Ge concentration at the gate dielectric interface and higher Ge concentration at the channel bulk. This Ge profile could achieve reduced Dit and enhanced channel mobility. Furthermore, the bulk traps caused by Ge are effectively reduced by H2 plasma treatment. These techniques increased the channel mobility to 32%, which can help increase the channel mobility of devices where poly-Si channels are used. [ABSTRACT FROM AUTHOR]

One-time programmable (OTP) memory is essential to the security and gaming industries because of its “write once, read many” capability. This device supports N-metal–oxide–semiconductor polycrystalline-silicon junctionless gate-all-around (GAA) nanowire transistor technology and can perform multistate antifuse. It is capable of functioning in four states instead of in the standard two states (open/short). Furthermore, the states can be read as fully open (0, 0), drain–gate breakdown (0, 1), source–gate breakdown (1, 0), and full breakdown (1, 1) states. The antifuse is formed from the oxide breakdown between the gate and the source or drain (S/D). Moreover, because multiple samples have been successfully produced, its information can be displayed as a chart or table to instantly convey information about the current device’s state to programmers by reading the S/D current. [ABSTRACT FROM AUTHOR]

In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration (Nch,eff). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage (VTH) increases as the Nch,eff of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower Nch,eff show the more severe rate of deterioration in the transconductance (Gm) and ON current (ION). By increasing Nch,eff to reduce the electric field (E-field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage (VGOD = VG – VTH = −3.5 V) to perform the NGBS test. [ABSTRACT FROM AUTHOR]

In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (TSi) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications. [ABSTRACT FROM AUTHOR]

For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of $5.3\times9$ nm2 and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable Ion–Ioff ratio of more than 108. We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage (${V}_{\textit {TH}}$) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub- ${V}_{\textit {TH}}$ slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under the Hf $_{{1-}{x}}$ ZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase (${o}$ -phase) before further post-metal annealing (PMA). [ABSTRACT FROM AUTHOR]

A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped ${n}^{+}$ source and drain junctions, nearly intrinsic ${n}^{-}$ channel, 500-nm gate length (${L}_{{{\mathrm {G}}}}$), and 50-nm poly-Si body thickness (${T}_{{{\mathrm {body}}}}$). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of $3.2~{\mu }\text{A}/{\mu }\text{m}$ and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems. [ABSTRACT FROM AUTHOR]

In this letter, stacked sidewall-damascene double-layer poly-silicon trigate field effect transistors (FETs) with and without rapid thermal annealing (RTA) are successfully demonstrated using a simple fabrication method. Devices with RTA exhibit superior electrical characteristics to those without RTA owing to better crystallinity. The better crystallinity of the device with RTA results from a larger grain size and fewer defects, leading to higher field-effect mobility \mu \text {FE} compared with devices without RTA. p-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA show excellent electrical characteristics, including an extremely low drain-induced barrier lowering (DIBL) of 7 mV/V, a steep subthreshold swing of 136 mV/decade, and high \textI \mathrm{\scriptscriptstyle ON}/\text I \mathrm{\scriptscriptstyle OFF} current ratio of 1.1\times 10^7 . The fabricated n-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA showed a low DIBL, subthreshold swing and an \textI \mathrm{\scriptscriptstyle ON}/\textI \mathrm{\scriptscriptstyle OFF} current ratio larger than seven orders of magnitude. Their simple fabrication method makes them a promising candidate for future monolithic 3D integrated-circuit applications. [ABSTRACT FROM AUTHOR]

In this brief, a negative bias stress (NBS) induced degradation in n-type multigate polycrystalline silicon (poly-Si) thin-film transistor (TFT) is investigated. It is observed that after NBS the transfer characteristic curves shift to the negative gate bias direction and multigate TFTs degrade more than the single-gate TFTs with the same effective channel length. The observed degradation phenomenon is explained with short channel effect that is resulted from the diffusion and distribution of hole carriers in the channel, which are generated in the source/drain depletion region and swept into the channel when the junctions are reversely biased during NBS. Pronounced NBS degradation caused by increased hole carriers in the channel is also verified in NBS experiment with light illumination. [ABSTRACT FROM PUBLISHER]

We have succeeded in developing a hybrid-type temperature sensor using poly-Si thin-film transistors (TFTs) that outputs rectangle waveforms. An advantage of the conventional hybrid-type sensor is that large temperature dependences of off-leakage currents can be utilized, and it simultaneously works in a digital operation tolerant of noises. Additionally, in this paper, by connecting two conventional ones, the sensor becomes able to output rectangle waveforms, which can be easily counted. We confirm the waveform and that the sensor can detect the correct temperature. We think that it is promising to integrate this temperature sensor in some applications using TFTs. [ABSTRACT FROM PUBLISHER]

In this paper, the electrical characteristics of the Pi-gate junctionless FETs (PG JL FETs) with the in situ n+ doped poly-Si (DP-Si) fin-channels have been experimentally investigated and comprehensively discussed. The subthreshold behavior and threshold voltage of the PG JL FETs are sensitive to the channel dimensions, especially the channel width. The crystallinity, carrier mobility, and effective carrier concentration in the DP-Si films are dependent on the initial DP-Si film thicknesses, which directly influence the on current and threshold voltage of the PG JL FETs. Based on an evaluation on the subthreshold behavior and the driving current, we found that the PG JL FETs with the low/high aspect ratio (A.R. = channel thickness/channel width) are separately suitable for the low-power/high-performance applications. Among these PG JL FETs, the device with a proper A.R. (3.35) exhibits a relatively steep subthreshold swing (S.S.) of 66 mV/decade and the highest ON/OFF currents ratio ( I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF}) of $1.2\times 10^{{8}}$ ( {V}_{D} = {1} V). These devices are very promising candidates for future multifunctional 3-D integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this paper, we investigate Low Pressure Chemical Vapor Deposition (LPCVD) SiN as a gate isolation material for AlGaN/gallium nitride (GaN) MIS-high electron mobility transistor power transistors. We compared the dielectric failure by forward-biased constant-current stress time-dependent dielectric breakdown measurements and statistical Weibull analysis. Several 4” AlGaN/GaN-on-Si wafers have been processed with different gate isolations and processes. Our investigation includes the dependence of the dielectric breakdown on the process flow (influence of dry etch), the thickness of the dielectric (12–20 nm), the area scaling, and the gate electrode, where we also consider the recently presented poly-silicon electrode. Additionally, we show the influence of the current density through the gate on the charge-to-breakdown characteristics as well as the influence of the temperature on the breakdown behavior. Using the poly-silicon electrode and 20 nm LPCVD SiN as gate isolation, we achieved a charge-to-breakdown of Q\text {BD, 10~\text {mA}/\text {cm}^{2}} ={3.7} ~ \text {kC}/\text {cm}^{{2}} at \text T = 130 ^\circ \text C for j = 10 ~ \text mA/\text cm^2 . A 20-years lifetime (100 ppm, \text T = 130 ^\circ \text C ) extrapolation for a scaled area of 0.2 ~ \text mm^2 ( \buildrel \wedge \over = WG = {100} ~ \text {mm} ) leads to a positive gate voltage of V\text {G} = {9.4} ~ \text V . [ABSTRACT FROM PUBLISHER]

Epitaxial InxGa1–xAs is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate InxGa1–xAs are thoroughly discussed; their impact on the electrical performances are investigated and the tunnel oxide (TuOx) quality is assessed. InxGa1–xAs channels with a diameter down to ~45 nm and different In concentrations are obtained after using two alternative surface preparation routes: HCl and Cl2. Thanks to the lower thermal budget involved, Cl2 seems the most suitable route to preserve the thickness of the TuOx. InxGa1–xAs channels with In concentration, x, higher than 0.45 have superior conduction properties compared with poly-Si channel, showing higher I\mathrm { {on}} and transconductance. [ABSTRACT FROM AUTHOR]

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ~ 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si3N4) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG poly-Si JL FETs show excellent electrical performance in terms of low gate overdrive voltage ( VG – V\mathrm{ TH} = 2 V), extremely near-ideal subthreshold swing (S.S.) ~68 mV/decade, steep average subthreshold swing (A.S.S.) ~ 73 mV/decade, smaller drain-induced barrier lowering ~9 mV/V, a higher ON/OFF current ratio \sim 1.1 \times 10^8 ( \textV\mathbf {D} = 1 V), and a better field-effect mobility ( \mu \mathrm{ FE}) \sim 35 (cm2/Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications. [ABSTRACT FROM AUTHOR]

We report high performance p-type poly-Si thin-film transistors (TFTs) achieved by lateral grain growth of amorphous silicon (a-Si) by using a continuous-wave blue diode laser of wavelength 445 nm. The blue laser beam is efficiently absorbed into the a-Si film, such that full melting and lateral crystallization is achieved in all thicknesses investigated, 50–200 nm. TFTs fabricated with 75-, 100-, and 125-nm-thick poly-Si films laterally grown by the blue laser annealing exhibited field-effect mobility of 108 ± 7, 104 ± 9, and 134 ± 12 cm2/ \textrm V\cdot \textrm s , and subthreshold swing of 210±51, 191±16, and 193±53 mV/decade, respectively, and high ON/OFF current ratio of \sim 10^8 . [ABSTRACT FROM PUBLISHER]

In this paper, we report the development of a high- k /metal gate stacking process to reduce the effective gate resistance, and circuit level validation results in 28-nm gate first integrated high- k /metal gate CMOS devices. To achieve this, millisecond annealing was adopted and the silicon (Si) gate and TiN gate electrode thicknesses were controlled. The recrystallized poly-Si gate by millisecond annealing improved the performance of the ring oscillator (RO) by 15% and the minimum operating voltage ( V\min ) of the high-frequency test pattern (HFTP) by 34 mV. The poly-Si gate improved the uniformity of the boron concentration and suppressed localized low doping area at the bottom of the gate. When the Si gate thickness was reduced by 10 Å with respect to the reference (POR) value, the performance of the RO improved by 5% and V\min of HFTP improved by 20 mV due to the shorter boron diffusion distance. A 10- Å thicker TiN gate electrode improved V\min of HFTP by 30 mV, since the thicker TiN reduced the TiN/Si gate interface resistance. [ABSTRACT FROM AUTHOR]

Two-stage degradation of p-type polycrystalline silicon thin-film transistors under dynamic positive bias temperature (PBT) stress is reported for the first time. ON-state current ( \(I_\mathrm{{\scriptstyle ON}}\) ) gradually increases in the first degradation stage while dramatically drops in the second degradation stage, which are, respectively, due to the channel length shortening effect, caused by electrons trapping into the gate oxide, and grain boundary potential barrier buildup, caused by dynamic hot-carrier-induced traps generation. The transition from the first to the second degradation stage is clarified, in which the pulse peak duration plays a key role. Longer pulse peak duration is preferred to suppress the dynamic PBT stress-induced degradation. [ABSTRACT FROM AUTHOR]

A physical-based analytical series resistance (Rs) model is first proposed to accurately evaluate the Rs of polycrystalline silicon thin-film transistors (TFTs). Through carefully analyzing the gate-to-source/drain overlap regions, three underlying physical effects wherein are adequately included, namely the gate (Vg)-induced carrier accumulation, current path spreading, and carrier transport via thermionic emission over grain boundaries. The proposed model can precisely reproduce the Vg dependent Rs behavior and fit the experimental data of both metal-induced lateral crystallized and excimer laser annealed TFTs. Furthermore, an explicit analytical expression of Rs is derived using appropriate approximation, based on which all underlying Rs components and their dependencies on device parameters can be clarified. Finally, feasible approaches of Rs reduction are suggested. [ABSTRACT FROM AUTHOR]

N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C– V characterization, the ionized dopant concentration in the channel is determined to be around \2 \times \10^19 \ \cm^-3 and the fixed charge density to be around -6 \times \10^12 \ \cm^-2. The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding. [ABSTRACT FROM AUTHOR]

We have analyzed the device behavior of a poly-Si thin-film transistor (TFT) with a lightly doped drain (LDD) structure using 2-D device simulation. It is found that the reason that the on current does not fall very much is that the electron channel oozes from the channel region to the LDD region and the electric current paths spread to the entire LDD region. On the other hand, the reason that the off current is effectively reduced is undoubtedly that the electric field at the interface between the channel and LDD regions is weakened. However, it should be noted that the depletion region is formed at the drain edge owing to the “pseudo” space-charge region in the channel region, where the carrier density is much lower than in the other channel region, although the net space-charge does not exist. [ABSTRACT FROM AUTHOR]

This paper investigates the read operation of poly-Si nanowire silicon–oxide–nitride–oxide–silicon devices with independent double-gate (IDG) configuration. The device features oxide–nitride–oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed. [ABSTRACT FROM PUBLISHER]

Positive-bias temperature-stress-induced degradation in p-channel poly-Si thin-film transistors is investigated. Two-stage degradation behavior is observed. In the first-stage degradation, on-state current (ION) initially increases associated with a positive threshold voltage (V \rm th) shift and is then followed by a gradual ION decrease. In the second stage, Vth shifts to the negative, and ION significantly degrades. A comprehensive physical model is proposed to clarify the two-stage degradation behavior. The first-stage degradation is attributed to electron trapping and detrapping, whereas the second-stage degradation is dominated by positive charge generation. [ABSTRACT FROM AUTHOR]

Trap-layer-engineered poly-Si nanowire silicon–oxide–nitride–oxide–silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxide/nitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer. [ABSTRACT FROM AUTHOR]

In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, \Omega -shaped gated \OmegaG, and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largest memory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications. [ABSTRACT FROM PUBLISHER]

Operation characteristics in a polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory device are studied with SiGe buried channel for the first time. Compared with the flash device with a general poly-Si NW channel, the device with SiGe buried channel shows improved programming and erasing speeds since the enhanced electric field in tunneling layer is enhanced by SiGe buried layer. The endurance characteristics are also improved by the SiGe buried channel while retention performances are retained. The SiGe buried channel is promising to CT flash device for 3D nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

We have evaluated the effects of thermal annealing before formation of gate insulator films (preannealing) and thermal annealing after formation of gate insulator films (postannealing) by extracting trap densities for solid-phase crystallized poly-Si thin-film transistors. It is suggested that the preannealing densifies the poly-Si films and induces additional internal stress after the thermal oxidation of the gate insulator films. On the other hand, the postannealing also relieves the internal stress. These conflicting effects indicate that the order of the thermal annealing is very important to improve device performance. [ABSTRACT FROM AUTHOR]

In this letter, for the first time, we experimentally investigate the radio-frequency (RF) characteristics and low-frequency noise (LFN) of n-type planar junctionless (JL) poly-Si thin-film transistors (TFTs). The fabricated JL devices show remarkable dc performance with good current drive and a high on-current/off-current ratio of \8 \times \10^7. Furthermore, with the implementation of an in situ phosphorus-doped channel architecture and a salicide process, the JL device with a channel length of 0.4 \mu\m exhibits a cutoff frequency (ft) of 3.36 GHz and a maximum oscillation frequency (f\max) around 7.37 GHz at a drain bias of 2 V. As far as LFN is concerned, the JL device shows approximately four orders of magnitude lower drain-current noise power spectral density (Sid) over conventional inversion-mode counterparts. These results demonstrate that the JL poly-Si TFT technique is promising for RF modules implemented in system-on-panel applications. [ABSTRACT FROM PUBLISHER]

A novel complementary metal-oxide-semiconductor inverter with poly-Si nanowire channels is proposed and demonstrated in this letter. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, the formation of the source and drain of both p-channel and n-channel devices requires only one lithographic step. The fabricated n-channel and p-channel field-effect transistors in the inverters show a high ON/OFF current ratio, an acceptable subthreshold swing, and a symmetric driving current, thus enabling the realization of excellent characteristics of the inverters. [ABSTRACT FROM PUBLISHER]

We have compared the temperature dependences of the current–voltage characteristics between single drain (SD) and lightly doped drain (LDD) poly-Si thin-film transistors (TFTs). It is found that the temperature dependence of the off-leakage current for the LDD TFT is larger because the electric field at the drain junction is weaker. Moreover, the change of the temperature dependence from low drain voltage (V \rm ds) to high Vds for the LDD TFT is smaller because the main mechanism of the off-leakage current is always phonon-assisted tunneling (PAT), whereas that for the SD TFT shifts from PAT to band-to-band tunneling. [ABSTRACT FROM PUBLISHER]

In this letter, we fabricated and characterized thin-film transistors with a suspended poly-Si nanowire (NW) channel and gate nitride with embedded silicon nanocrystals (Si NCs). The embedded Si NCs increase the surface roughness, thus reducing the adhesive force as the nitride is in contact with the poly-Si NW channel during the operation. Such a feature results in a reduction in pull-in voltage and sharper pull-out behavior. Moreover, this approach also greatly improves the endurance characteristics of the devices. [ABSTRACT FROM AUTHOR]

In this letter, we study the characteristics of n-type junctionless (JL) poly-Si thin-film transistors (TFTs) with an ultrathin and heavily phosphorous doped channel. The fabricated devices show excellent performance with a subthreshold swing of 240 mV/dec and an on/off current ratio of > \10^7. Moreover, the JL device shows 23 times increase in the on-state current at a gate overdrive of 4 V as compared with the conventional control device with an undoped channel. The significant improvement in the current drive is ascribed to the inherently high carrier concentration contained in the channel of the JL device. These results evidence the great potential of the JL poly-Si TFTs for the manufacturing of future 3-D and flat-panel electronic products. [ABSTRACT FROM PUBLISHER]

High-performance poly-Si-TFT-based TiN–alumina–nitride–vacuum–silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications. [ABSTRACT FROM AUTHOR]

We have analyzed the mechanism of off-leakage current in an lightly doped drain (LDD) poly-Si thin-film transistor by investigating the activation energy Ea. It is found that Ea decreases as the gate and drain voltages increase. We have also discussed the mechanism using a device simulator. It is found that a hole channel is lightly formed in the LDD region, and a pseudo p-n junction appears at the junction between the LDD and drain regions. The aforementioned experimental behavior of Ea is because the electric field increases there. These results suggest that the off-leakage current is caused by the phonon-assisted tunneling with Poole–Frenkel effect at the junction between the LDD and drain regions. [ABSTRACT FROM AUTHOR]

A capacitorless single-transistor (1T) memory cell with a long data-retention time is demonstrated on polycrystalline silicon thin-film transistors (TFTs). A new operation mode using channel traps is employed to modulate the drain current in the accumulation region. The different drain current can be read by modulating the barrier height at the grain boundary. The extrapolated retention time at the half of the current window is \sim\!\!\10^7\ \s. There is no degradation after 2000 write/erase cycles by trap-assisted tunneling programming. The low-temperature process of the TFT cells is attractive for the 3-D integration. [ABSTRACT FROM PUBLISHER]