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As the nano scale device performance depends on the detailed engineering of the dopant distribution, advanced doping processes are required. Progressing towards 3D-structures like FinFETs, studying the dopant gate overlap and conformality of doping calls for metrology with 3D-resolution and the ability to confine the analyzed volume to a small 3D-structure. We demonstrate that through an appropriate methodology this is feasible using Atom Probe Tomography (APT). We extract the 3D-dopant profile and important parameters such as gate overlap and profile steepness, from transistor formed with plasma doping processes. Analyzing samples with different doping processes, the APT results are entirely consistent with device performances (Ioff vs. Ion). [ABSTRACT FROM PUBLISHER]

Introduction: Series resistance (Rseries) is a crucial factor for technology optimization and benchmarking [1–3]. Rseries is typically extracted in the bias conditions where Rseries dominates, i.e., linear regime and high Vgs by comparing multiple gate lengths. However this simple extraction is very challenging for sub22nm CMOS devices as changing a device length / width may change mobility or Rseries. For instance, this is the case for SiGe where the built-in stress effect [5,6] increases the channel mobility thus making the standard extraction difficult. The case is even more compelling for the bulk finfet case where the length width and height may not be known with the necessary precision and the gate stack itself may introduce (un)wanted stress components. As any Rseries extraction do rely critically on assumptions, in this paper we will first test the applicability and limits of several Rseries extraction techniques [1–3] and then use the best of both to gain new insights on the finfet and SiGe technology. [ABSTRACT FROM PUBLISHER]

We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution. [ABSTRACT FROM PUBLISHER]