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In this article, taking into consideration the exceptional technological properties of a unique 2-D material, namely Graphene, we are envisioning its usage as the structure material of a non-back-gated re-programmable switching device. The proposed topology is analyzed in depth, not only by verifying its operation and re-programmability as a 2-input XOR, 3-input XOR and 3-input Majority gate, but also by examining its computing performance in terms of area, delay and power dissipation. More specifically, we are utilizing L-shaped Graphene Nanoribbons (GNRs) to develop comb-shaped Graphene based switching devices. These devices are in position with effective programming through biasing to design any combinatorial circuit as resulting from the aforementioned universal set of Boolean gates. The resulting figures of merit regarding the area with a universal footprint of $\text{2.53 nm}^{2}$ for every gate independently of the number of inputs, the propagation delay with $2.05\times {10^{-2}}\;\text{ps}$ and, last but not least, the power dissipation with only $\text{10.204 nW}$ for the gates with greater number of inputs, are quite encouraging and promising. Moreover, the ability of the proposed topology to pave the way towards the implementation of basic circuits has been further investigated, by demonstrating an example of a 1-bit full adder cell and its sufficient operation arriving from the corresponding successful SPICE simulation results. [ABSTRACT FROM AUTHOR]

We demonstrate nonvolatile and area-efficient ternary content-addressable memories (TCAMs) featuring amorphous indium–gallium–zinc–oxide (a-IGZO) ferroelectric field-effect transistors (FeFETs) with excellent electrical characteristics. An extremely large sensing margin of the TCAM array is achieved due to the large current ON/OFF ratio ($I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ of the a-IGZO FeFETs. Our HfxZr $_{\text {1-x}}\text{O}$ 2 (HZO)-based a-IGZO FeFETs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. By engineering the area ratio of the ferroelectric layer (${A}_{Fe}$) and the metal–oxide–semiconductor layer (${A}_{MOS}$), a large memory window (MW) of 2.9 V is realized. Reliability test results, including retention, endurance, and positive bias temperature instability, show long-term retention of more than ten years and high endurance of 108 cycles. In addition, by scaling the channel length down to 40 nm, ON current of $77 ~\mu \text{A}/ \mu \text{m}$ (${V}_{\mathrm{GS}} - {V}_{\mathrm{TH}}$ = 5 V and ${V}_{\mathrm{DS}}$ = 2 V) and ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ of more than eight orders can be obtained for the ultrascaled a-IGZO FeFETs while maintaining an MW of 2.8 V. [ABSTRACT FROM AUTHOR]

Conventional field-effect transistors (FETs) based on silicon downscaling are approaching physical limits, and thus, it is urgent to explore additional novel solutions to address this issue. The 2-D semiconductors have unique advantages as the channel material and provide a promising prospect for high-performance FETs in the post-Moore era. In this work, a new 2-D semiconductor, monolayer BeN2, is studied for the FET performance limits through first-principle quantum-transport simulations. Monolayer BeN2 exhibits a graphene-like planar structure with a direct bandgap of 1.3 eV. Transfer characteristics of sub-10-nm BeN2 FETs are thoroughly assessed through scaling gate length. In particular, 2-D BeN2 FETs with 10-nm gate present the ultrahigh ON-state current above $4500\,\, \mu \text{A}/\mu \text{m}$ for high-performance applications. Also, we realize the significant reduction of gate length (only 2.5 nm) against the International Technology Roadmap for Semiconductors (ITRS) requirements through introducing underlap structures. In addition, the performance of single devices based on monolayer BeN2 is evaluated and compared with some of the recently proposed 2-D devices. [ABSTRACT FROM AUTHOR]

In Part I of this article, we discussed the basic operation of 2-D Dirac-source field-effect transistors (DS-FETs) and studied the impact of key device parameters on the device performance. In this article, we continue to study the impact of nonidealities on the performance of DS-FETs, such as graphene disorder and rethermalization, as well as ways to mitigate them. In addition, we study the performance improvement by introducing a bandgap in the graphene source. Finally, we benchmark the performance of DS-FETs for different channel materials, providing a guide for the proper choice of material for 2-D DS-FETs. [ABSTRACT FROM AUTHOR]

Conventional bulk silicon is approaching its physical limit in the continued scaling of field-effect transistors (FETs). To extend the scaling limit of silicon-FETs, 2-D silicon semiconductors are highly desired because of the atomic thickness and mature CMOS-compatibility. By employing the hybrid honeycomb-kagome (hhk)-silicene monolayer as transport channel, we study the performance of sub-5-nm p- and n-type FETs based on ab initio quantum transport simulations. The hhk-silicene pFET (nFET) can be scaled down to 2-nm (3 nm) gate length (${L}_{g}$) with performances fulfilling the high-performance requirements of International Technology Roadmap for Semiconductors (ITRS) for 2028 horizon. Besides, with ${L}_{g}$ scales down to 3 nm, the subthreshold swing (SS) of the hhk-silicene FETs still can break the thermal limit of 60 mV/dec. The subthermal switches of hhk-silicene FETs benefit from the relatively isolated bands near the Fermi level. This work reveals the great potentials of hhk-silicene for ultrascaled and steep-slope FETs in future. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) transistors exemplify the fundamental tradeoff between desirable high mobility and undesirable leakage current due to the small effective mass and bandgap. To understand leakage current limits in high-speed CNT transistors, electrical bandgaps are extracted on 12 single-CNT top-gate MOSFETs from the energy gap between thermionic emission and band-to-band tunneling (BTBT) at 10 K. At 300 K the minimum IOFF at 0.5 V VDS is analyzed as a function of bandgap between 0.96 eV and 0.43 eV with IOFF-MINfrom 0.2 pA/CNT to 15 nA/CNT. NEGF simulation validates the bandgap extraction methodology and reproduces the experimental MOSFET IOFF-MIN data. A TCAD model calibrated to this work’s leakage data projects the accessible ION-IOFF design space bounded by CNT bandgap, indicating EG > 0.65 eV (dCNT < 1.3 nm) is needed to achieve 100 nA/ $\mu \text{m}$ at 0.5 V VDD and 250 CNT/ $\mu \text{m}$ for channel length above 20 nm. An EG of 1.06 eV (dCNT = 0.8 nm) can deliver $2750\times $ tunable range of IOFF by adjusting VT, which exceeds the $400\times $ tunable range of IOFF used in Si CMOS platform technologies. [ABSTRACT FROM AUTHOR]

We report the performance of field-effect transistors (FETs), composed of monolayer of recently synthesized layered two-dimensional (2-D) MoSi2N4 as channel material, using the first principles quantum transport simulations. The devices’ performance is assessed as per the International Roadmap for Devices and Systems (IRDS) 2020 roadmap for the year 2034 and compared to advanced silicon-based FETs, carbon nanotube-based FETs, and other promising 2-D materials-based FETs. Finally, we estimate the figure of merits of a combinational and a sequential logic circuit based on our double gate devices and benchmark against promising alternative logic technologies. The performance of our devices and circuits based on them is encouraging, and competitive to other logic alternatives. [ABSTRACT FROM AUTHOR]

In this work, the effects of Rare-Earth (RE) doping (Y, Gd, Dy, Yb) in HfO2 on the interface chemistry and leakage current conduction mechanism of Ge-MOS devices have been explored. The electrical experimental results have indicated that ${\text{HfREO}}_{\!{x}}$ (RE = Gd and Dy) show excellent performance, including the reduced flat-band voltage, almost disappeared hysteresis, and the decreased leakage current, which can be attributed to the tradeoff of performance between lanthanide-based oxides and HfO2. X-ray photoelectron spectroscopy (XPS) measurements also display that ${\text{HfGdO}}_{\!{x}}$ and ${\text{HfDyO}}_{\!{x}}$ gate dielectrics can effectively inhibit the formation of unstable Ge suboxides and low- ${k}$ germanate interface layer, leading to the reduced defect state at/near the interface and the improved electrical performance. In addition, the doping element-dependent leakage current conduction mechanism of Ge-based MOS devices under low temperature has been investigated systematically. As a result, it can be inferred that RE doping has a significant impact on Hf-based MOS capacitors, and Hf-based gate dielectrics doped with heavy RE elements show excellent application prospects in future microelectronic devices. [ABSTRACT FROM AUTHOR]

Pentagonal PdSe2 is a promising candidate for layered electronic devices due to its high air stability and anisotropic transport properties. Here, we investigate the performance of p-type field-effect transistors (p-FETs) based on PdSe2 monolayer using a multiscale simulation framework combining density functional theory and quantum transport. We find that monolayer PdSe2 devices show excellent switching characteristics (< 65 mV/dec) for the source-drain direction aligned along both [010] and [100] directions. Both directions also show good ON-state current and large transconductance though these are larger along the [010] direction for a 15-nm channel device. The channel length scaling study of these p-FETs indicates that the channel length can be easily scaled down to 7 nm without any significant compromise in the performance. Going below 7 nm, we find that there is a severe degradation in the subthreshold swing for a 4-nm channel length. However, this degradation can be minimized by introducing an underlap structure. The length of underlap is determined by the trade-off between the ON-state current and the switching performance. [ABSTRACT FROM AUTHOR]

The effects of a single point defect on InAs gate-all-around nanowire tunnel FETs (NW TFETs) are investigated. We considered two kinds of interfacial defects, the arsenic dangling bond (AsDB) and the arsenic antisite (AsIn). The critical physics related to the point defects, which are the charge trapping (CT), the trap-assisted tunneling, and their interplay, are rigorously captured using the full quantum transport model with the physical defect Hamiltonian obtained from the density functional theory calculations. We found that both defects on the NW cause the bandgap states, which crucially affects the TFETs performances. Through nonequilibrium Green’s function method self-consistently coupled with Poisson’s equation, the characteristics of the point defects under finite bias conditions are analyzed. We found that the CT is strong in AsIn, and thus the defect level, referenced to the valence band edge, is significantly changed by the gate bias. The strong CT leads to the screening of the gate field, which makes the defect level of AsIn effectively pinned near the drain Fermi level. The radial distributions of the density of states (DOS) and the phase relaxation time are analyzed. AsIn shows the strongly localized DOS at the defect center, while the DOS of AsDB is relatively delocalized due to the coupling with the valence bands. The impact of the defects on the TFET performances is examined as the gate length is scaled down. It is shown that AsIn acts as a limiting factor for scaling down of the TFETs. [ABSTRACT FROM AUTHOR]

In this article, for the first time, we propose a silicene-based spin filter having a TFET configuration. The device portrays a voltage-dependent spin polarization and achieves a “spin polarization” as high as 98% at a minimal “operating voltage” (0.35 V). The operation of the device is based on the “spin-polarized edge states” in a silicene nanoribbon. The “spin polarization” of the output current can be tuned by modifying the bandgap of the spin-up and spin-down states via an in-plane perpendicular “electric field” generated by two “lateral gates.” The device features high spin polarization apart from its expected integration with Si-based technology. The proposed device has a simple construction, wherein a single layer of Si atoms achieves such a high value of spin polarization at a minimal operating voltage. The operation of the proposed device is demonstrated by using the first-principles quantum transport simulations. [ABSTRACT FROM AUTHOR]

In this article, we propose a standard ternary inverter (STI) based on a dual-pocket tunnel FET (DP-TFET) for low-power applications. Using 2-D device simulations, we demonstrate that if appropriate doping concentration and length are chosen for the dual-pocket, then the device can exhibit ternary inverter voltage transfer characteristics (VTCs) with three stable output voltage levels. Ternary inverter characteristics are obtained by two tunneling mechanisms in the device: 1) gate bias-independent within-channel tunneling and 2) gate bias-dependent source-channel tunneling. We also demonstrate that the ternary inverter obtained could be operated at different supply voltages by controlling the pocket doping concentration. [ABSTRACT FROM AUTHOR]

We demonstrated a prototype Gated Lateral power bipolar junction transistor (GLP-BJT) on wide bandgap semiconductor. The device combined the intrinsic advantages of high current gain of a Gated Lateral-BJT and good current handling and voltage blocking capabilities of GaN material. As a result, the common-emitter current gain remained over 300 at a high collector current density of 2 kA/cm2 despite a wide p-base region of 2 μm. The open base breakdown voltage BVCEO was over 300 V corresponding to a high critical field of 2.5 MV/cm. These figures of merit show great promise of GaN-based GLP-BJT in power applications and also shed light on the development of state-of-the-art bipolar transistors based on other wide bandgap semiconductors. [ABSTRACT FROM AUTHOR]

The 5-nm-thick Mg0.05Sn0.95Ox thin film deposited using mist chemical vapor deposition is used as a channel layer of the thin-film transistor (TFT). Mg0.05Sn0.95Ox improves the crystallinity, reduces the number of oxygen deficiencies, and enlarges the energy bandgap compared with SnO2. Mg0.05Sn0.95Ox-based TFT shows higher field-effect mobility (144.9 cm2V−1s−1), steeper subthreshold slope (134 mV/decade), and significant ON/OFF current ratio (>109) than the SnO2-based TFT. Owing to fewer oxygen-related defects, wide energy bandgaps, and stable Mg-O chemical bonding, the Mg0.05Sn0.95Ox-based TFT exhibits more stable electrical performance than the SnO2 TFT after negative bias illumination stress testing. These results suggest that Mg0.05Sn0.95Ox is a promising material for high electron mobility TFT applications. [ABSTRACT FROM AUTHOR]

We present the comprehensive analysis and the compact modeling methodology of fast electron detrapping from the bandgap engineered tunneling oxide (BE-TOX) in 3-D NAND flash memories. To this end, we develop a physics-based detrapping model considering the detailed electron dynamics in the BE-TOX and various emission paths of the detrapping mechanism. By the aid of the carrier density rates from the accurately calibrated model, we find that the major path of the charge loss can be direct tunneling (DT) or trap-to-band tunneling (TBT) depending on the temperature and the nitride layer position in the BE-TOX. In addition, we compare the model result and the fitted stretched exponential function. From those comparisons, we correlate several indicators (time constant and curve shape) of the retention characteristics with the major paths of the charge loss. Finally, our model facilitates the quantitative separation of the detrapping mechanism into different paths. [ABSTRACT FROM AUTHOR]

A phenomenological all region drain current model for boron (B) or nitrogen (N) substitution-doped bottom gated graphene field effect transistor (GFET) is developed. In this work, a self-consistent approach is utilized to obtain appropriate potential-charge relation. The effects of substitution doping such as shift in Dirac point with significant nonzero bandgap, change in carrier sheet density and mobility are explicitly captured in this model. In addition to that the semiclassical diffusive mobility is modeled extensively as a function of two predominant parameters such as interaction parameter (rs) and impurity concentration (ni). The proposed drain current model and diffusive mobility model are predicting an excellent agreement with experimental data from fabricated B-doped bottom gated GFET. B/N substitution-doped bottom gated GFETs completely suppress the bipolar behavior and exhibit significant reduction in OFF-current. And, the ON/ OFF-ratio has been enhanced significantly from 1 to 8 × 104 as compared from undoped to 25% B-doped GFET, which makes B/N-doped GFETs well-suitable in digital applications. Also, B/N-doped GFETs enhance the saturation behavior which is highly desirable in analog/RF applications. Hence, B/N substitution doping in graphene fulfill the requirement of GFET in both analog/RF and digital applications. [ABSTRACT FROM AUTHOR]

In this paper, OR and AND logic gate functions are realized in a triangular lattice using two dimensional photonic crystal (2DPC). The proposed design of logic gates are based on the phenomenon of resonance and interference. The OR and AND logic gates are constructed by varying the rod radius and by creating Y-shaped waveguide in the structure. Initially, the OR gate is designed with reference input and without reference input and it's extended for AND gate. The functional parameters of the logic gates such as response period, bit rate, contrast ratio and field distribution of different logics are investigated through 2D finite difference time domain (FDTD) method. The contrast ratio, response period, bit rate and size of the three input OR gate are 30 dB, 0.52 ps, 1.92 Tbps and 12.6 μm×11 μm, respectively. Similarly, the aforementioned parameters are estimated for two input OR gate, two input AND gate and three input AND gate. The proposed logic gates are highly desirable for integrated optics. [ABSTRACT FROM AUTHOR]

Polarity regulation is the biggest obstacle to the application of two-dimensional materials in logic circuits. Here, we demonstrate an innocuous doping strategy for modulating the polarity of WSe2 field-effect transistors (FETs). The substoichiometric indium oxide (InOx) was employed to realize the n-type WSe2 FETs. In stark contrast to others reporting the reduction of electron-dominant current with n-type metal/oxide doping, the InOx-doped strategy demonstrated herein facilitates superior electron-dominant current, which can be attributed to the van der Waals interface between InOx and WSe2. Furthermore, the InOx-doped n-type FET was connected with the undoped p-type FET to construct an inverter, which exhibited an ultrahigh Gain exceeding 120 with a full width at half of the maximum gain of only 30 mV and total noise margin around 80%. The damage-free doping strategy allowed the integration of complementary WSe2 FETs with impressive performance, thereby paving the way for practical applications in WSe2 integrated circuits. [ABSTRACT FROM AUTHOR]

A novel CMOS-compatible SiGe Tunnel Field-Effect Transistor (TFET) with a high current drivability is demonstrated, which features a vertically-stacked SiGe nanosheet (NS) with high Ge content and gate-all-around(GAA) structure to improve carrier injection efficiency and gate controllability. A multi-NS Si 0.2 Ge0.8 channel is formed by the Si selective etching and Ge condensation technique. The measured data shows both the 50 mV/dec minimum subthreshold swing (SS) and 70 mV/dec average SS over 3 decades of drain current change. Compared to previously reported devices, it is clear that the proposed SiGe nanosheet TFET can achieve steeper switching and low-level leakage current with a low drive voltage as an alternative to conventional MOSFET. [ABSTRACT FROM AUTHOR]

The combination of the InAs/GaSb heterojunction and the line-tunneling mechanism is considered as one of the most promising approaches to simultaneously obtain high ON-state current (ION) and low subthreshold swing (SS) in tunneling field effect transistors (TFETs). However, in an InAs/GaSb line-tunneling field effect transistor (LTFET), the isolation between the source and the drain is a big issue. The leakage current path could lead to complete loss of the OFF-state characteristics in extreme cases. The “cantilever” or “airbridge” structure is usually introduced to cutoff the leakage path. However, it also induces serious reliability problems and brings additional process complexity. In this article, an N+ doped buried drain is first proposed to form a reverse biased p-n junction with the P+ source and effectively cuts the leakage current path off. The InAs GaSb LTFETs with this buried drain technique exhibits ION/IOFF > 107 and SS < 60 mV dec for five decades of current. Besides the excellent performance, the buried drain technique keeps the device planar and brings no additional fabrication complexity, which is of great significance for future experimental investigation and the low power applications. [ABSTRACT FROM AUTHOR]

In this article, a device called GaAs/InAs/Ge junctionless tunnel field-effect transistor (JL-TFET) is proposed and investigated by a numerical simulator. This device utilizes an InAs pocket at the source side and its digital performance parameters such as subthreshold slope (SS) and ON-state current to OFF-state current (ION/IOFF) ratio have been improved in comparison with GaAs/Ge JL-TFET. Simulation results show that the electron tunneling mechanism is based on intraband tunneling and interband tunneling in GaAs/InAs/Ge JL-TFET, while the electron tunneling mechanism is interband tunneling in regular JL-TFET. To further reduce SS, we have proposed for the first time GaAs/InAs/Ge JL-TFET structure with a fixed gate (f-gate), the so-called dual-material gate (DMG) GaAs/InAs/Ge JL-TFET. The f-gate induces a local dip in the conduction band edge leading to more abrupt band bending at the vicinity of the InAs/GaAs interface. Simulation results show that DMG GaAs/InAs/Ge JL-TFET is turned on at lower VGS compared to GaAs/InAs/Ge JL-TFET, causing a SS is improved. A brief examination of the proposed device has been done on the impacts of both the variations of the f-gate work-function (φF) and the f-gate length (Lf-gate). The DMG GaAs/InAs/Ge JL-TFET with a channel length of 20 nm, φF = 3.7 eV, and Lf-gate = 5 nm showed the average SS of SS = 2.1 mV/dec, and ON-state current of ION = 0.51 mA/μm. The SS and ION of the DMG GaAs/InAs/Ge device are improved by 150% and 76%, respectively, compared to the GaAs/Ge JL-TFET device with similar dimensions. The DMG GaAs/InAs/Ge JL-TFET device proposed in this article can be a reasonable candidate for digital applications. [ABSTRACT FROM AUTHOR]

The electrostrictive 2-D field-effect transistor (EFET) is a steep-slope device that promises to offer aggressive length and voltage scalability. Two key features of this device are its high-drive strength with high ON–OFF current ratio and the isolated back-gate terminal, which provides us the fourth knob to control the transistor drive strength. The disadvantage of the technology is the increased device capacitance incurred due to the additional piezoelectric layer in the transistor structure. Second, although the back-gate biasing of EFETs provides us the fourth knob of control, statically biasing the back gate increases the static power consumption. Despite the idiosyncrasies of the technology, this work shows the use of EFETs in field-programmable gate arrays (FPGAs) to be advantageous because the added energy cost of device capacitance gets amortized by the improvement in performance and energy efficiency of using high-drive EFET transistors in the FPGA interconnect architecture. We also show that co-optimization of back-bias voltage along with transduction efficiency is essential in the FPGA subcircuit level for achieving an energy-efficient architecture. This work highlights the specific design approach tradeoffs that differ from prior CMOS approaches and provides guidance for the engineering parameters necessary for EFETs to evolve as a competitive technology. [ABSTRACT FROM AUTHOR]

We demonstrate the electronic trap energy distribution (Δ EIL) in the wide bandgap, nonconventional aluminum oxide phosphate (ALPO) dielectrics. The trap energy distribution has been measured by using the gate injection high-speed capacitance–voltage measurement technique and verified through conventional deep-level transient spectroscopy. The electronic trap energies in ALPO dielectrics were found to be influenced and, hence, tunable by the irradiation temperature. The nonirradiated dielectric film (NI-ALPO) displayed the maximum number of electronic traps at an energy level of 0.2 eV below the conduction band of silicon (Si-ECB). On the other hand, the dielectric film irradiated at 200 °C confirmed the highest number of traps at the location of 0 eV and at the same energy level of Si-ECB. In addition, the NI-ALPO dielectric contained over 90% of traps in the deep level of the bandgap (below Si-ECB). In contrast, the ALPO film irradiated at 200 °C accommodated a limited number of traps (~75%) at the deep level of the bandgap. [ABSTRACT FROM AUTHOR]

The performance of ultra-wide bandgap semiconductors like β-Ga2O3 is critically dependent on achieving high average electric fields within the active region of the device. In this article, we show that dielectrics like BaTiO3 with extremely high dielectric constant can provide an efficient field management strategy by improving the uniformity of electric field profile within the gate–drain region of lateral field-effect transistors. Using this strategy, we achieved high average breakdown field of 1.5 and 4 MV/cm at gate–drain spacing (Lgd) of 6 and 0.5~μm, respectively in β-Ga2O3, at a high channel sheet charge density of 1.6 × 1013 cm−2. The high channel charge density along with the high breakdown field enabled a record power figure of merit (Vbr2/RON) of 376 MW/cm2 at a gate–drain spacing of 3~μm. [ABSTRACT FROM AUTHOR]

We have demonstrated, for the first time, a surrounding gate vertical-channel field-effect transistor (FET) with a gate length of 40 nm by introducing back-end-of-line (BEOL) process-compatible oxide semiconductor (OS) In-Al-Zn-O as a channel material. Fabricated FETs exhibited high scalability by excellent thermal stability (~420 °C) compared to conventional In-Ga-Zn-O-channel FETs, with high-mobility (12.7 cm2/V.s) characteristics. Furthermore, the vertical-channel FET also exhibited excellent reliability and stable operation without floating body effect. Endurance of over 1011 cycles was also demonstrated. Our work opens a pathway to realization of high-performance BEOL transistor for 3-D-large-scale integration (LSI) applications. [ABSTRACT FROM AUTHOR]

This article proposes a bandgap reference (BGR) recursive low-dropout (LDO) regulator chip that achieves a high power supply rejection (PSR) in the low- to mid-frequency range. The presented LDO design enables the total PSR of LDO to be free from the finite ripple-rejection of the BGR circuit, resulting in low design complexity and low power consumption. To improve the PSR further, the gate buffer is modified to provide an additional ripple feedforward cancellation. The modified gate buffer also offers fast transient response and stable operation. Moreover, a light-load stabilizer loop is also suggested to provide high stability over all load conditions. A prototype chip able to supply up to 300 mA output current was implemented by 0.5-μm 5-V CMOS devices. The PSR was measured to be –102 to –80 dB at frequencies from 100 Hz to 0.1 MHz, which is higher than that of prior LDOs with COUT ≥ 1 μF. The proposed LDO consumes only 50 μA at a load current of 300 mA, and a peak current efficiency of 99.98% was achieved. The line and load regulations were measured as 0.003%/V and 0.28%/A, respectively. This chip shows a figure-of-merit of 11 ps in the transient response. [ABSTRACT FROM AUTHOR]

Failure of metal–oxide–semiconductor field-effect transistor (MOSFET) in the nanometer regime has raised concern for the researchers. Although researchers have provided solutions in the form of tunnel FETs and junctionless transistors but due to their fabrication issues, MOSFET remains as the backbone of the very large-scale integration (VLSI) industry. This work is dedicated to the design and study of the novel split-gate MOSFET made up of transition metal dichalcogenide. The proposed design can help in realizing digital gates because the device is used as a single transistor AND gate in this work. The device is analyzed for different conditions like the variation in work function, variation in gate length, variation in spacer oxide, and effect of interface trap charge (ITC) density. Nonequilibrium Green’s Function is used as an elemental model of the transistor to include quantum effects for scaled-down dimensions. This work shows that the proposed device results in a noticeable flow of current only when both the gate terminals are at higher potential, that is, at state “11.” The observed linearity is good enough for the efficient working of the device. Hence, the device can be utilized as AND gate with a lesser area and power dissipation. [ABSTRACT FROM AUTHOR]

Resonant-tunneling diodes (RTDs) based on graphene nanoribbons have attracted the attention of many researchers recently. In this article, we propose a new RTD based on graphene nanoribbon/h-boron nitride. In this structure, two hexagonal boron nitride (h-BN) slices are used as potential barriers to form a double-barrier structure, due to the higher bandgap of h-BN. Two gate electrodes are used in order to control the peak-to-valley current ratio (PVR). In the proposed structure, a PVR of 1.11 at a valley current of 5.56~μ A and a PVR of 2.41 at a valley current of 0.49~μ A have been obtained that are better than many reported structures in the literature. The proposed structure is a suitable candidate for use in various high current RTD-based applications. A numerical tight-binding model coupled with nonequilibrium Green’s function formalism is used for simulation and studying electronic properties of this structure. [ABSTRACT FROM AUTHOR]

In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to 2.7 × larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing VB-enabled SRAM designs. [ABSTRACT FROM AUTHOR]

In Part I of this article, we had discussed the device characteristics of 2D Strain FET (2D-SFET) and 6T-SRAM with 2D-SFET used as a drop-in replacement for 2D-FET. Here (in Part II), we propose 2D-SFET-based 6T-SRAM designs targeted toward improving cell robustness (which is otherwise low in 2D-SFET SRAMs analyzed in Part I). Our 2D-SFET-based 6T-SRAM designs, namely Schmitt Trigger (ST) SRAM, Schmitt Trigger with Data-Driven Access Feedback (ST-DAF) SRAM and Schmitt Trigger with Dual Word-line (ST-DWL) SRAM leverage back voltage (VB)-driven dynamic bandgap change in 2D-SFET to mitigate the design conflicts. We show that in all designs ST action is achieved by dynamically tuning the strength of pull-up 2D-SFETs enabled by VB. This along with other optimizations result in up to 33% higher read stability in the proposed designs over 2D-FET-based standard 6T SRAM, while mitigating the design conflicts present in standard 6T SRAMs. Our analysis also highlights the benefits and trade-offs for write and hold operations for each of our designs. All the proposed 2D-SFET VB-enabled SRAMs achieve the enhanced functionalities at iso-area compared to 2D-SFET drop-in SRAM in Part I. [ABSTRACT FROM AUTHOR]

Schottky-barrier field-effect transistors (SBF-ETs) based on 2-D semiconductors had been investigated as a substitute for a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) based on bulk silicon in the field of high-performance (HP) device. Especially, the monolayer SiC has been studied because it has a large band gap, which results in reducing the short-channel effect. In this article, the gate–source/drain underlap-dependent characteristics of HP SBFETs based on monolayer SiC with 5.1- and 4.6-nm gate lengths are investigated through ab initio simulations. The performances of the 5.1-nm monolayer SiC SBFET are degraded by the gate–source/drain underlap. The gate–source/drain underlap, however, shows the different improved performances for the 4.6-nm monolayer SiC SBFET. The gate–source underlap could enhance the ON-current to 2792~μA/μm and the gate–drain underlap can enhance the ON-current to 1754~μA/μm, which all far exceed the International Technology Roadmap for Semiconductors (ITRS) requirement. [ABSTRACT FROM AUTHOR]

Power and RF electronics applications have spurred massive investment into a range of wide and ultrawide bandgap semiconductor devices which can switch large currents and voltages rapidly with low losses. However, the end systems using these devices are often limited by the parasitics of integrating and driving these chips from the silicon complementary metal–oxide-semiconductor-based design (CMOS) circuitry necessary for complex control logic. For that reason, implementation of CMOS logic directly in the wide bandgap platform has become a way for each maturing material to compete. This review examines potential CMOS monolithic and hybrid approaches in a variety of wide bandgap materials. [ABSTRACT FROM AUTHOR]

In this work, we present a numerical investigation of the asymmetric double nonlinear coupling of photonic crystal fibers in an on‐off switch to obtain fully optical logic gates. Ultra‐short pulses (100 fs) are propagated through the device in three distinct excitation power regimes, power below critical (Po = 72 kW, where Po represents the excitation power of the device), critical power (Pc = 103.5 kW, where Pc represents critical Power for which the power switching is 50% for both guides. There are cases where Po is above the critical value, there are cases that is below), and power above critical (Po = 110 kW). The pulse switching characteristics are analyzed as a function of the input power and the nonlinearity profile (β‐beta) inserted in one of the component guides. The nonlinearity profiles follow the regimes: constant, increasing and decreasing, and high order effects, such as third‐order dispersion, intrapulse Raman scattering and self‐steepening are included in the generalized Schrödinger nonlinear equation governs the pulse propagation dynamics. The results show that the proposed device can be used to obtain AND, OR, and NOT logic gate. Numerical studies were done from the coupled‐coupled equations solved using the fourth‐order Runge‐Kutta method, using MATLAB as a programming tool for solving equations. The implementation of fully optical logic gates tends to revolutionize new digital systems in the field of data storage, such as optical memory, "replacement" of electronic circuits among other applications. Optical systems have a great advantage as they are free from electromagnetic interference and have high rates of data transmission. [ABSTRACT FROM AUTHOR]

In this article, we present, for the first time, the results of simulation and analysis of the current–voltage characteristics of germanium–tin electron–hole bilayer tunnel field-effect transistor (EHB TFET) of various compositions of the semiconductor substrate. Ge1−xSnx is an interesting material due to the possibility of tuning the band structure by changing the Sn content. The direct and indirect bandgap of GeSn can be changed to affect the direct and phonon-assisted band-to-band tunneling currents. In this article, both currents are calculated for various compositions of Ge1−xSnx and the channel body thickness as a parameter. The simulated structure exhibits steep-slope current–voltage characteristics due to the reduced carrier dimensionality and the use of 2-D–2-D tunneling as the transport mechanism. Sudden current bumps on characteristics are related to the alignment of the subsequent hole and electron energy levels in the gate-induced surface quantum wells. An increase in the Sn content results in a boost of the ON-current, which is related to the higher magnitude of the direct tunneling current. This effect depends strongly on the body thickness. We show that the application of GeSn in EHB TFET structure can be beneficial in terms of low-power applications. [ABSTRACT FROM AUTHOR]

Here, the electronic properties and ballistic transport properties of two-dimensional (2D) ZrNBr are comprehensively investigated by the nonequilibrium Green’s function coupled with density functional theory. 2D ZrNBr has a wide direct band gap of 1.82 eV with the highest mobility of 8700cm $^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$. Both the n- and p-type 2D ZrNBr MOSFETs with 5-nm channel length hold the on-currents above $2300~\mu \text{A}/\mu \text{m}$ for high-performance devices and an on/off ratio exceeding 106 for low-power applications, which is of great value for the design of complementary circuits in 2D electronics. In addition, the energy-delay products of the single 2D ZrNBr MOSFETs and the 32-bit Arithmetic Logic Unit show more potential compared to other 2D materials and CMOS proposals. Thus, this work broadens a promising path towards beyond-silicon electronic systems. [ABSTRACT FROM AUTHOR]

A design of n-type InAs piezoelectric tunnel FETs (PE-TFETs), which is worth further experimental verification, is proposed for steep sub-threshold slope and studied using TCAD simulations. Piezoelectric layers (PE-layer) are inserted in gate stacks to induce dynamic compressive strain and to modulate the band gap during switching. The non-equilibrium Green’s function (NEGF) approach with strained 8-band k⋅p Hamiltonian is used to investigate the PE-TFETs performance. Our results suggest that PE-TFETs are compressively strained perpendicular to the transport direction at OFF state, while PE-TFETs feel no strain at ON state. This compressive strain enlarges the channel band gap and meanwhile reduces the tunneling energy window, which greatly suppresses OFF current. In this work, the n-type InAs PE-TFETs achieve 50 times lower OFF current than conventional TFETs, and the minimum SS of PE-TFETs is 48 mV/dec with 0.5 V supply voltage. Moreover, the proposed design is helpful to suppress the ambipolar current. [ABSTRACT FROM AUTHOR]

In this article, an electrical doping method to realize the high n-type doping for a germanium (Ge) layer in a low-doped n-type Ge metal-oxide-semiconductor (MOS) structure in the accumulation condition is proposed, which maintains the initial crystal quality of Ge. The direct-bandgap electroluminescence (EL) from Ge light-emitting diode (LED) has been demonstrated with 1.5– 1.6μm infrared emission using the metal/graphene/high-k/ interfacial layer (IL)/n-Ge MOS structure fabricated on bulk-Ge substrate. An onset current density of 5 A cm−2 is observed, which is, up to now, the lowest onset current density compared with the Ge LEDs fabricated on unstrained Ge substrates. These results indicate the superiority of the electrical doping method and the interface passivation technique on yielding the high-performance Ge-based LEDs and lasers. [ABSTRACT FROM AUTHOR]

Based on the nonequilibrium Green’s function method combined with density functional theory, a nanoscale tiny diode is designed by doping B and P in armchair graphene nanoribbons (AGNRs). Moreover, the mechanism of its rectification may be explored by the analysis of transmission spectrum and energy band. The analysis of simulation data shows that the relationship between rectification and transmission peak at −0.25 eV is very close, and the broadening and disappearance of the peak may be explained by the local device density of states (DOS) and electrostatic difference potential. In addition, the eigenstates of the highest occupied molecular orbital and the lowest unoccupied molecular orbital under different bias voltages also explain the change of the transmission spectra. Moreover, the occurrence of rectification also can be ascribed to the difference of effective mass between Ev and Ec and distinctive position of π and π* in band structure. [ABSTRACT FROM AUTHOR]

As the p-type doping β-Ga2O3 is absent up to now, metal gate (MG) stacks with high work functions are expected to benefit the fabrication of normally- OFF β-Ga2O3 transistors. In this article, the electrical characteristics of β-Ga2O3 metal-electrode-gated metal–oxide–semiconductor (MOS) devices with Al-rich HfAlO dielectrics and different MG stacks (Ni, Au, Pt, and Ti) are evaluated. The interface state density (Dit) of HfAlO/β-Ga2O3 interface is characterized based on the frequency-dependent capacitance–voltage (C − V) and photo-assisted deep ultraviolet (DUV) C − V measurements. An average Dit of 4.45 × 1011 eV−1 cm−2 is extracted from the photo-assisted (deep UV) C − V measurement, while a large amount of border traps, negative fixed charges, and deep traps is also induced at the oxide layer and/or HfAlO/β-Ga2O3 interface. Then, this article investigates the evaluations of Ti, Ni, Au, and Pt as candidate MGs for β-Ga2O3 MOS using Al-rich HfAlO as gate dielectric. The obvious flat-band voltage (VFB) shift and gate leakage variation are observed in β-Ga2O3 capacitors with different MG solutions, indicating that HfAlO dielectric combined with Ni, Au, and Pt MGs is promising to facilitate some beneficial modifications of normally- OFF β-Ga2O3 transistors, while Ti electrode is more suitable for normally- ON β-Ga2O3 transistors. This article provides an additional practical guideline for choosing the appropriate MG stacks and potential gate dielectric to the development of normally-OFF Ga2O3 transistors. [ABSTRACT FROM AUTHOR]

This article is the first report of MOSFETs fabricated on PtSe2 grown by molecular beam epitaxy. Both material synthesis and device fabrication are done below 450 °C—the thermal budget of CMOS back-end-of-line processes. The MOSFETs are batch-fabricated by a CMOS-compatible process on 200-mm-diameter Si substrates prepared by a state-of-the-art BiCMOS foundry. With three monolayers of PtSe2, an n-type MOSFET exhibits a current ON/OFF ratio of 43 at room temperature, which increases to 1600 at 80 K. These results are among the best of transistors based on synthesized PtSe2. Despite the thin PtSe2 layer, doping by contact bias lowers the contact resistance significantly and boosts the current capacity and the ON/OFF ratio. Temperature-dependent current-voltage characteristics imply a bandgap of approximately 0.2 eV, which confirms that the semiconductor-semimetal transition of PtSe2 is not as abrupt as originally predicted. Better MOSFET performance can be expected by growing even thinner PtSe2 uniformly and by thickening the PtSe2 in the contact regions. [ABSTRACT FROM AUTHOR]

Schottky-barrier field-effect transistors (SBFETs) based on monolayer SiC contacting four metals (Ag, Au, Al, and Pd) have been proposed using density functional theory and ab initio simulations. The n-type Schottky contacts could be formed between monolayer SiC and Ag, Au electrodes with electron Schottky barrier heights (SBHs) of 0.7 and 1.1 eV, respectively, whereas the p-type Schottky contacts were formed between monolayer SiC and Al, Pd electrodes with hole SBHs of 1.0 and 0.1 eV, respectively. When the gate length was equal to 5.1 nm, SiC-SBFETs with four metals could all overcome the short-channel effect due to the wide bandgap of SiC. In addition, the SiC-SBFET with Pd electrode provided the best performance and could satisfy the performance requirement of high-performance transistor with gate length of 5.1 nm outlined by the International Technology Roadmap for Semiconductors (ITRS). Our study gives an insight into the monolayer SiC–metal interfaces and, thus could be developed into a viable 5-nm “More than Moore” device in the future. [ABSTRACT FROM AUTHOR]

In this article, we investigate a variant of the line-tunnel FET employing dual MOS–capacitor (MOSCAP) extensions incorporating field-induced quantum confinement (FIQC). Unlike Gate-over-Source (GoSo) TFET having an all-lateral design, dual-MOS (D-MOS) TFET has raised channel/drain regions exhibiting better electrostatics at the 2-D source boundary. At similar dimensions, 2-D-calibrated simulations reveal that under No-FIQC condition, D-MOS exhibits $2.1\times $ better ${I} _{ \mathrm{\scriptscriptstyle ON}}$ along with much improved parasitic leakage in the OFF-state (${V} _{ \mathrm{GS}}=\textsf {0}$ V, ${V} _{\textsf {DS}}=\textsf {1}$ V). Energy quantization due to FIQC in the conduction band (CB) near the gate dielectric is captured along with the reshaped carrier density distribution. The delay in the onset of vertical band-to-band tunneling (BTBT), $\Delta {V}_{\textsf {BTBT}}$ shift, and deterioration in ${I} _{ \mathrm{\scriptscriptstyle ON}}$ are also calculated. We later observe that the use of a dual-metal-gate (DMG) and an unequal lateral/vertical oxide thickness as structural improvements further eliminates the parasitic leakage. In addition, with the gate–drain underlap (${L} _{\textsf {GD}}$) up to 10 nm, a reduction in intrinsic delay is also observed. [ABSTRACT FROM AUTHOR]

The observation of a significant temperature-dependent variation in the ${I}$ – ${V}$ characteristics of tunneling devices is often interpreted as a signature of a trap-assisted-tunneling dominated current. In this letter, we use a ballistic 2D quantum-mechanical simulator, calibrated using the measured temperature-dependent ${I}$ – ${V}$ characteristics of Esaki diodes, to demonstrate that the temperature dependence of band-to-band tunneling (BTBT) current can vary significantly in both Esaki diodes and tunnel FETs. The variation of BTBT current with temperature is impacted by doping concentration, gate voltage, possible presence of a highly-doped pocket at the tunnel junction, and material. [ABSTRACT FROM AUTHOR]

The back-channel-etch amorphous InGaZnO (a-IGZO) double-layer thin-film transistor (DL-TFT) consists of an a-IGZO layer with no oxygen flow (NOF) as a top layer and an a-IGZO layer with oxygen flow (OF) as a bottom layer. The DL-TFT demonstrates the field-effect mobility of 19 cm2/V–s, which is $1.6\times $ of the NOF and the OF single-layer TFTs (SL-TFTs) at the overdrive voltage of 18 V and the drain voltage of 0.1 V. Several measurements are performed to obtain the band alignment between the NOF and the OF layer for further understandings of the mechanism of the improvement in the field-effect mobility. Tauc method, X-ray photoelectron spectroscopy, and Kelvin probe force microscopy measurements were used to extract the optical bandgaps, the Fermi level position, and the work function of the NOF and the OF, respectively. The conduction band difference of 0.28 eV between the NOF and the OF layer is obtained. The carriers in the DL-TFT are confined in the NOF layer by quantum confinement, where the OF layer serves as the barrier to reduce the Coulomb scattering and the surface roughness scattering. [ABSTRACT FROM AUTHOR]

We present a 1-V precision voltage reference with a programmable temperature coefficient (“temp-co”). The voltage reference is based on a parasitic bipolar junction transistor (BJT) realized within the process steps available in the chosen 7-nm FinFET technology. Details of its characterization and SPICE modeling are presented to provide insight into key device–circuit optimization choices. The trimming techniques needed to cope with process spread together with two curvature compensation techniques are presented. The reference achieves a maximum inaccuracy of ±0.2% and a minimum temp-co of 6 ppm/°C from −45°C to 125°C. Furthermore, its temp-co is digitally programmable between −7 mV/100°C and +8 mV/100°C. Its line regulation is 0.1%/V, and it occupies 0.078 mm2. [ABSTRACT FROM AUTHOR]

A ternary alloy rare-earth scandate, (Y0.6Sc0.4)2O3, is demonstrated as a high- ${k}$ dielectric insulator for $\beta $ -Ga2O3 MOS devices. (Y0.6Sc0.4)2O3/ $\beta $ -Ga2O3 (010) MOS capacitors were fabricated and characterized using capacitance–voltage (${C}$ – ${V}$) techniques and interface state density (${D} _{\mathrm {it}}$) methods. The ${D} _{\mathrm {it}}$ distribution was extracted using photo-assisted C–V with a 265-nm light-emitting diode (LED), demonstrating a peak ${D} _{\mathrm {it}}$ value of $4 \times 10^{12}$ cm−2 eV−1 near the conduction band, and dropping to below $2 \times 10^{11}$ cm−2 eV−1 at 0.9 eV below the conduction band. A total interface charge of $< 1 \times 10^{12}$ cm−2 was calculated based on the experimental data. Similar ${D} _{\mathrm {it}}$ values were observed using the Terman method for the energy range 0.35–0.55 eV below the conduction band. Current–voltage (${J}$ – ${V}$) measurements showed rising accumulation leakage current due to bulk-limited transport of electrons through traps in the (Y0.6Sc0.4)2O3 and low depletion leakage current limited by the generation of holes from deep-level $\beta $ -Ga2O3 traps. High breakdown fields of 4.3– $6.0\,\,\text {MV}\cdot \text {cm}^{-1}$ were observed. The low ${D} _{\mathrm {it}}$ value shows the excellent potential of (Y0.6Sc0.4)2O3 as a gate dielectric for $\beta $ -Ga2O3 metal–oxide–semiconductor field-effect transistors (MOSFETs). [ABSTRACT FROM AUTHOR]

We investigate the impact of gate-stack engineering using W/ZrO2/Al2O3 on the performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that 1-nm-thick capacitance equivalent thickness (CET) with low leakage current is achieved by using ZrO2 with the dielectric constant of around 40 on In0.53Ga0.47As. On the other hand, the reduction of Dit by insertion of ALD 1–5 cycle Al2O3 interfacial layers (ILs) is found to be mandatory for obtaining TFET performance enhancement. The planar-type InGaAs TFETs using the ZrO2/Al2O3 IL gate-stack with CET of 1 nm exhibit the minimum subthreshold swing (S. $\text{S}_{\min }$) of 55 mV/dec and ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of $0.88~\mu \text{A}/\mu \text{m}$ (${V}_{\text {G}}$ – ${V}_{ \mathrm{\scriptscriptstyle OFF}}= \text {0.5}$ V, ${V}_{\text {D}}= \text {0.2}$ V, and ${I}_{ \mathrm{\scriptscriptstyle OFF}}= \text {10}$ pA/ $\mu \text{m}$). Furthermore, the ZrO2/Al2O3 IL gate-stack is applied to the optimized In0.75Ga0.25As quantum well (QW) channel TFETs. The low S. $\text{S}_{\min }$ of 50 mV/dec and high ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of $1.2~\mu \text{A}/\mu \text{m}$ (${V}_{\text {G}}$ – ${V}_{ \mathrm{\scriptscriptstyle OFF}}= \text {0.5}$ V, ${V}_{\text {D}}= \text {0.2}$ V, ${I}_{ \mathrm{\scriptscriptstyle OFF}}= \text {10}$ pA/ $\mu \text{m}$ , and CET = 1.1 nm) are demonstrated by combing the present ZrO2-based gate-stack with the optimum In0.75Ga0.25As QW channel structure. [ABSTRACT FROM AUTHOR]

In this paper, the electron transport properties of a C3N nanoribbon-based field-effect transistor (FET) in the ballistic regime have been simulated. Using the density-functional theory (DFT) to obtain the band structures, we found that the armchair-edged C3N nanoribbons are semiconductors, and their bandgaps are determined by their widths, while the zigzag-edged ribbons present the metallic properties. We have carried out calculations to study the transport properties of armchair-edged C3N nanoribbon by using DFT combined with the nonequilibrium Green’s function. Our simulation results revealed that both bandgap and current on/off ratio are reduced as the width increasing. Moreover, the gate length, channel length, and ribbon’s width are found to have prominent influences on the transfer characteristics. The armchair-edged C3N nanoribbon-based FETs have the highest current on/off ratio of 106 and the ideal subthreshold swing of 61.2 mV/dec, which make it promising for potential applications of FET. [ABSTRACT FROM AUTHOR]

High-performance p-channel transistors are crucial to implementing efficient complementary circuits in wide-bandgap electronics, but progress on such devices has lagged far behind their powerful electron-based counterparts due to the inherent challenges of manipulating holes in wide-gap semiconductors. Building on recent advances in materials growth, this work sets simultaneous records in both on-current (10 mA/mm) and on-off modulation (four orders) for the GaN/AlN wide-bandgap p-FET structure. A compact analytical pFET model is derived, and the results are benchmarked against the various alternatives in the literature, clarifying the heterostructure trade-offs to enable integrated wide-bandgap CMOS for next-generation compact high-power devices. [ABSTRACT FROM AUTHOR]