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HfO2 layers, 25-Å thick, were grown by cyclic Hf sputter deposition and room temperature oxidation steps on chemically oxidized Si(001). Subsequent in situ annealing and TiN deposition yield a high- \kappa gate-stack for which the original 8-Å-thick SiO2 layer is eliminated, as confirmed by transmission electron microscopy. Transistors fabricated with this gate-stack achieve an equivalent oxide thickness in inversion T_{\rm inv} =9.7 Å, with a gate leakage J_{g} =0.8 A/cm2. Devices fabricated without in situ annealing of the HfO2 layer yield a Tinv which increases from 10.8 to 11.2 Å as the oxidation time during each HfO2 growth cycle increases from 10 to 120 s, also causing a decrease in Jg from 0.95 to 0.60 A/cm2, and an increase in the transistor threshold voltage from 272 to 294 mV. The annealing step reduces Tinv by 1.5 Å (10%) but also increases the gate leakage by 0.1 A/cm2 (30%), and causes a 61 mV reduction in Vt . These effects are primarily attributed to the oxygen-deficiency of the as-deposited HfO2, which facilitates both the reduction of an interfacial SiO2 layer and a partial phase transition to a high- $\kappa $ cubic or tetragonal HfO2 phase. [ABSTRACT FROM AUTHOR]

We investigate the determining mechanisms of the inversion-layer capacitance Cinv in the high-k/metal gate stacks, focusing on the two perturbative effects related with the dielectric properties. Those effects are the penetration of inversion-layer carriers into the dielectrics with a finite potential barrier and the image potential acting on the carriers adjacent to the dielectrics with permittivity different from that of the silicon substrate. The experimental and the theoretical analyses of the Cinv dependency on the crystal orientation of silicon substrates enable us to separate the two effects and to prove that the observed Cinv modulation in the high- k/metal gate stacks is attributable not to the image potential effect, but to the penetration effect. Moreover, we investigate the reduction of the total gate capacitance due to the Cinv in the advanced gate stacks scaled down to 0.66-nm equivalent oxide thickness. The influence of the elementary composition, the physical thickness, and the interface layer on a scaling loss due to the Cinv is experimentally evaluated. [ABSTRACT FROM AUTHOR]

The inversion-layer capacitance Cinv of electrons in high-k/metal gate stacks (HKMGs) is studied theoretically and experimentally from the viewpoint of the penetration of electrons into the dielectrics. The numerical calculation of Cinv in the dielectric/substrate bilayer structure has clarified the influence of penetration on Cinv. Cinv in an HKMG is evaluated experimentally and is compared with the computational predictions in terms of the dependence on the dielectric boundary and the silicon crystal orientation. The consistency of the experiment and the calculation is the first evidence for the considerable modulation of Cinv due to penetration in the actual HKMG. Moreover, the dependence of Cinv on substrate biasing is investigated. The detailed analysis of Cinv in the system where the confinement of the inversion layer is intentionally changed has led to a further understanding of Cinv determined by penetration. [ABSTRACT FROM PUBLISHER]

In this letter, we investigated a dominant mechanism for leakage reduction by the incorporation of La in a \HfO2\/SiO2 gate stack. We compared the experimental data for the leakage current for the La-doped \HfO2 \/SiO2 gate stack and the calculation for tunnel current through the gate stack, assuming that the La-induced dipole increases the barrier height of \HfO2 for electrons from the substrate. The agreement between the experimental data and calculated values strongly suggests that the main cause for leakage reduction is the effective barrier height modulation induced by the interface dipole. [ABSTRACT FROM AUTHOR]

Strained-silicon-on-insulator (SSOI) undoped-body high-\kappa/metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e., LGATE\sim\!\!\25\ nm and a contacted gate pitch of 130 nm) were fabricated using a gate-first flow. A “long and narrow” fin layout (i.e., fin length \sim\!\!\1\ \mu\m) was leveraged to preserve uniaxial tensile strain in the transistors. These devices exhibit drive currents suitable for high-performance logic technology. The change in the slope of RON - LGATE\ (\rm dRON/\dLGATE), transconductance GMSAT, and injection velocity (vinj) measurements indicate a \sim15% mobility-induced ION enhancement with SSOI relative to SOI nFinFETs at ultrashort gate lengths. Raman measurements conducted on SSOI substrates after fin formation demonstrate the preservation of \sim1.3-GPa uniaxial tensile strain even after 1100 ^\circ\C annealing. [ABSTRACT FROM AUTHOR]