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Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) transistors exemplify the fundamental tradeoff between desirable high mobility and undesirable leakage current due to the small effective mass and bandgap. To understand leakage current limits in high-speed CNT transistors, electrical bandgaps are extracted on 12 single-CNT top-gate MOSFETs from the energy gap between thermionic emission and band-to-band tunneling (BTBT) at 10 K. At 300 K the minimum IOFF at 0.5 V VDS is analyzed as a function of bandgap between 0.96 eV and 0.43 eV with IOFF-MINfrom 0.2 pA/CNT to 15 nA/CNT. NEGF simulation validates the bandgap extraction methodology and reproduces the experimental MOSFET IOFF-MIN data. A TCAD model calibrated to this work’s leakage data projects the accessible ION-IOFF design space bounded by CNT bandgap, indicating EG > 0.65 eV (dCNT < 1.3 nm) is needed to achieve 100 nA/ $\mu \text{m}$ at 0.5 V VDD and 250 CNT/ $\mu \text{m}$ for channel length above 20 nm. An EG of 1.06 eV (dCNT = 0.8 nm) can deliver $2750\times $ tunable range of IOFF by adjusting VT, which exceeds the $400\times $ tunable range of IOFF used in Si CMOS platform technologies. [ABSTRACT FROM AUTHOR]

Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency of abundant-data applications 1,000-fold by using new logic and memory technologies, 3D integration with fine-grained connectivity, and new architectures for computation immersed in memory. [ABSTRACT FROM AUTHOR]

Nanoelectronics comprises a variety of devices whose electrical properties are more complex as compared to CMOS, thus enabling new computational paradigms. The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and high-performance circuit design. Within this space, we analyze a set of emerging technologies characterized by a similar computational abstraction at the design level, i.e., a binary comparator or a majority voter. We demonstrate that new logic synthesis techniques, natively supporting this abstraction, are the technology enablers. We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to both evaluate emerging technologies and to achieve the best results in terms of area, power and performance. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100\boldsymbol \times faster than existing approaches and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with ≤5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints. [ABSTRACT FROM PUBLISHER]

This paper describes the improvement of pull-in stability, contact properties, and reliability of laterally actuated nanoelectromechanical relays by partitioning the mechanical and electrostatic domains in the relay structure. Separation of the two physics allows us to individually optimize the structural stiffness and the actuation voltage to increase the contact pressure and reduce the ON-state resistance without applying excessive drain voltage. The devices can tolerate more than 200% overdrive gate voltage, resulting in near 100% increase in contact force, and reducing the contact resistance from $\sim 10$ G $\Omega $ to $\sim 23$ K $\Omega $ . For a given overall device dimension, tailoring the mechanical and electrostatic elements independently also enables us to control the pull-in and pull-out voltages, which have different design requirements for different applications. The measurement results show that the pull-in/pull-out hysteresis could vary between 30% and 60% of the actuation (pull-in) voltage. Increasing the mechanical force without affecting the device actuation voltage improves the relay reliability by reducing the possibility of failure due to source–drain stiction when the relay is switched ON. As a proof of concept, mechanical relays are fabricated using polycrystalline silicon coated by a titanium nitride layer deposited via plasma enhanced atomic layer deposition. [2014-0018] [ABSTRACT FROM AUTHOR]

Low-power applications, such as sensing, are becoming increasingly important and demanding in terms of minimizing energy consumption, driving the search for new and innovative interface architectures and technologies. Carbon nanotube FETs (CNFETs) are excellent candidates for further energy reduction, as CNFET-based digital circuits are projected to achieve an order of magnitude improvement in energy-delay product compared with silicon-CMOS at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to imperfections and variations such as those induced by mispositioned and metallic CNTs. These substantial imperfections and variations have prevented the demonstration of complex CNFET circuits until now. This paper presents the first demonstration of a subsystem, which is a complete capacitive sensor interface circuit, implemented entirely using CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This is made possible by: 1) a digitally oriented interface architecture and 2) the imperfection-immune design paradigm, which combines design and processing techniques to successfully overcome CNT imperfections and variations. In addition to electrical measurements, we demonstrate correct operation of our CNFET circuitry by interfacing it with a sensor used to control a handshaking robot. [ABSTRACT FROM AUTHOR]

Laterally actuated polycrystalline silicon nanoelectromechanical (NEM) relays with enhanced electrical properties are presented. Due to surface oxidation of polysilicon in room ambient conditions, the relays have a high contact resistance (>1\ \G\Omega) that requires high drain bias (3–5 V) to break through. The addition of a platinum sidewall coating reduces the on-resistance and the required drain bias to as low as 3 \k\Omega and 0.1 V, respectively. The platinum coating's stability is demonstrated by two tests: first, a contact-and-hold test where the relay passes current (\sim\!\! 1\ \mu\A) for up to 155 min and, second, a hot cycling test where the relay survives for over 10^8\ \cycles. The NEMS relays are simulated using finite-element analysis, and the models are verified against experimental tests. Furthermore, the relays are configured and tested as a 2 : 1 multiplexer to show their potential as a digital logic component. \hfill[2012-0077] [ABSTRACT FROM AUTHOR]

We present a new very large scale integration (VLSI)-compatible metallic carbon nanotube (CNT) removal technique called VLSI-compatible metallic CNT removal (VMR) that overcomes challenges of existing techniques by combining design and processing to create carbon nanotube field effect transistors (CNFET) circuits immune to CNT imperfections such as metallic and mispositioned CNTs. Using VMR, we experimentally demonstrate combinational and sequential CNFET logic circuits such as half-adder sum generators and D-latches. These circuits form the fundamental building blocks of VLSI digital systems. [ABSTRACT FROM PUBLISHER]