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The corrugated p-base (CB) structure has been acknowledged as an effective method to improve the maximum controllable current (MCC) of asymmetric integrated gate-commutated thyristor (IGCT), but never clarified in symmetrical devices such as reverse blocking IGCT (RB-IGCT). This study focuses on the influence of the CB structure on the MCC and the failure mechanism of RB-IGCT. First of all, by employing the CB structure in the RB-IGCT samples, it is verified that the CB structure can improve MCC of the symmetrical devices by more than 50%, no matter under high or low dc-link voltages. Moreover, regarding the scenario under the high dc-link voltage, the effect of the CB structure on the dynamic avalanche is analyzed via simulation, and the improvement of MCC and the positive trend of MCC upon temperature are further clarified. As to the scenario under the low dc-link voltage, distinct failure phenomenon and negative temperature dependence of MCC are observed evidentially on the symmetric devices with CB structure. To explain these failure characteristics that are conflicting with the well-acknowledged dynamic avalanche failure, a novel failure mode named cathode retrigger failure is proposed in this study. It is believed that this study not only deciphers the fundamental mechanisms of the CB structure in RB-IGCT, but also provides practical strategy to optimize the symmetric IGCT devices. [ABSTRACT FROM AUTHOR]

Compared with integrated gate commutated thyristors (GCTs), an integrated emitter turn-off thyristor (IETO) has a potential of higher turn-off current capability and requires lower power consumption for gate driver units, which is more suitable for high-power applications. Thus, in this article, an advanced design of 4-in IETO was presented. To reduce the gate commutation impedance and enhance the turn-off current, the turn-off circuit with low impedance DirectFETs was integrated into the housing. And the housing structure was carefully designed to provide a compact current commutation path. Then, a 4-in IETO prototype based on a 4.5 kV/5 kA GCT wafer was developed. Experimental results show that its maximum turn-off current was over 8.1 kA with an extremely short commutation time of 130 ns. And the total commutation inductance was only 0.38 nH. Additionally, the thermal and mechanical characteristics of the housing were also taken into consideration during design and verified by the thermal simulation and mechanical stress test. Consequently, according to this article, IETO has the potential to be a competitive device in high-power applications in the near future. [ABSTRACT FROM AUTHOR]

Gate electrode inductance is a key factor for the controllable current capacity of unity-gain turn-off devices. However, the precise and credible measurement of this nH-level inductance is very difficult due to the compact structure of housing package. In this article, a precise measurement methodology of nH-level gate electrode inductance based on calculation-error-free algorithm for unity-gain turn-off devices is proposed. First, the turn-off process was modeled and discussed. Based on the feature of different stages, a customized extraction method is proposed for nH-level inductance measurement with ultrahigh accuracy. Then, a gate current measurement method for separate cathode rings with minimum inductance introduction was invented and discussed. After careful measurement and calculation, the gate electrode inductance for each region was derived and the abrupt change in gate contact region was observed and analyzed. The inductances measured in this article can be further utilized for housing structure optimization and lateral arrangement of segments on unity-gain turn-off chips. [ABSTRACT FROM AUTHOR]

The integrity of housing and feature of short circuit is hardly guaranteed for traditional power devices under overvoltage breakdown with following high surge energy. Thus, extra bypass thyristor is needed to achieve stable overvoltage bypass protection for submodules in modular multilevel converters at present. In this article, a novel controlled punch-through IGCT (CP-IGCT) is presented. Based on the punch-through breakdown principle instead of avalanche breakdown principle, the device can achieve breakdown at design voltage with uniformity, thermal stability, and robust package rupture-resilience. As a consequence, no extra sacrificial device is necessary. The fabricated sample proves a stable breakdown at 4000 V and a robust short-circuit feature after energy release of a 18 mF capacitor under 4500 V. [ABSTRACT FROM AUTHOR]

The turn-off capability test for the single cell of power devices is of great significance to both the safe operation assurance and the destruction mechanism research. However, with present techniques, the device under test is supposed to be destroyed once the turn-off fault occurs. In this article, a robust nondestructive test scheme based on the multistage anode voltage detection for 4500 V single-cell turn-off capability of press-packed devices is proposed. Based on the proposed scheme, a single cell of IGCT is tested until a fault occurs. The result proves that a total bypass time is less than 100 ns for the 2200 V/5 A turn-off fault, and thus, the aim of nondestructive tests can be achieved with the proposed method. [ABSTRACT FROM AUTHOR]

The performance of solid-state dc circuit breaker (SS-DCCB) is mainly determined by the on-state feature of power device. In this article, an optimized low on-state voltage integrated gate-commutated thyristor (LO-IGCT) for SS-DCCB is developed. First, the impacts of device parameters, including base length, carrier lifetime, and emitter injection efficiencies, on on-state voltage are presented. The boundary conditions raised by blocking voltage and safe operation area (SOA) are analyzed. Based on that, a three-step blocking-SOA-emitter optimization routine is proposed. Then, the optimization methodology for doping profiles in different regions, especially in n-drift, n buffer, p+ base, n+ emitter, and p+ emitter regions, is presented. The optimal values are derived with theoretical deduction or numerical calculation. After that, based the optimization result, samples of LO-IGCTs are fabricated and tested. The fabricated LO-IGCT sample shows a blocking voltage capability over 4500 V and an on-state voltage of 1.11 V at the current of 2000 A. The commercialized IGCT and IGBT optimized for high-frequency applications exhibits 1.23 and 1.85 times the on-state voltage under the same test configuration. [ABSTRACT FROM AUTHOR]

Turn-off capability of integrated gate-commutated thyristor is highly dependent on the commutation capability of its gate driver unit (GDU). To enhance it, stray impedance is the crucial limitation, which has not been obtained accurately before. Thus, in this paper, acquisition method of impedance based on experimental measurements was carefully analyzed, including electrolytic and ceramic capacitors, mosfets, printed circuit board, and GCT housing. And each part of stray impedance was obtained based on a series of experiments with 6-inch GCTs and two types of conventional GDUs. To further enhance commutation speed, an improved GDU was developed, reducing the total stray inductance from 0.395 to 0.037 nH, stray resistance from 0.444 to 0.227 mΩ. An extremely high current of 12.5 kA was successfully turned off, which is the maximum turn-off current level so far. Besides, the maximum commutation capability was tested as over 17 kA. Consequently, no further optimization of GDU is necessary. However, there was still about 1.0 nH existing inside the GCT housing we used. A novel housing with lower stray inductance is expected for higher commutation speed in the future. [ABSTRACT FROM AUTHOR]

DC circuit breakers (DCBs) are crucial components in dc power systems. The ultralow operating frequency of the DCBs enables the use of gate-commutated thyristors (GCTs) in the DCBs. This paper proposed a 6-in dual-gate ring commutated thyristor (DGRCT) for the DCB applications. The wafer and package designs of the DGRCT are first presented and discussed, analyzing the principles of the current commutation in the DGRCTs. Subsequently, a DGRCT prototype is fabricated, and experiments are conducted to measure the inductance along the current commutation loop (CCL) of the prototype DGRCT. Finally, a large current interruption experiment is conducted. The results show that the prototype DGRCT reduced the parasitic inductance within the CCL by at least 20% compared to conventional GCTs with single-gate ring design. The maximum current interruption capacity of the prototype DGRCT is no less than 12 kA at T = 300 K, which approaches the fault current interruption requirement in DCB applications for both transmission and distribution levels of dc power systems. [ABSTRACT FROM AUTHOR]

Gate-commutated thyristors (GCTs) are subject to uneven impedances along the current path from GCT circles to the gate contact, which leads to current redistribution between the GCT circles during turn-off. The current redistribution inequality significantly limits the maximum controllable current of GCTs. This paper presents an optimization method for GCT cell arrangement design to minimize the current redistribution inequality. First, the whole GCT wafer model is applied to calculate the inequality of the current redistribution. The whole GCT wafer model is a hybrid model built by physics-based GCT cell models connected with lumped parameter models. The GCT cell models applied here are improved compact models with multiple physical mechanisms, while the lumped parameter models represent the uneven impedances of the GCT circles along the GCT wafer. In order to measure those impedances, a set of physical concentric contact rings are developed. Finally, the Tabu search (TS), a heuristic algorithm, is applied to optimize the GCT cell arrangement. Using the optimization method based on TS, an optimized set of GCT cell numbers for a 4-in GCT wafer is obtained, reducing the inequality of the current redistribution by 20%. [ABSTRACT FROM AUTHOR]