Search

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low-k (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted. [ABSTRACT FROM AUTHOR]

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer. [ABSTRACT FROM AUTHOR]

In this paper, we propose an analytical model to accurately evaluate the parasitic capacitances of an advanced 7-nm-node multigate device structure: 1) FinFET on Silicon On Insulator (SOI) (FFSOI) and 2) stacked nanowire on SOI (SNWSOI). Our model, validated through 3-D TCAD simulations, accounts for gate contact, advanced process bricks, such as gate last, BAR contact, and low- $k$ spacer, but also multilayer dielectric by introducing an equivalent permittivity. Finally, FFSOI and SNWSOI architectures are compared from this parasitic capacitance point of view. [ABSTRACT FROM AUTHOR]