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In the back-end-of-line double-gate (DG) amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs), the linearity of top-gate voltage (${V}_{TG}$)-swept threshold voltage (${V}_{T,TG}$) with back-gate voltage (${V}_{BG}$) is essential. In this work, the influence of positive bias stress (PBS) condition on both $\beta = \partial {V}_{T,TG}/\partial {V}_{BG}$ and $\Delta \beta = \partial \Delta {V}_{T,TG}/\partial {V}_{BG}$ is investigated in DG a-IGZO TFTs, using the subgap density-of-states (DOS) extracted before and after PBS. While $\Delta \beta $ remains almost constant in the PBS condition of ${V}_{TG}/{V}_{BG}=30$ /-30 V, the ${V}_{TG}={V}_{BG}=30$ V condition shows the complicated nonlinear relationship between $\Delta {V}_{T,TG}$ and ${V}_{BG}$. It is found that $\lambda = \delta \Delta \beta /\delta {V}_{BG}$ , as the parametric indicator describing the PBS-induced degradation of linearity for the ${V}_{BG}$ -controlled ${V}_{T,TG}$ , is $\times 7$ larger (less linear) at ${V}_{TG}={V}_{BG}=30$ V than at ${V}_{TG}/{V}_{BG}=30$ /−30 V. The origin of this non-linearity is comprehensively explained based on the model of the excessive oxygen-related defect creation resulting from broken peroxy linkage. Our result suggests that the ${V}_{TG}/{V}_{BG}=30$ /−30 V is a more advantageous condition in the viewpoint of the $\Delta {V}_{T,TG}$ linear with ${V}_{BG}$ , in comparison with ${V}_{TG}={V}_{BG}=30$ V. [ABSTRACT FROM AUTHOR]

This study proposes a model of mobility and negative bias stress stability degradation mechanism of zinc oxynitride (ZnON) thin-film transistors (TFTs) with various anion compositions. The subgap density of states (DOS) for ZnON TFTs were extracted using monochromatic photonic capacitance–voltage measurement. The extracted subgap DOS indicated an additional nitrogen-related subgap peak was observed in ZnON TFTs with an excessive nitrogen condition, which might originate from a nitrogen divacancy formation. Furthermore, the shifted threshold voltage components after the bias stress test were quantitatively divided as subgap DOS and interface trapping. [ABSTRACT FROM AUTHOR]

In amorphous oxide semiconductors, hydrogen-related defects have been unable to be observed from the electrical characteristics of thin-film transistors (TFTs) in comparison to oxygen-related defects. Here, the hydrogen-related defect is observed as the Gaussian distributed density of states (DoS) in EC − 0.6 eV level by using the photoresponse of C-V characteristics in In-Ga-Zn-O (IGZO) TFTs. Coupled with X-ray photoelectron spectroscopy (XPS), it is identified as hydroxide ion (OH−), which both passivates oxygen vacancy defects and supplies the carriers as shallow donors. Furthermore, the evolution of DoS under positive bias stress and its origin are comparatively investigated for IGZO TFTs with three types of gate insulators (GIs), such as low-temperature atomic layered deposited Al2O3, thermally grown SiO2, and double-layered GIs. [ABSTRACT FROM AUTHOR]

In this study, silicon nanowire (SiNW) FET-based and SiNW tunnel FET (TFET)-based biosensors are co-integrated with CMOS circuits by using top-down approached and CMOS-compatible back-end process simultaneously. The possibility of multiplexed sensing is verified with the fabricated FET and TFET biosensors. For multiplexed-sensing, two separate sensing materials which react with two distinct bio-targets are formed by partially capping the gold on SiO2 film through a lift-off process. Then two bio-receptors which selectively combine to the gold and the SiO2 are deposited. After the reaction of each biomolecule to each receptor, the changes of saturation and gate-induced-drain-leakage (GIDL) currents are monitored in the FET sensor. It is experimentally confirmed that two different biomolecules are independently detectable by the changes of the saturation and the GIDL currents in the FET sensor. To solve the dependence of the gold formation position on the sensitivity as well as the large current difference between the saturation and the GIDL currents, we demonstrated the TFET biosensor which uses the changes of tunneling and ambipolar currents generated in the source and the drain end. As a result, it is clearly revealed that two different biomolecules can be detected without interference, regardless of the position of the gold layer by the changes of the tunneling and the ambipolar currents with almost equivalent sensing current level. [ABSTRACT FROM AUTHOR]

Amorphous indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) have shown significant potential for application in transparent and flexible electronic devices. However, the source and drain (S/D) electrodes of IGZO TFTs with indium tin oxide (ITO) thin films can cause Schottky-like behavior in the output characteristics owing to the formation of a potential barrier between the IGZO and ITO thin films. In this study, we designed and fabricated TFTs by applying a novel ITO S/D electrode layer (375 nm) with co-sputtered IGZO and ITO thin films (125 nm) deposited at room temperature. The proposed TFT exhibits superior electric characteristics ($\mu _{\text {sat}} =35.4$ cm2/Vs) compared to those of TFTs with conventional ITO electrodes ($\mu _{\text {sat}} =9.1$ cm2/Vs) owing to its lower contact and channel resistance and the generation of a surface reaction between S/D and channel layers, creating additional oxygen vacancies at the IGZO channel region. The proposed S/D electrode could be fabricated on a glass substrate at low temperatures (below 200 °C). The excellent electrical properties of the proposed IGZO TFT are expected to promote the application of TFTs in advanced displays. [ABSTRACT FROM AUTHOR]

An extraction technique for flat band voltage (${V}_{\textit {FB}}$) in an amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) using the frequency-independent ${C}-{V}$ relationship which is taken from the measured multi-frequency ${C}-{V}$ characteristics, is proposed. The proposed method comprises the consideration of multiple physical parameters for accurate ${V}_{\textit {FB}}$ extraction, including the sub-gap density of states, doping concentration, gate oxide capacitance, and series resistance. The method was verified by comparing both the measured current–voltage characteristics and the extracted ${V}_{\textit {FB}}$ value with the technology computer-aided design simulation results. Moreover, we confirmed the versatility of the method by extracting ${V}_{\textit {FB}}$ from devices with different oxygen contents. The proposed physical-based technique showed better accuracy and compatibility with amorphous oxide semiconductor (AOS) TFTs compared with classical empirically based methods. We believe that our technique is useful for the experimental design and optimization of the gate metal-dielectric-AOS stack for high-performance AOS TFTs. [ABSTRACT FROM AUTHOR]

We report a novel technique for separating the parasitic source (${R} _{\text {S}}$) and drain (${R} _{\text {D}}$) resistances in MISFETs using the open drain and the open source configurations based on an alternating-current(AC) signal. We conducted impedance analysis for the AC signal in the open drain for ${R} _{\text {S}}$ and the open source configuration for ${R} _{\text {D}}$. The proposed technique is independent of the I-V equation of MISFETs with various influencing parameters for separate extraction of ${R} _{\text {S}}$ and ${R} _{\text {D}}$ through the physics-based equivalent circuit of MISFETs. So the proposed technique is applicable to every single device as long as the device is an insulated gate MISFET structure, regardless of the presence or absence of the body terminal. This technique is applied to amorphous oxide semiconductor thin-film transistors with the gate length $= 10~\mu \text{m}$ without the body contact. As a result, parasitic resistances were separately extracted to be ${R} _{\text {S}} =2.1\,\,\text{k}\Omega $ , ${R} _{\text {D}} =1.7\,\,\text{k}\Omega $ for ${W} = 600~\mu \text{m}$ , ${R} _{\text {S}} = {R} _{\text {D}} =1.1\,\,\text{k}\Omega $ for ${W} = 1000~\mu \text{m}$ , and ${R} _{\text {S}} = {R} _{\text {D}} =0.6\,\,\text{k}\Omega $ for ${W} = 2000~\mu \text{m}$ independent of gate bias. [ABSTRACT FROM AUTHOR]

In this letter, the effects of negative and positive bias stability with respect to the anion composition of Zn–O–N thin-film transistors were researched. In the positive bias stress tests, the threshold voltage shift was high for ZnON devices with high nitrogen composition. In contrast to this, the negative bias stress test results have smaller $\Delta ~\text{V}_{th}$ values when nitrogen composition in ZnON was low. This different degradation behavior of ZnON for thin-film transistors was analyzed by using the subgap density of states which were obtained from monochromatic photonic capacitance-voltage measurement. [ABSTRACT FROM AUTHOR]

The instability induced under positive gate-bias stress (PBS) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with self-aligned top-gate coplanar structure is investigated under the threshold-voltage $({V}_{T})$ compensated pixel scheme in the backplane of organic light-emitting diode displays and compared with that under a constant-PBS scheme. Based on the investigation, which combines the extraction of density of states, the decomposition of ${V}_{T}$ shift ($\Delta {V}_{T}$), and technology computer-aided design, the unreleased electric field across the gate insulator (GI) and the maintained electron concentration are observed under the ${V}_{T}$ -compensated PBS condition. Indeed, the main difference between the two schemes originates from increasingly activated electron trapping within the GI deep-level traps and from the excessive oxygen-related peroxide bond-breaking in the a-IGZO-active film, i.e., O22− + $2 {e}^{-} \to$ O2− + O2−. Although the latter is quantitatively much smaller than the former, the two mechanisms are closely related to each other and should be jointly optimized. This is because a large amount of oxygen interstitials can generate a high density of GI electron traps. Since the GI deep-level trapping results in noticeable $\Delta {V}_{T}$ with an increase in PBS time, our results suggest that the $\Delta {V}_{T}$ should be seriously underestimated with respect to either the estimation of pixel lifetime or the assessment of ${V}_{T}$ -compensated pixel-circuit schemes, if the reliability/acceleration test relies only on the constant-PBS-based single-TFT device test. [ABSTRACT FROM AUTHOR]

A temperature (${T}$) sensor based on an amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) is demonstrated and its performance is analyzed quantitatively. The performance analysis includes the influences of the gate-to-source bias (${V}_{{GS}}$) and oxygen content in IGZO on the mobility ($\mu $), threshold voltage (${V}_{T}$), and drain-to-source current (${I}_{\text {DS}}$) of TFTs. The linearity and sensitivity of the sensor are found to improve with decreasing oxygen content and increasing ${V}_{\text {GS}}$ , because $\partial {I}_{\text {DS}}/\partial {T}$ is quantitatively dominated by $\mu $ and (${V}_{\text {GS}} -{V}_{\text {T}}$) rather than by $\partial \mu /\partial {T}$ and $- \partial {V}_{\text {T}}/\partial {T}$. This indicates that the IGZO TFT has great potential as a temperature sensor in terms of immunity in device/process variation. A sensitivity of 125 nA/K with 1.55 K resolution over a temperature range of 303–373 K was successfully demonstrated in low oxygen and ${V}_{\text {GS}}= {9}$ V conditions. [ABSTRACT FROM AUTHOR]

Degradation on the current saturation of the output characteristics in amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors with the bottom-gate structure is investigated. As the drain-to-source voltage (${V}_{\textsf {DS}}$) increases at a fixed gate-to-source voltage (${V}_{\textsf {GS}}$), the current from drain to source (${I}_{\textsf {DS}}$) becomes nonsaturated and increases due to the mobility enhancement and ${I}_{\textsf {DS}}$ also decreases again due to the electron trapping into the gate insulator and/or an interface, which occurs mainly at the channel edge near a drain. Analysis is validated by using the pulsed ${I}_{\textsf {DS}}$ – ${V}_{\textsf {DS}}$ measurement. Nonsaturated current is attributed to the Joule heating-assisted mobility enhancement and the thermally activated electron trapping, which is the reason why the nonsaturation becomes more prominent as the IGZO active thin film becomes thinner. Furthermore, it is found that the rate of the increased ${I}_{\textsf {DS}}$ per increasing ${V}_{\textsf {DS}}$ gets higher as either the channel width (${W}$) increases or the channel length (${L}$) decreases; whereas, the rate of the decreased ${I}_{\textsf {DS}}$ per increasing ${V}_{\textsf {DS}}$ becomes higher as the device size, i.e., ${W}\times {L}$ , increases. The former is well correlated with Joule heating while the latter with the self-heating-assisted electron trapping due to a total heat accumulated in an active layer. [ABSTRACT FROM AUTHOR]

In this paper, we fabricated In0.53Ga0.47As-on insulator (OI) MOSFETs on Si substrates with different doping types to mimic ground plane doping using direct wafer bonding and epitaxial lift-off (ELO) techniques. We investigated the impact of doping types on the ground plane and the backgate biasing, which are important and preferable components in monolithic 3-D (M3D) integration, on the electrical properties of MOSFETs, such as the threshold voltage ( ${V} _{T}$ ) and the effective mobility ( $\mu _{\textsf {eff}}$ ). It was found that ${V} _{T}$ and $\mu _{\textsf {eff}}$ were significantly modulated by the backsubstrate doping and the backbiasing. These observations were explained by the change of carrier distributions, which were confirmed by technology computer-aided design simulation. Furthermore, we investigated the reusability of InP donor substrates for sequential epitaxial growth after ELO process toward a cost-effective M3D integration with the In0.53Ga0.47As channel. [ABSTRACT FROM AUTHOR]

The low-frequency noise (LFN) characteristics of a vertical pillar-type FET were investigated in order to observe the different influences of the source resistance ( RS) and the drain resistance ( RD) . Because of its inherent vertical channel structure, the RS and RD are inevitably different. To observe the effects of the asymmetric RS and RD on LFN, a forward mode (FM) and reverse mode (RM) of voltage sweep were used. In the RM, the correlated mobility fluctuation effect was higher and the power spectral density of resistance fluctuation ( S\mathrm{ RSD}) was lower than those in the FM. In addition, S\mathrm{ RSD} was correlated with the RS , but little with the RD . To suppress S\mathrm{ RSD} , it is important to minimize the RS . [ABSTRACT FROM AUTHOR]

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are investigated for a possible application to infrared (IR) photodetector through subgap density-of-states over the forbidden bandgap. The origin of the sub-bandgap( h\nu < E g) photo-response in a-IGZO TFTs is due to optically pumped electrons from the photo-responsive subgap states ( E C - E \textit {ph}{<}Et{<}EF) . Among the sub-bandgap lights, we investigate the reproducible IR photo-response in a-IGZO TFTs as a photodetector without the persistent photoconductivity (PPC) effect. In this letter, we characterize the IR photo-response mechanism through various optical and electrical measurements on the wavelength, optical power, bias-modulated quasi-Fermi level, and photo-responsive states. This result is expected to provide independent and/or integrated IR detector with transparent substrate combined with a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

We propose an experimental method to decompose the positive gate-bias stress (PBS)-induced threshold voltage shift ( \Delta V\mathsf {th}) of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) into the contributions of distinct degradation mechanisms. Top-gate self-aligned coplanar structure TFTs are used for this letter. Stress-time-divided measurements, which combine the subgap density-of-states (DOS) extraction and the analysis on recovery characteristics, are performed to separate the \Delta V\mathsf {th} components. Change in excess oxygen ( \textO\mathsf {ex}) -related DOS is clearly observed, and \Delta V\mathsf {th} by PBS is quantitatively decomposed into the contributions of the active \textO\mathsf {ex} , and the deep and shallow gate insulator traps. The quantitative decomposition of PBS-induced \Delta V\mathsf {th} provides physical insight and key guidelines for PBS stability optimization of a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

We report a model for the band-bending effect (BBE) for improved extraction of the subgap density-of-states (DOS) in amorphous semiconductor thin-film transistors (TFTs). In previous works, the potential ( \psi ( {x} )) across the amorphous active layer was assumed to be the same as the surface potential ( \psi _{\mathrm {S}} ) over the active layer without the BBE. Due to the distributed DOS ( g ( E )) over the bandgap and the modulation of the quasi-Fermi level ( E F(x, V{\textsf {GS}}) ) by the gate bias, the non-uniform potential distribution should be considered in the characterization of DOS. We propose an empirical quadratic potential model ( $\psi $ ( $x,V_{{\textsf {GS}}})=\psi _{S} (V {\textsf {GS}})(1-{x/t}{\textsf {IGZO}})^{2}) for the BBE and extract a corrected distribution of DOS [ {g}(\textsf {E}) ]. We applied the BBE model to the amorphous indium–gallium–zinc oxide TFTs through the differential ideality factor technique. We extracted a corrected DOS as a superposition of two exponential functions with tail and deep state \vphantom \int densities ( N {To} =\textsf {8.8} \times \textsf {10}^{{\textsf {17}}} eV ^-1 cm ^-3 , and N {Do} = \textsf {9} \times \textsf {10}^{{\textsf {16}}} eV ^-1 cm ^-3) at the tail and deep state characteristic energy ( kTT = \textsf {18} meV and kTD = \textsf {280} meV), respectively. We confirmed the potential model and extracted DOS parameters by the TCAD simulation. [ABSTRACT FROM PUBLISHER]

The memristor ratioed logic (MRL)-based NAND operation is demonstrated using a combination of two Ag/ $\gamma $ -Fe2O3 nanoparticles assembly/Pt memristors in series with one CMOS inverter. This letter finds the MRL operational frequency to be restricted due to an inconsistency between SET and RESET and by an imbalance of the resistance between the two memristors. It is also shown that optical tuning resistance is a promising technique for use in improving the operational frequency of the MRL operation. MRL-based NAND logic demonstrated in this letter manifests itself as a potential candidate for memristor-based logic compatible with CMOS digital/analog circuitry. [ABSTRACT FROM PUBLISHER]

The Internet-of-Things (IoT) provides a great opportunity to many vertical industries because IoT interconnects various devices such as sensors and actuators and collects/processes data from them in order to improve services and reduce costs. As there exists many IoT technologies in the market, global standards and interworking mechanisms are critical to the success of the IoT. This article introduces standardized interworking interfaces and procedures based on oneM2M global standards, and tests them through use cases involving multiple IoT service platforms. The interworking involves smart city applications/services running on multiple IoT service layer platforms interoperating with each other. The main purpose of the interworking experiment is to show how machine-to-machine (M2M)/IoT service providers are using oneM2M compliant service layer platforms to deliver services more efficiently across multiple technology domains such as smart city. Because the deployment configurations of this interworking experiment span multiple domains, and the IoT devices and platforms are from different companies, we believe that this interworking experiment clearly proves that global IoT standards specifications can foster implementations of a service layer that enables services and interoperability between devices/device networks and cloudbased applications. [ABSTRACT FROM PUBLISHER]

Thin-film transistors using In–Ga–Zn–O (IGZO) semiconductors were evaluated under positive bias stress with different gate and drain voltages ( V\textrm {GS} and V\textrm {DS} , respectively). The transfer characteristics with respect to stress time were examined, focusing on the threshold voltage ( VT ) values obtained when the source and drain electrodes are interchanged during readout (forward and reverse V\textrm {DS} sweep). The VT values shift toward either negative or positive values during stress, while transitions from negative to positive shifts are also observed. The negative VT shift under positive bias stress is interpreted to occur by the generation of donor-like states related to ionized oxygen vacancies. On the other hand, positive VT shifts result from the trapping of electrons near the IGZO/gate insulator interface. The transitions from negative to positive VT shift are believed to result from the local electron trapping mechanism that gradually takes over donor-like state creation. From the experimental results and TCAD device simulation, it is suggested that a competition occurs between donor-like state creation and electron trapping. The relative magnitudes of the V\textrm {GS} and V\textrm {DS} fields determine which mechanism dominates, providing an analytical insight for the design of stable devices for driving transistors in AMOLED backplanes. [ABSTRACT FROM AUTHOR]

Bias-dependent effective channel length [ L\mathrm {eff}(VG)] is empirically modeled with a channel conduction factor [ \alpha (VG)] for a consistent capacitance–voltage ( C – V ) characterization of the intrinsic subgap density of states (DOS) over the bandgap with the sub-bandgap photoresponsive C – V through the product of the empirical channel conduction factor [ L_{m}) . We confirm that the gate bias-dependent channel conduction effect is significant in the subgap DOS far from the conduction band edge ( E_{C})$ due to the low conductivity of the channel under subthreshold bias. [ABSTRACT FROM AUTHOR]

We found that field-effect mobility, which had been widely used in the evaluation of the mobility of an amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) failed to describe the effect of mobility on propagation delay ( tPD ) in an a-IGZO TFT-based circuit, and also proposed an extraction technique for the tPD -correlated mobility ( $\mu _{{{t_{\rm PD}}}}$ ) considering both the subgap density-of-states and the voltage-dependent charge density. It is verified that the proposed $\mu _{{{t_{\rm PD}}}}$ is the best correlated with the measured tPD in IGZO TFT-based inverters other than various mobilities in the literature. Our results have revealed that it is possible to predict tPD only with the measured current–voltage characteristic of the a-IGZO TFT without measuring tPD in IGZO-based circuits. [ABSTRACT FROM AUTHOR]

We report a technique for separate extraction of extrinsic source/drain (S/D) resistances ( R\mathrm {Se}/R\mathrm {De}) and gate bias ( $V_{{\mathbf {GS}}}) -dependent but channel length (L)-independent intrinsic source/drain ( R\mathrm {Si}/R\mathrm {Di}) resistances for the overlap region in MOSFETs. For extraction of the overlap length ( L\mathrm {ov}) in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance–voltage ( $C_{{{G-S}}}$ , $C_{{{G-D}}}) characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract \mathrmV\mathrm {\mathbf {GS}} -dependent R\mathrm {\mathbf {Si}}= 0.9{\sim }3.7~\Omega and R\mathrm {\mathbf {Di}}= 1.0{\sim }3.9~\Omega in an n-channel MOSFET with W=140~\mu m and L=0.35 ~\mu m. In addition, V\mathrm {\mathbf {GS}} - and L -independent extrinsic S/D resistances are separately extracted to be R\mathrm {Se}=5.1~\Omega and R\mathrm {De}= 5.0~\Omega , respectively. [ABSTRACT FROM AUTHOR]

A sub-bandgap optoelectronic differential ideality factor technique is proposed for extraction of the intrinsic density-of-states (DOS) over the bandgap in amorphous semiconductor thin-film transistors (TFTs). In the proposed technique, the gate bias-dependent differential change in the difference of ideality factors ( \(d\Delta \eta (V_{\mathrm {GS}})/dV_{\mathrm {GS}}\) ) between dark and sub-bandgap photonic excitation condition is employed. With the sub-bandgap photons ( \(h\nu < E_{g}\) ), the photonic excitation of electrons is confined only from the localized DOS over the bandgap. We applied the proposed technique to a-InGaZnO TFTs with \(W/L = 50/25 \mu \) m/ \(\mu \) m and extracted the energy distribution of the intrinsic DOS for the localized states over the bandgap. [ABSTRACT FROM PUBLISHER]

A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW. [ABSTRACT FROM PUBLISHER]

A universal drain current model for multiple-gate field-effect transistors (FETs) (Mug-FETs) is proposed. In Part I, a universal charge model was derived using the arbitrary potential method. Using this charge model, Pao–Sah's integral is analytically carried out by approximating its integrand. The model describes both the subthreshold inversion for undoped FETs and the effects of finite doping density in the channel. With an explicit and continuous expression, the proposed drain current model covers all regions of device operation: subthreshold, linear, and saturation. The accuracy from the proposed model is comparable with that from well-known previous models for double-gate (DG) and cylindrical gate-all-around (Cy-GAA) FETs with an undoped channel. In addition, the model shows good agreement with 2-D and 3-D numerical simulations for doped-channel multiple-gate structures such as single-gate, DG, triple-gate, rectangular gate-all-around, and Cy-GAA FETs. The proposed model is well suited to be a core model for Mug-FETs due to its good computational efficiency and high accuracy; hence, it is useful for compact modeling. [ABSTRACT FROM PUBLISHER]

A universal core model for multiple-gate field-effect transistors (Mug-FETs) is proposed. The proposed charge and drain current models are presented in Parts I and II, respectively. It is first demonstrated that an exact potential profile in the entire channel is not necessary for the derivation of accurate charge models in inversion-mode FETs. With application of this new concept, a universal charge model is derived for Mug-FETs by assuming an arbitrary channel potential profile, which simplifies the mathematical formulation. Thereafter, using the Pao–Sah integral, a drain current model is obtained from the charge model of Part I. The proposed model can be expressed as an explicit and continuous form for all operation regimes; therefore, it is well suited for compact modeling to support fast circuit simulations. The model shows good agreement with 2-D and 3-D numerical simulations for several multiple-gate structures, such as single-gate, double-gate, triple-gate, rectangular gate-all-around, and cylindrical gate-all-around FETs. [ABSTRACT FROM PUBLISHER]

A compact model of quantum electron density at the subthreshold region is derived for junctionless (JL) double-gate (DG) FETs. The proposed quantum model is obtained under two different quantum confinement conditions. One is for a case of a thick channel and a heavily doped channel, where quantum confinement effects (QCEs) are modeled by a 1-D quantum harmonic oscillator. The other is for a case of a thin channel, where QCEs are modeled by the use of a 1-D quantum well surrounded by high potential barriers and an energy correction term coming from the depletion charge. It is shown that, regardless of the channel thickness, the quantum confinement is higher in JL than in inversion-mode (IM) DG FETs. However, for a thin channel, the quantum threshold voltage shift is less severe in JL than in IM DG FETs. The proposed model gives an analytical expression for the threshold voltage shift due to QCEs, which can be used as a quantum correction term for compact modeling. [ABSTRACT FROM AUTHOR]

A novel bias scheme is demonstrated for performance improvement of floating-body cell memory, particularly retention time. Its basic mechanism is based on carrier lifetime engineering, which takes advantage of generation lifetime that is longer than recombination lifetime. In addition, the proposed scheme is suitable for low-power operation; a high drain bias is unnecessary to generate excess carriers, which allows reliable endurance of up to \10^12 switching instances at 85 ^\circ\C. [ABSTRACT FROM PUBLISHER]

An underlap channel-embedded FET is proposed for electrical, label-free biosensor in both watery and dry environments, and current–voltage characteristics measured under each environment are compared. To investigate the effectiveness of the underlap device as a biosensor for both environments, antigen–antibody binding of an avian influenza (AI) is used. Antibody of AI binding on antigen-immobilized surface provides additional negative charge on underlap surface, and they give rise to channel potential increasing and result in drain current reduction. In this study, we have verified that the biosensor characteristics measured under dry environment is valid as much as they are valid for watery environment. [ABSTRACT FROM PUBLISHER]

A novel interface characterization technique is proposed to extract interface trap density Nit in fully depleted silicon-on-insulator MOSFETs. The proposed technique utilizes the temporal variation of the drain current, which is caused by the application of a single pulse to the gate in order to trigger charge pumping (CP). Vacant interface traps created as a result of recombination through the CP effect are gradually filled by carriers generated from a floating body (FB). By the characterization of this transient phenomenon, the interface trap density is directly extracted from FB devices without extra body contacts. [ABSTRACT FROM PUBLISHER]

A drain current model available for full-range operation is derived for long-channel double-gate junctionless transistors. Including dopant and mobile carrier charges, a continuous 1-D charge model is derived by extending the concept of parabolic potential approximation for the subthreshold and the linear regions. Based on the continuous charge model, the Pao–Sah integral is analytically carried out to obtain a continuous drain current model. The proposed model is appropriate for compact modeling, because it continuously captures the phenomenon of the bulk conduction mechanism in all regions of device operation, including the subthreshold, linear, and saturation regions. It is shown that the model is in complete agreement with the numerical simulations for crucial device parameters and all operational voltage ranges. [ABSTRACT FROM AUTHOR]

The energy distribution of interface traps is extracted using an optically assisted charge pumping (optical CP) technique. Optically generated majority carriers through light illumination enable the CP process even in a floating-body (FB) device without an extra body contact. With the use of square pulses at different rising and falling times and the proposed analytical model, the energy distribution of the interface traps is investigated via an optical CP technique. The optical CP technique is useful to extract the energy distribution of interface traps, as well as the interface-trap density in nanoscale FB devices. The data extracted by the optical CP is verified in a comparison with the data extracted by subthreshold-slope techniques. [ABSTRACT FROM PUBLISHER]

Label-free electrical detection of biomolecules is demonstrated with a double-gate (DG) nanowire (NW) field-effect transistor (FET). Experimental results confirm that detection sensitivity is favorably improved by the increment of NW size in the DG-NWFET, whereas it is enhanced by the decrement of NW size in a conventional single-gate (SG) NWFET. Sensitivity improvement by the augmentation of the NW size in the DG-FET paves the way to overcome technical challenges we face in achieving ultimate miniaturization of the NW size in the SG-FET. This result is comprehensively understood by simple capacitive modeling. The proposed model explains the observed experimental data and provides a design guideline for highly sensitive NW biosensors. [ABSTRACT FROM PUBLISHER]

This paper experimentally investigates the unique behavior of transconductance (gm) in the Schottky-barrier metal–oxide–semiconductor field-effect transistors (SB-MOSFETs) with various silicide materials. When the Schottky-barrier height (SBH) or a scaling parameter is not properly optimized, a peculiar shape of gm is observed. Thus, gm can be used as a novel metric that exhibits the transition of the carrier injection mechanisms from a thermionic emission (TE) to thermally assisted tunneling (TU) in the SB-MOSFETs. When the local maximum point of gm is observed, it can be expected that an incomplete transition occurs between TE and TU in SB-MOSFETs. When a dopant-segregation (DS) technique is implemented in the SB-MOSFETs, however, the carrier injection efficiency from the source to the channel is significantly improved, although the SBH is not minimized. As a consequence, the peculiar shape of the gm disappears, i.e., a complete transition from TE to TU can be enabled by the DS technique. [ABSTRACT FROM AUTHOR]

Enhanced Dopant-segregated Schottky-barrier (DSSB) FinFETs combined with a fully silicided (FUSI) gate were fabricated via single-step Ni-silicidation. Both workfunction control of the gate and a lowered effective SB-height in the source/drain junctions are simultaneously achieved by the dopant-segregated silicidation process. Moreover, the leakage current was significantly reduced with the aid of deep source/drain implantation. Therefore, it can be expected that a DSSB device with a FUSI gate have several advantages as both a logic and nonvolatile memory device. First, for a logic device, it can provide low parasitic resistance and a tunable threshold voltage. Second, for a nonvolatile memory device, the increased workfunction due to the FUSI gate can enhance the erasing characteristics by suppressing the back tunneling of electrons from the gate side as well as the programming characteristics. [ABSTRACT FROM PUBLISHER]

Asymmetric source and drain (S/D) series resistances ( RS and RD ) are unavoidable in exfoliated MoS2 field-effect transistors (EM-FETs). Through combining the capacitance–voltage ( C – V ) and current–voltage characteristics, the asymmetric C – V and R_{D,int}) are characterized through deembedding the parasitic pad capacitances ( C_{Pad} = C_{S,Pad}+C_{D,Pad}) between the S/D metal and the bottom gate (G) in an overlapped region with the consideration of the structure-dependent parameters in the EM-FET. The proposed methodology is verified through comparison with the well-known channel resistance method, which is based on only the ID – VD characteristics in the linear region. Finally, RS,int and RD,int at various parasitic overlap areas are extracted separately with improved accuracy. [ABSTRACT FROM PUBLISHER]

Hump characteristics of n-channel amorphous indium-gallium–zinc-oxide (a-InGaZnO) thin-film transistors (TFTs) after positive gate and drain bias stress (PGDBS) are investigated. With the increase of the PGDBS time, we observed not only a shift of the threshold voltage ( VT ) but also a generation of the hump in the transfer characteristics. The hump is caused by the localized trapping of electrons in the gate insulator over the gate-source overlap region by the high vertical field during the PGDBS ( V\mathrm {GS}=30 , V\mathbf {DS}=30 ; V\mathrm {GD}=V\mathrm {GS}-V\mathrm {DS}=0 V). The TFT with a hump after PGDBS is modeled as a series connection of main and parasitic TFTs. The parasitic TFT for the electron trapping at the gate-source overlap region has a higher threshold voltage ( V\mathrm {Tp} ) and a shorter effective channel length ( L\mathrm {chp}\cong L\mathrm {ov} ) compared with those ( V\mathrm {Tm} and L\mathrm {ch} ) of the main TFT. [ABSTRACT FROM PUBLISHER]

Thin-film transistors using In-Ga–Zn-O (IGZO) semiconductors were evaluated under current stress by applying positive voltages to the gate and drain electrodes. Initially, the transfer characteristics exhibit identical threshold voltages ( VT) when the source and drain electrodes are interchanged during measurement (forward and reverse V\mathrm {DS} sweep). However, as stress time increases, larger shifts in VT are observed under forward V\mathrm {DS} sweep than under reverse V\mathrm {DS} sweep conditions. Subgap states analyses based on the photoresponse of capacitance-voltage ( $C$ – $V$ ) curves suggest that local annihilation of donor-like traps occurs near the drain electrode. Hump-like features are clearly observed in the $C$ – $V$ curves collected between the drain and gate electrodes, while they do not appear in the $C$ – $V$ data obtained between the source and the gate. Based on the above, a local charge trapping model is introduced in order to interpret the device degradation. In this model, the major carrier electrons are trapped more abundantly near the source electrode due to the presence of a Schottky junction between IGZO and the source/drain electrodes. [ABSTRACT FROM AUTHOR]

Sub-bandgap ( E\mathrm {ph}

We report a dual-sweep combinational transconductance technique for separate extraction of parasitic source ( RS ) and drain ( RD ) resistances in thin-film transistors (TFTs) by combining forward and reverse transfer characteristics. In the proposed technique, gate bias-dependent total resistance [ RTOT ( VGS )] and degradation of the transcond- uctance due to the parasitic resistance at the source terminal during the dual-sweep characterization are employed. Applying the proposed technique to amorphous oxide semiconductor TFTs with various combinations of channel length ( L ) and width ( W ), we successfully separated R_{S} and RD . A model for the W$ - and $L$ -dependences of the extracted parasitic resistances is also provided. [ABSTRACT FROM PUBLISHER]

The physical origins of the negative-bias stress (NBS) instability in polymer-based thin-film transistors have been characterized. Through the quantitative analysis by TCAD simulation for the NBS time-dependent experimental results, the threshold voltage (VT)-shift by sub-bandgap density-of-states redistribution forms 70% and 78% for the measured total VT -shift while VT -shift by gate oxide charge trapping only takes 30% and 22% at NBS time of 3000 and 7000 s, respectively. In addition, the increase of source/drain Schottky contact resistance (RSD) is the main reason for NBS-induced on -current (ION) degradation. [ABSTRACT FROM AUTHOR]

We investigated the effect of the deposition temperature on the electrical performance of SiOx passivation layers for amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs). Compared to the time-of-flight secondary ion mass spectroscopy depth profile of the IGZO film with a SiOx passivation layer deposited at low temperature (150 ^\circ\C), that with the SiOx film formed at 300 ^\circ\C exhibited the significant migration of metal ions from the IGZO film into the SiOx passivation layer. These results were attributed to the high-energy ion bombardment on the IGZO channel layer. In order to suppress the interdiffusion of In, Ga, and Zn atoms between the IGZO and passivation layers, we proposed double SiOx passivation using different substrate temperatures. It combines the merits of low-temperature (150 ^\circ\C) and high-temperature (300 ^\circ\C) passivations and compensates for their individual weaknesses. We confirmed the enhanced electrical characteristics and improved reliability of the IGZO TFTs compared to those of the conventional device. [ABSTRACT FROM AUTHOR]

We proposed and fabricated amorphous indium–gallium–zinc-oxide thin-film transistors (TFTs) employing a novel organic-passivation layer (CYTOP) that results in low damage and good dielectric quality. The TFT with the CYTOP-passivation layer successfully exhibited a relatively good electrical characteristic (\musat = \12.3\ \cm^2/\V\cdot\s) compared with that (\musat = \5.8\ \cm^2/ \V\cdot\s) of the TFT with a SiOx-passivation layer. The CYTOP-passivated device exhibited relatively good stability (\Delta VTH : \2.8\ \V) under positive bias-temperature stress while the TFTs with the SiOx-passivation layer showed a 3.3-V \Delta VTH shift, respectively. The CYTOP passivation was performed at low annealing temperature (180 ^\circ \C), and therefore, it is a good candidate for advanced flexible displays. [ABSTRACT FROM AUTHOR]

A nonpiecewise drain current model is formulated for long-channel junctionless (JL) cylindrical nanowire (CN) FETs. It is obtained by using the Pao–Sah integral and a continuous charge model, which is derived by extending the parabolic potential approximation in all regions of the device operation. The proposed nonpiecewise model analytically describes the bulk and surface current mechanisms in JL CN FETs from the subthreshold region through the linear region to the saturation region without any fitting parameters. In addition, for each of these operation regions, the model reduces to simple expressions that explain the working principle of JL CN FETs. The model is compared with numerical simulations and shows good agreement. [ABSTRACT FROM PUBLISHER]

The unidirectional read-out characteristics of a two-terminal biristor are investigated through numerical simulations and experiments. The base doping profile in the biristor, which is analogous to an open-base bipolar junction transistor (BJT), is a key parameter to control both the multiplication factor and the common–emitter gain of the open-base BJT. The simulated results indicate that the asymmetric base doping produces a difference in the latch-up voltage according to the reading direction. A unidirectional conduction path is thereby implemented in a crossbar-array configuration that consists of only the two-terminal biristor. The experimental results based on a vertical structure with local charge injection support that the leakage path through the reverse read direction can be blocked by the asymmetric base doping structure with the selection of proper bias conditions. [ABSTRACT FROM PUBLISHER]

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohm's law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively. [ABSTRACT FROM AUTHOR]

A junctionless transistor with a width of 10 nm and a length of 50 nm is demonstrated for the first time. A silicon nanowire (SiNW) channel is completely surrounded by a gate, and the SiNW is built onto the bulk substrate. The proposed junctionless transistor is applied to a Flash memory device composed of oxide/nitride/oxide gate dielectrics. Acceptable memory characteristics are achieved regarding the endurance, data retention, and dc performance of the device. It can be expected that the inherent advantages of the junctionless transistor can overcome the scaling limitations in Flash memory. Hence, the junctionless transistor is a strong candidate for the further scaling of nand Flash memory below the 20-nm node. [ABSTRACT FROM AUTHOR]

A gate length of 25 nm and a silicon nanowire (SiNW) with a width of 6 nm and a height of 10 nm fully surrounded by a gate are demonstrated. A suspended SiNW, which is fully depleted, is fabricated on a bulk substrate by employing the deep reactive-ion etching process known as the Bosch process. The electrical characteristics and short-channel effects (SCEs) of the SiNW MOSFETs with all-around gates are presented. The fabricated devices show excellent immunity against SCEs despite their being built on a bulk substrate and having gate lengths scaled down to the 25-nm regime. Improved electrostatic characteristics that suppress the SCEs are shown when the dimension of the SiNW is reduced. [ABSTRACT FROM AUTHOR]

We experimentally investigate the sensitivity of threshold voltage (VT) to the variation of silicon nanowire (SiNW) width (W \rm si) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors. [ABSTRACT FROM AUTHOR]

An optically assisted charge-pumping (CP) technique is proposed for the characterization of interface traps in floating-body (FB) devices. Even without a body contact, majority carriers can be supplied into the FB by light illumination, which contributes to enabling the CP process. Under a strong inversion enabled by a back gate, the front gate triggers the CP process with a designed pulse waveform. Consequently, modulation of the majority-carrier concentration at the front interface is monitored by the change of the drain current. Thus, the interface-trap density is extracted from the monitored drain current and the developed analytical model. [ABSTRACT FROM AUTHOR]