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Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

In this article, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film silicon-on-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length. [ABSTRACT FROM AUTHOR]

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer. [ABSTRACT FROM AUTHOR]

The impact of back-gate bias on the total ionizing dose (TID) response of silicon-on-insulator (SOI) nanowire field-effect transistors (NWFETs) is investigated. The voltage shift induced by TID is studied using different NWFET geometries and as function of the bias applied to the back-gate made of the silicon substrate. Modifications induced on static electrical characteristics, that is, drain current versus gate-to-source voltage ID(VGS) characteristics, are investigated. Experimental results highlight that the bias applied to the back-gate during I−V measurements strongly impacts the NWFET TID response. At 0 V applied to the back-gate, a usual TID behavior is observed. I−V curves are shifted to negative VGS values, which is consistent with the literature. In contrast, two competing mechanisms are shown when negative biases are applied to the back-gate. ID(VGS) curves are first shifted to positive VGS values for low TID before showing a more usual negative TID-induced voltage shifts. This two-step behavior may be attributed to several phenomena. They include either a modification of the net trapped charge sign for several back-gate biases and/or a motion of carriers trapped into the Buried OXide (BOX). The major goal of this article is to identify the mechanism at stake which drives this combined TID/electrostatic behavior. [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) response of pMOS nanowire field-effect transistors (NWFETs) is investigated using X-ray irradiations. The TID-induced voltage shift is studied using two NWFET widths and four bias configurations. Both the impact of the geometry and the influence of the bias configuration during irradiation on the radiation-induced trapped charges into the buried oxide are thus addressed. The impact of gate length downsizing on the NWFET’s electrical characteristics in several bias configurations is studied and compared to one of the nMOS NWFETs to state on the mechanisms which leads to their TID response. [ABSTRACT FROM AUTHOR]

This paper investigates the total ionizing dose (TID) sensitivity of nanowire (NW) field-effect transistors (NWFETs). Both X-ray irradiations and self-consistent calculations of charge trapping in dielectrics are performed to study their TID response. First of all, the impact of the NW geometry is investigated. The NWFET TID behavior exhibits a strong dependence as a function of the NWs width while shortening the gate length does not significantly change the TID characteristics of optimized narrow NWFETs. Furthermore, the effect of the bias configuration used during irradiation is discussed to state if nMOS NWFETs could withstand significant amount of TID in several operation conditions. [ABSTRACT FROM PUBLISHER]

This paper investigates the total ionizing dose (TID) response of nanoscaled field-effect transistors (FET) made of silicon multiple-gate nanowire (NW). The NWFET architecture relies on its remarkable electrostatic properties to push “silicon”-based technologies much deeper into device scaling than present FinFETs. However, as commonly observed when a new device or technology concept is proposed, such as shallow trench isolation and silicon-on-insulator or FinFET, TID effects reveal unexpected behaviors that can permanently modify pristine device electrical characteristics. This is why this paper discusses the impact of several parameters including the NWFET design and the transistor’s type to get thorough insights into the NWFET TID behavior. [ABSTRACT FROM PUBLISHER]

In this paper, we propose an analytical model to accurately evaluate the parasitic capacitances of an advanced 7-nm-node multigate device structure: 1) FinFET on Silicon On Insulator (SOI) (FFSOI) and 2) stacked nanowire on SOI (SNWSOI). Our model, validated through 3-D TCAD simulations, accounts for gate contact, advanced process bricks, such as gate last, BAR contact, and low- $k$ spacer, but also multilayer dielectric by introducing an equivalent permittivity. Finally, FFSOI and SNWSOI architectures are compared from this parasitic capacitance point of view. [ABSTRACT FROM AUTHOR]

This paper investigates the vulnerability of several micro- and nano-electronic technologies to a mixed harsh environment involving high total ionizing dose at MGy levels and high temperature. Such operating conditions emerge today for several applications like new security systems in existing or future nuclear power plants, fusion experiments, or deep space missions. In this work, the competing effects of ionizing radiations and temperature are characterized in elementary devices made of MOS transistors from several technologies. First, devices are irradiated using a radiation laboratory X-ray source up to MGy dose levels at room temperature. Devices are either grounded or biased during irradiation to simulate two major circuit cases: a circuit which waits for a wake up signal, representing most of the lifetime of an integrated circuit operating in a harsh environment, and a nominal circuit function. Devices are then annealed at several temperatures to discuss the post-irradiation behavior and to determine whether an elevated temperature is an issue or not for circuit function in mixed harsh environments. [ABSTRACT FROM PUBLISHER]

We investigate the impact of performance boosters using mechanical stress on the Single-Event Transient (SET) response of nanometer scaled Fully-Depleted Silicon-On-Insulator (SOI) devices. Laser SET measurements show that the active silicon layer thickness is the most important contributor to the SET response of highly scaled Ultra-Thin SOI (UTSOI) devices compared to the impact of strain. This is then demonstrated by dedicated TCAD calculations performed without taking into account any strain engineering technique. Finally, heavy ion-induced charge collection mechanisms are analyzed through the measurement of fast transients to get additional insights into the impact of short channel effects on the SET response of nanometer scaled SOI devices. [ABSTRACT FROM PUBLISHER]