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Device scaling of partially depleted (PD) silicon-on-insulator (SOI) has the potential to increase speed. However, the increased gate tunneling and capacitance will complicate device behaviors and increase the difficulty in characterization for modeling purpose. For the first time, gate-bulk leakage current Igb and gate capacitance Cgg characterization methodology for PD SOI floating-body (FB) CMOS with high accuracy is proposed and verified in 40-nm SOI devices. These devices are with ultrathin equivalent oxide thickness of 12A, and radio frequency-capacitance voltage (RF-CV) technique is used for Cgg measurement to overcome the impact of leaky gate current. This methodology can eliminate properly the parasitic elements due to the coexistence of opposite poly gate type in the SOI T-shape body-tied device and accurately characterize and model Igb and Cgg behaviors for the PD SOI FB devices. Test patterns are designed with RF ground-signal-ground configuration and same test patterns can be used for both Igb and Cgg characterization. Impact of Igb and Cgg changes on the history effect, and speed and body potential is analyzed by BSIMSOI4.0 models. Simulation accuracy of history effect will have at least 3% improvement with this proposed methodology.

We successfully developed and verified a complete compact model solution for layout dependent effect (LDE) of FinFET technology. LDE has significant impact on the device performances mainly due to the application of stressors and aggressive device scaling. With LDE, performance degradation may be up to 10% or more. In this work, compact model solution for Length of Oxidation (LOD), Well Proximity Effect (WPE), Neighboring Diffusion Effect (NDE), Metal Boundary Effect (MBE), and Gate Line End Effect (GLE) were delivered. This solution was implemented successfully in BSIM-CMG for efficient circuit simulation.

A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling.

For the first time, an efficient methodology to accurately characterize the gate-bulk leakage current (I gb ) and gate capacitance (C gg ) of PD SOI floating body (FB) devices was proposed and demonstrated in 40-nm PD SOI devices with ultra-thin oxide EOT 12A. By applying the RF testing skill for the proposed SOI test patterns, we can eliminate properly the parasitic elements due to the co-existence opposite poly gate type the SOI T-shape body-tied (BT) device and accurately characterize and model the SOI FB I gb and C gg behaviors. Impact on the history effect was analyzed by BSIMSOI4.0 model. History effect analysis with high pulse and low pulse width was shown. Improvement of more than 3% simulation accuracy for history effect was also demonstrated.