Search

The designed circuit features a dual-stage Low Noise Amplifier (LNA) in which, a common source (CS) configuration is employed to achieve high gain, while the subsequent stage adopts a Complementary Common Gate (CCG) setup provide the low power consumption. This arrangement ensures that both transistors share the same biasing current, promoting energy efficiency. The two stages are interconnected in a cascade configuration, amplifying the overall gain and concurrently mitigating noise. To facilitate wideband matching in the input stage, a parallel RC feedback mechanism is implemented. Additionally, a pair of mutually coupled inductors in the CS and CCG stages contribute to rendering the input impedance exclusively resistive, concurrently minimizing the overall size of the circuit. All simulations were done using 65 nm CMOS technology in Cadence Virtuoso. The proposed LNA showcases a Noise Figure (NF) of 3.2 dB, a Peak Power Gain (S21) of 19.8 dB, and an input reflection coefficient (S11) of –16.2 dB, spanning a bandwidth of 3.1-6.2 GHz. Operating on a 1V power supply, the proposed LNA demonstrates power efficiency by consuming only 2.8 mW. The overall performance assessment of the LNA is gauged using the Figure of Merit, yielding an obtained value of 18.2. Comparative analysis with other cutting-edge designs is presented in Table 1. [ABSTRACT FROM AUTHOR]

The current research paper presents a design of a mutually coupled cascode Common Gate Common Source (CG-CS) Low Noise Amplifier (LNA) using current reuse technique. The proposed design provides a significant improvement in the gain and noise performance of the LNA, while also reducing power consumption. Mutually coupled inductors help in reducing the size of the circuit while transformer connected at the output provide output impedance matching. Proposed LNA simulated for the 4–14 GHz RF frequency. Mathematical analysis of proposed LNA has been analyzed using the small signal model henceforth input impedance; gain and Noise Figure (NF) have been derived from it. The design and simulation results show that the proposed LNA design with current reuse technique achieved a maximum gain of 17.87 dB, minimum NF of 5.45 dB, and input reflection coefficient less than –10 dB for the 10 GHz bandwidth. These results indicate a significant improvement in the overall performance of the LNA compared to conventional designs as Figure of Merit (FoM) is 17.34. [ABSTRACT FROM AUTHOR]

A triple path dual resistive feedback noise cancellation (TP-DRNC) low noise amplifier (LNA) with transformer output presented which provides high gain, low noise figure (NF), and high figure of merit (FM). The analysis of triple path, dual resistive, gain, and NF have been discussed. The effect of various components used in the circuit have been analyzed and their optimized values are obtained which resulted in the high (FM). The combination of dual resistive feedback with triple path NC transformer output allowed for low NF and high gain. The proposed GPDK 45 nm complementary metal oxide semiconductor (CMOS) technology-based LNA offers a flat gain curve of 10.81 dB over the range of 1.6 GHz to 4.3 GHz, or 2.7 GHz bandwidth, and S11 less than −9 dB. The input third order intercept point (IIP3) for the given bandwidth has value of 5.7 dBm, while the minimal NF achieved is 2.7 dB; (FM1) is 14.026 and (FM2) is 12.48. The proposed LNA's layout with an o -chip transformer has an area of 0.01985 mm2 [ABSTRACT FROM AUTHOR]

In this paper, a Quad Path Noise Cancellation (QPNC) Low Noise Amplifier (LNA)presented for 5G sub-band 25-35GHz using GPDK 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology; which is composed of Common Source (CS) & Common Gate (CG) stages with resistive feedback and current reuse at the output. QPNC is used to cancel the noise of common gate transistors, which leads to reduce the noise fig. (NF). Resistive feedback is used to tradeoff between the input matching, gain, and NF i.e. overall refining the Figure of Merit (FoM) of the circuit. Mathematical analysis of impedance matching, gain, noise transfer function, and NF have been done using the small signal model of QPNC-LNA. Simulation has been done on Cadence Virtuoso software using GPDK 45 nm CMOS technology. Pre layout simulation result shows the minimum value of gain is 13.38 dB at 30.9GHz while the maximum value is 14.12 dB at 25.87GHz and flat over the entire frequency range. S 11 i.e. input reflection coefficient is ranging from −16.16 dB at 25.21GHz to −11.52 dB at 35GHz for 50 Ω input impedance matching. NF value ranges from 2.69 dB at 25.69GHz to 3.77 dB at 35GHz. The IIP3 value for the proposed QPNC-LNA is 5.3 dB. For the four corners S S, S F, F S, and F F, process corner simulation has been performed. Post-layout simulation results depict the maximum value of gain is 12.71 dB at 25.75GHz. NF value is varying from 2.88 dB to 4.02 dB while the input reflection coefficient is ranging from −10.12 dB to −14.13 dB for 10GHz bandwidth. The circuit consumes 17.53 mW power at 1.2 V under a DC current of 14.61 mA, FoM 1 is 8.36 dB and FoM 2 of the proposed LNA is 49.35 dB. The layout of the proposed LNA is having an area of 0.03026mm2. [Display omitted] • QPNC LNA designed for 25-35GHz using CS and CG stages with resistive feedback and current reuse. • QPNC cancels noise of common gate transistors, reducing the NF. • Resistive feedback optimizes input matching, gain, and NF, improving the FoM of the circuit. • Mathematical analysis of LNA parameters has been done using the small signal model. [ABSTRACT FROM AUTHOR]