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Ferroelectric field effect transistors (FeFETs) composed of P(VDF-TrFE) (Poly(Vinylidenefluoride-Tirfluoroethylene)) thin films and semiconductor substrates show excellent ferroelectric transistor characteristics. Since P(VDF-TrFE) has the ferroelectric polarization as large as those of oxide ferroelectric materials with much lower dielectric constant, it is an ideal material to build FeFETs with the combination to inorganic semiconductor materials. In addition, the process condition to form P(VDF-TrFE) is much milder to underlying semiconducting material compared to oxide ferroelectrics. Therefore, the improvement on the retention characteristics is expected by employing P(VDF-TrFE) ferroelectrics in FeFET instead of oxide ferroelectrics. The potential of P(VDF-TrFE) FeFET is discussed in this chapter.

Microstructures (texture and grain size) dependence of PZT thin films on the oxidation state of lead, heating rate of crystallization annealing, and the quality of bottom electrode was discussed. The spatial variations of the switching charge for a PZT capacitor is mainly determined by the texture of PZT thin film. Switching charge variation less than ±2% is achieved by making a film highly [111] textured.

Antireduction characteristics of IrO2/Pb(ZrxTi1−x)O3(PZT)/Pt ferroelectric capacitors are improved by post annealing. When an as-processed capacitor receives a 3% hydrogen annealing at 300 °C (a process condition for fabricating the interlayer dielectric), capacitor characteristics are heavily degraded. This is because Ir that is produced by IrO2 reduction plays a catalytic role in PZT reduction. By contrast, if the IrO2/PZT/Pt capacitor is post annealed in O2 atmosphere at 600 °C for 1 h, the capacitor characteristics can be maintained even if it undergoes the hydrogen annealing. The O2 annealing improves the crystallinity of the IrO2 top electrode and excess PbOx in sol-gel derived PZT diffuses into the IrO2 film. As a result, antireduction characteristics of the IrO2 top electrode itself are drastically improved and the PZT film becomes stoichiometric at the same time. Exclusion of excess PbOx in PZT results in an increase in spontaneous polarization of the IrO2/PZT/Pt ferroelectric capacitor. Furtherm...

Characteristics of metal-ferroelectrics-metal (MFM) capacitors and meta -ferroelectrics-insulator-semiconductor (MFIS) diodes with poly(vinylidene fluoridetrifluoroethylene) [P(VDF-TrFE)] copolymer films thinner than 100 nm were investigated. The films were prepared by spin cast process and were annealed at 140 degrees C in air for crystallization. The ferroelectric properties are equivalent to those of oxide ferroelectrics, even under low voltage or high frequency operation.

In the stacked structure of PbZr1-xTixO3(PZT)/Pt/TiN/poly-Si for a ferroelectric random access memory (RAM), the mechanism of TiN barrier-metal oxidation was investigated by transmission electron microscopy (TEM). In the cross-sectional TEM images of PZTyPtyTiNySi, titanium oxide was observed beneath the Pt grain boundary. The oxygen was diffused through the Pt grain boundary during the heat treatment in an oxygen atmosphere for crystallization of PZT films. The annealing of the TiN film in ammonia resulted in the suppression of the oxidation during the crystallization annealing of PZT. The minimum required Pt film thickness to protect TiN from oxidation can be reduced from 200 nm to 100 nm.

Degradation of ferroelectricity in PZT (Pb(Zr0.52, Ti0.48)O3) thin-film capacitors caused by heat treatment in a reductive ambience is investigated. We have found that the degradation of ferroelectricity depends upon the metal used for the top electrode of the PZT capacitor. The increased degradation in the case of a PZT capacitor with Pt electrodes can be explained by a catalytic reaction on the Pt surface. With the use of an IrO2 non-catalytic top electrode, we have made the ferroelectricity of an IrO2/PZT/Pt capacitor retained even after the H2 annealing at 400°C, or above. This IrO2/PZT/Pt capacitor is a useful structure to avoid H2 damage in actual LSI fabrication processes.

A one-mask-patterned ferroelectric capacitor test structure designed with a 0.5-μm feature size was fabricated. Oxygen plasma treatment after dry etching decreased the leakage current to as low as that of as-deposited film. These one-mask-patterned ferroelectric capacitors, with switching charge almost equal to as-deposited film, were successfully fabricated. Ferroelectric memories as dense as dynamic random access memories will become possible with this technology. However, the leakage current density for micron-sized capacitors is 2 to 10 times that of large capacitors. The leakage current in small capacitors is increased due to perimeter leakage that runs through the damaged region on the capacitor sidewall. © Scripta Technica, Inc. Electr Eng Jpn, 121(1): 43–50, 1997

The disappearance of ferroelectricity in Pb(Zr0.52,Ti0.48)O3 (PZT) thin-film capacitors, which is caused by heat treatment in a reductive ambience, is investigated. Bare PZT films are not damaged by annealing in a hydrogen-containing atmosphere (H2 annealing) up to 400 °C, whereas a PZT capacitor with Pt electrodes loses its ferroelectricity during annealing at less than 300 °C. We have found that the degradation of ferroelectricity depends upon the metal used for the top electrode of the PZT capacitor. The increased degradation in the case of a PZT capacitor with Pt electrodes can be explained by a catalytic reaction on the Pt surface. We have made the ferroelectricity of a Pt/PZT/Pt capacitor retained even after the H2 annealing at 300 °C, or above, simply by oxidizing it before the H2 annealing.

A one-mask-patterned ferroelectric capacitor memory cell structures designed with a 0.5-μm feature size were fabricated. Oxygen plasma treatment after dry etching decreased the leakage current to as low as as-deposited film. The one-mask-patterned ferroelectric capacitors with switching charge almost equal to as-deposited film were achieved. Ferroelectric memories as dense as dynamic random access memories will become possible with this technology.

Lead zirconate titanate (PZT) thin films were prepared by reactive coevaporation with high-concentration ozone. PZT thin films that demonstrate the highest charge storage density (280 fC/μm2 at 1.5 V for 75-nm-thick film) yet reported have been fabricated. No fatigue was observed after 1011 polarization switching cycles even though a Pt electrode is used. A low leakage current of

We developed Al2O3/Si3N4 stacked insulators suitable for the advanced metal–oxide–semiconductor (MOS) devices. Ultrathin Si3N4 was prepared by direct nitridation of Si substrate using atomic nitrogen radicals. With this process, the film obtained was less defective compared to conventional Si3N4. Al2O3 was then deposited by atomic layer deposition on Si3N4 and oxidized to eliminate defects in the film. Since the buffer Si3N4 does not contain a large amount of hydrogen, we could perform high-temperature oxidation without any additional interfacial layer formation in the Si substrate. We achieved high capacitance density and low leakage current that are acceptable for the gate insulator in advanced MOS devices with a 0.1 μm gate length by exploiting this buffering technique.

The ferroelectricity of sol-gel derived 80-nm Bi3.45La0.75Ti3O12 (BLT) films was significantly enhanced by low-pressure baking during the sol-gel process. The ferroelectricity enhancement was caused by the low-pressure baking after the drying process in air and before the crystallization of the dried gel. The maximum remanent polarization (Pr) was 27.2 µC/cm2, which was achieved after baking at 1.3 kPa oxygen pressure. The coercive field of 54.3 kV/cm was also achieved at the same time. This Pr value is 2.3 times larger than the value attainable with the usual 1-atm baking process. The saturation property of the same capacitor proved that +/-2 V operation is possible. It was also found that the enhanced polarization is fatigue-free up to 1010 switching cycles.

A three-dimensional (3-D) vertical chain-cell-type phase-change memory (VCCPCM) for next-generation large-capacity storage was developed. The VCCPCM features formation of memory holes in multi-layered stacked gates by using a single mask and a memory array without a selection transistor. As a result of this configuration, the number of process steps for fabricating the VCCPCM is reduced. The excellent scalability of the VCCPCM's new phase-change material makes it possible to reduce the cell size beyond the scaling limit of flash memory. In addition, a poly-silicon selection diode makes it possible to reduce the cell factor to 4F2. Consequently, relative cost of the VCCPCM compared to 3-D flash memory is reduced to 0.2.

We developed high-performance metal–ferroelectric–insulator–semiconductor (MFIS) structures with a damage-free and hydrogen-free Si3N4 buffer layer as an insulator. We fabricated Si3N4 films by nitriding Si substrates with N2 and/or atomic N radicals generated by an rf radical cell. In contrast to conventional Si3N4 films, the radical-nitride Si3N4 films showed no hysteresis or flat-band shift in the capacitance–voltage (C–V) characteristics even after high-temperature treatments, such as crystallization annealing of ferroelectric thin films deposited on the buffer Si3N4. Using this radical nitride Si3N4 as a buffer layer, we fabricated MFIS diodes with a Pt/Bi3.25La0.75Ti3O12/Si3N4/Si structure. These diodes had good hysteresis in their C–V characteristics, resulting from remnant polarization of the ferroelectric films. However, no other parasitic effects originating in charge trapping and/or detrapping were observed.

We report a novel resistive switching ion-plug memory (IPM) with a dual-layered structure containing a solid electrolyte layer (supply layer) that has Cu ions and a resistive switching layer (memory layer). By adopting this structure, IPM achieved higher endurance and longer retention time compared to previously reported solid electrolyte memory because excess Cu deposition was prevented. The conductive path of Cu with a 20 nm was observed by a cross sectional transmission electron microscope analysis. Generation/rupture of the path enables local resistance switching at diameters smaller than 32 nm. A set/reset operation that takes 30 ns and an endurance of 109 cycles were presented. IPM is a promising candidate for high-density memory for 32-nm technology node and beyond.

Exceptionally low-voltage operation of organic ferroelectric capacitors and diodes was demonstrated. Ferroelectric polyvinylidene fluoride-trifluoroethylene [P(VDF-TrFE)] thin films were prepared by the solvent-cast method. Metal-ferroelectric-metal capacitors with 60-nm-thick P(VDF-TrFE) films exhibited well-saturated hysteresis curves whose coercive voltage (Vc) and remanent polarization (Pr) were 2.0V and 11.9μC∕cm2, respectively. The authors also fabricated metal-ferroelectric-insulator-semiconductor diodes with 100-nm-thick P(VDF-TrFE) films. Rectangular-shaped capacitance-voltage (C-V) hysteresis loops were obtained with a voltage sweep range narrower than 5V. The maximum memory window of 4.7V was achieved.

A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., current and voltage) for the cell is significantly reduced by inserting a very thin Ta2O5 film between GeSbTe (GST) and a W plug. The Ta2O5 interfacial layer works not only as a heat insulator enabling effective heat generation in GST but also as an adhesion layer between GST and SiO2 underneath. Nonetheless, sufficient current flows through the interfacial layer due to direct tunneling. A low programming power of 1.5 V/100 muA can therefore be obtained even on a W plug with a diameter of 180 nm fabricated using standard 0.13-mum CMOS technology. In addition, the uniformity and repeatability of cell resistance are excellent because of the inherently stable Ta2O5 film properties

One of the most serious forms of damage that occurs during the integration of Pt/PZT/Pt ferroelectric capacitors [where PZT is Pb(ZrxTi1−x)O3] is the disappearance of polarization hysteresis characteristics during the passivation process. The hydrogen content of the atmosphere during this process affects the ferroelectric capacitor characteristics. However, the PZT film itself is not damaged by annealing in a hydrogen‐containing atmosphere even at 400 °C, whereas the Pt/PZT/Pt ferroelectric capacitor loses its polarization hysteresis characteristics at 300 °C. The top Pt electrode was found to induce this damage. Possible mechanisms such as stress and a chemical reaction with the Pt catalyst are discussed.

A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O/sub 2/ annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array.

The Al2O3 thin films were deposited on the Si3N4 (radical- Si3N4) prepared by the direct nitridation of a Si substrate using atomic nitrogen radicals. Because the radical- Si3N4 is highly resistive against the oxidation process, we can completely eliminate the metal phase in Al2O3 that degrades the insulating properties of Al2O3. The 1.3nm thick Al2O3 film was found to have a permittivity of 9.76 in this stacked Al2O3/Si3N4 structure. It was also found that no oxidation took place at the interface of Si3N4 and the Si substrate during the deposition and post-oxidation of the Al2O3 film on the radical-Si3N4/Si substrates. As a result, highly capacitive MIS (Metal-Insulator-Semiconductor) structures were realized using the Al2O3/Si3N4 stacked insulator. The MIS diode with Al2O3/Si3N4 is found to have 105 times less leakage current compared to the diode with Si3N4 insulator film with similar capacitance density. We have shown that the insulating properties of the Al2O3/radical-Si3N4 stack are suitable for the MFIS (Metal-Ferroelectric-Insulator-Semiconductor) transistors.

The hillock growth mechanism at the surface of Pt/TiN electrodes is investigated. TEM and SEM observations confirm that local delamination occurs at the Pt/TiN interface first, and then, plastic deformation of the Pt films under compressive stress forms hollow domes, which result in hillocks. Hillocks always start to grow when the internal stress in the Pt films reaches about −1000 MPa during annealing in N2/O2 ambient. Since the initial internal stress of Pt thin films varies from −500 to 500 MPa, depending on their deposition temperature, the hillock growth temperature strongly depends on the deposition temperature of the Pt films. It is very important, therefore, to control the initial internal stress in Pt films in order to eliminate hillock growth at the surface of Pt/TiN electrodes.

An indium-incorporated germanium–antimony–telluride material, In20Ge15Sb10Te55 (IGST), was investigated as a recording material for phase change memory. The crystallization temperature of IGST was 226 °C, which is 75 °C higher than that of conventional GST. The reset current of the device using IGST was about 10 mA for a plug 180 nm in diameter, which enabled a low-power operation, compared with the GST-based device. A cycle endurance of up to 1.5×104 was achieved. The data retention was estimated to be 10 years at 145 °C. These data clearly show that IGST exhibits promising characteristics as a recording material for phase change memory.

Retention performance of organic metal–ferroelectric–insulator–semiconductor (MFIS) diodes composed of random copolymer poly(vinylidene fluoride)-trifluoroethylene [P(VDF-TrFE)] was drastically improved by introducing poly(methyl methacrylate) (PMMA). Only a small amount of PMMA blended to P(VDF-TrFE) copolymer improved the insulating property of thin ferroelectric films. The MFIS diode with 1.65 wt % PMMA-blended P(VDF-TrFE) film achieved the retention time longer than 106 s until now and it showed no obvious degradation of switching charge. Precise control of PMMA composition and the crystallization condition made it possible to achieve the above mentioned performance.

The deposition temperature dependence and postannealing temperature dependence of the properties of metal-organic chemical vapor deposited Ru film were investigated in order to minimize the leakage current density across Pt∕Bi4−xLaxTi3O12∕Ru ferroelectric capacitors. With postannealing at 400°C, leakage current density was decreased to 1∕100 of the as-deposited sample, although surface morphology and crystallinity hardly changed. The improvement effect of the leakage current was not pronounced, even if the postannealing temperature was further increased. These observations suggest that the effect of crystallinity and surface morphology of Ru film is less significant for the leakage current density, and alternative phenomenological model to explain these results is presented.

Large-scale integrated fabrication in a H2 containing atmosphere, for example, during the passivation process, can cause serious damage in metal/Pb(Zr,Ti)O3/metal capacitors (i.e., Pt/PZT/Pt capacitors). To reveal the cause of the H2 damage, we investigated the behavior of hysteresis curves and the leakage current of capacitors with a top electrode of Pt, Pd, Au, or Ag. Capacitors with a top electrode of Au or Ag are more resistant to the H2 annealing damage than those of Pt or Pd. We found that the H2 damage was strongly affected by the catalytic activity and adsorptive properties of the top electrode when exposed to H2.

Ferroelectric Ru/Bi4-x La x Ti3O12/Ru capacitors were fabricated by combining metalorganic chemical vapor deposition (MOCVD) of top and bottom Ru electrodes and spin-coating of the ferroelectric film. After optimization of the deposition conditions, good ferroelectric properties (2P r=18 µC/cm2, P r: remanent polarization) and low leakage current density (2×10-6 A/cm2) were achieved. No significant fatigue phenomenon (decrease of P r) was observed even after 1010 switching cycles.

For field effect transistor (FET)-type ferroelectric memories, c-axis oriented (Bi, La)4Ti3O12 films with small remanent polarization Pr of 4 µC/cm2 were investigated. Bi3.25La0.75Ti3O12 films were prepared by the sol-gel method on amorphous Si3N4 layers formed on Si substrates using atomic nitrogen radicals. It was found that the films formed using stoichiometric sol-gel solution did not crystallize even after annealing at 800°C in O2 ambient. Therefore, 2.5 to 7.5% excess-Bi solutions were used and such parameters as pre annealing and crystallization temperatures, film thickness and crystallization ambient were optimized. As a result, the well c-axis-oriented Bi3.25La0.75Ti3O12 films with good crystallinity and good surface morphology were obtained at temperatures higher than 600°C. It was also found in a Pt/100 nm-Bi3.25La0.75Ti3O12/3 nm-Si3N4/Si (metal/ferroelectric/insulator/semiconductor) structure that C–V characteristics showed a hysteresis loop with a memory window of about 1 V and both high and low capacitance values kept at zero bias voltage did not change for more than 3 h.

Ultrathin (Ba,Sr)TiO3 (BST) film capacitors with a Pt/Ba0.5Sr0.5TiO3(30 nm)/Pt/TiN/Si structure were fabricated. To investigate the effects of annealing temperatures, capacitors were annealed in flowing Ar or O2 at temperatures ranging from 400°C to 600°C for 30 min. The electrical properties of the annealed samples were strongly dependent on the annealing temperatures. In the capacitors annealed at 500°C (in Ar and O2) and 550°C (in O2), the leakage current decreased to a level of 10-8 A/cm2 when the bias voltage was ±1.5 V. In the as-deposited sample, the maximum capacitance appeared at a bias voltage of -1 V. However, the maximum capacitance increased and appeared at the zero bias voltage after annealing. These phenomena are believed to be defect-related (due to oxygen vacancies). The annealing atmospheres were also found to have an effect on preserving the morphology of the Pt electrodes.

Resistance of the IrO2/PZT/Pt ferroelectric capacitor to the ambient of an interlayer-dielectric-deposition process is investigated for integrating the capacitor in a ferroelectric nonvolatile memory. Silicon dioxide films are deposited on the capacitor as the interlayer dielectric by plasma-enhanced chemical vapor deposition (CVD) using SiH4 and N2O gases. Degradation of ferroelectric characteristics reported so far for Pt/PZT/Pt capacitors is found to be significantly suppressed in the IrO2/PZT/Pt structure. This is because IrO2 does not show a catalytic effect as exhibited by a platinum electrode which causes hydrogen decomposition during the CVD processes. Hence, the IrO2/PZT/Pt capacitor structure proposed by us did not undergo the degradation in the process.

Oxygen diffusion through the grain boundaries of Pt films during the crystallization annealing of Pb(Zr, Ti)O3 (PZT) was investigated for the stacked structure of PZT/Pt/TiN. If the Pt film was sputtered on the TiN film by an in-vacuum process, then columnar (111)-oriented grains were grown with continuous grain boundaries normal to the substrate. On the other hand, a Pt film deposited on a TiN film exposed to air after the TiN deposition consisted of granular grains with a random orientation, because the Pt film was grown on the native oxide surface of the TiN film. The degree of oxygen diffusion in the Pt film deposited on the exposed TiN film was lower than that on the nonexposed TiN film after the PZT was crystallized at 650° C in O2. Differences in the grain boundary structure, such as the diffusion length, are considered to determine the oxygen diffusion rate.

The PZT polarization hysteresis characteristics in a Pt/PZT/Pt ferroelectric capacitor are degraded by annealing in a hydrogen-containing atmosphere due to the catalytic effect of the top Pt electrode. This can be avoided by using an IrO2/PZT/Pt capacitor structure as we proposed. During hydrogen annealing of the as-grown capacitor, the top IrO2 electrode is deoxidized, degrading the capacitor characteristics. However, the polarization hysteresis characteristics are preserved after hydrogen annealing at 300° C if the IrO2/PZT/Pt capacitor is pre-annealed in oxygen at 600° C.

Pb(Zr,Ti)O3 capacitors with top platinum electrodes area subjected to hydrogen annealing from 300°C to 450°C. Both the remnant polarization and breakdown voltage were drastically degraded after hydrogen annealing, whereas the dielectric constant was found to be relatively stable. Capacitors recovered their characteristics before annealing after re-oxidation treatment. An interfacial degradation model with a platinum-catalysis reduction is proposed to explain these notable degradation phenomena.

The characteristics of TiN film, which is well suited for use as the barrier layer of ferroelectric capacitors, were investigated. It was found that high-density TiN is more resistive against oxidation than low-density one. It was also revealed that the -oriented TiN had higher oxidation resistance than the -oriented one. However, whereas a thick Pt bottom electrode was previously used to prevent barrier layer oxidation, we found that the Pt thickness can be reduced to less than half with high-density -oriented TiN. TiN oxidation followed the linear-oxidation law (a reaction-limited process) in the initial stage of oxidation, and the oxidation rate was found to be inversely proportional to the density and proportional to the etching rate. The etching rate of the -oriented TiN was lower than that of the -oriented TiN, indicating that (100) was less reactive than (111). Consequently, the -oriented TiN film exhibited high oxidation resistance.

A new technique called microwave DLTS is developed and proven to be a powerful method for the characterization of deep levels in semi-insulating GaAs wafers. Because this new technique is essentially nondestructive and contactless, it is quite suitable for the direct characterization of GaAs wafers for IC fabrication processes. Using microwave DLTS, density distributions of EL2 in undoped semi-insulating GaAs wafers were measured nondestructively.