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The formation and dynamics of a single drop of liquid under the influence of gravity can be experienced as everyday phenomena, and have been the subject of scientific investigations since at least the work of Leonardo da Vinci in the early 1500s and Mariotte in the 1680s. Experiences with liquid drops in everyday life are captured by poets and artists as well as scientists, whose theoretical and experimental investigations develop fundamental understanding of drops with size 107 m. This paper presents observations of the formation of a single liquid drop of molten steel following bursting of a liquid film formed by illuminating a steel plate by a high energy laser. The hole morphology is analyzed with a proposed kinematic model of hole expansion for the very early stages in the bursting of the hole. Estimates of the hole eccentricity, area, perimeter, and circularity obtained from the model are presented and discussed. Experimental measurements show that a single drop of liquid steel detaches from the end of a neck that then cools to room temperature. Measurements also show that the liquid drop oscillates while falling under gravity. No satellite drops are observed.

The beauty, kinematics, and dynamics of thin liquid soap films under the influence of gravity have inspired experimental and theoretical investigations by scientists at least since the research of Plateau and Lord Rayleigh in the mid1800s. The wide-ranging interest in thin films may also be attributed in part to readily available, inexpensive ingredients as well as to the enjoyable nature of the interactive activity itself. While the creation of the films produces relatively long-lived persistent films, the violent destruction of the films follows a rupture that may occur spontaneously and can also be initiated by external forces. This paper presents thick liquid films of molten steel and discusses the fundamental nature of the behavior of vertical thick films under the influence of gravity. This paper presents observations of stable thick liquid films of molten steel with thicknesses of 1.5 mm, 1.8 mm, and 1.9 mm. We observe spontaneous bursting of vertical thick films in the presence of gravity, without any other external forces, with an initial horizontal speed of 0.68 m/s–0.9 m/s and a vertical acceleration of ∼(6 ± 1)g, with sudden hole enlargement, like soap film popping. Experimental measurements of the preburst films, following cooling to room temperature, show the presence of a three-dimensional dimple and bulge and fairly agree well with theoretical predictions of Surface Evolver, due to a liquid surface tension that is strong enough to resist the force of gravity.The beauty, kinematics, and dynamics of thin liquid soap films under the influence of gravity have inspired experimental and theoretical investigations by scientists at least since the research of Plateau and Lord Rayleigh in the mid1800s. The wide-ranging interest in thin films may also be attributed in part to readily available, inexpensive ingredients as well as to the enjoyable nature of the interactive activity itself. While the creation of the films produces relatively long-lived persistent films, the violent destruction of the films follows a rupture that may occur spontaneously and can also be initiated by external forces. This paper presents thick liquid films of molten steel and discusses the fundamental nature of the behavior of vertical thick films under the influence of gravity. This paper presents observations of stable thick liquid films of molten steel with thicknesses of 1.5 mm, 1.8 mm, and 1.9 mm. We observe spontaneous bursting of vertical thick films in the presence of gravity, without...

Research on Rent's rule in electrical engineering, the applied sciences, and technology has been based on the publication of a 1971 interpretation of Rent's memoranda by B. S. Landman and R. L. Russo. Because of the wide impact of Rent's work and requests from researchers, we present his original memoranda in this paper. We review the impact of Rent's work and present the memoranda in the context of IBM computer hardware development since the 1950s. Furthermore, because computer hardware components have changed significantly since the memoranda were written in 1960, a new interpretation is needed for today's ultra-large-scale integrated circuitry. On the basis of our analysis of the memoranda, one of the authors' personal knowledge of the 1401 and 1410 computers, and our experience in the design of high-performance circuitry for microprocessor chips, we have derived an historically equivalent interpretation of Rent's memoranda that is suitable for today's computer components. We describe an application of our historically equivalent interpretation to the problem of assessing on-chip interconnection requirements of control logic circuitry in the IBM POWER4TM microprocessor.

Computer hardware components have changed significantly since the 1960s, 1970s, 1980s, and even since the early 1990s. Work concerning Rent's memos prior to the present paper has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent while working at IBM, even though today's computer components are significantly different from those in 1960 and 1971. However, because of the significant changes in the design and implementation of computer hardware components since 1960 and 1971, a new interpretation of Rent's memos is needed for today's components. We have obtained copies of Rent's two memos. In these memos, Rent describes the method that he used to obtain an empirical relationship between properties of the computer hardware components of the IBM 1401 and the IBM 1410 computers. We have studied these memos carefully in order to understand Rent's original intent. Based on our careful reading of these two memos, the personal knowledge of one of us with the 1401 and 1410 computers, and our experience designing ultralarge-scale integrated (ULSI) circuits for high-performance microprocessors, we have derived an historically equivalent interpretation of Rent's memos suitable for today's computer components. The purpose of this paper is to present a new interpretation of the memos and to present an application to wirelength distributions of real ULSI circuitry. In this paper, we will: 1) describe the contents of the memos and Rent's method; 2) provide an historically-equivalent interpretation of Rent's memos for today's computer components; and 3) apply this new interpretation to real ULSI control logic circuitry in the 1.3-GHz IBM POWER4 microprocessor. In this paper, we will show that this new interpretation of the two memos provides improved wirelength distribution models with better qualitative agreement with measurements and more accurate estimates of wirelength distributions and wirelength requirements for real ULSI designs compared with prior methods.

Ultralarge-scale integrated (ULSI) chip design data is needed for an assessment of existing on-chip wirelength distribution models. Data extracted from modern chips such as high-performance microprocessors provide information about actual wire length requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by evaluating existing models as functions of Rent's parameters that are extracted from the designs. This brief assesses the extent to which existing models estimate wirelength requirements in 100 ASIC-like control logic designs in the 1.3-GHz POWER4 microprocessor. For each design, physical design characteristics and wirelength requirements are measured and compared with model estimates. Lack of agreement between the data and models is observed for most designs, and possible reasons for the lack of agreement are discussed.

The DARPA TRUST program was established to address the need to verify integrated circuits (ICs). This paper explores methodologies to resolve conflicts among IC designs in prior applications of commercial software to verify designs ranging in size from 1 to 283,359 cells. Preliminary results show the capability of commercial software tools to generate test cases for evaluation.

This paper presents a method of characterizing single-walled carbon nanotube (SWCNT) ink and discusses preliminary research results of our characterization efforts. First, the process of ink jet printing SWCNT ink onto organic and inorganic substrates is discussed. Next, the tests for measuring sheet resistance, conductance, thickness, roll-off, and S-parameters of the ink are described. Future research directions will be discussed, including the additional characterization of SWCNT ink

The phase contrast imaging of surface steps in reflection electron microscopy is analysed. It is shown that the typical images are seriously affected by incoherence effects and that this arises, not from the strong inelastic scattering which is often present, but from the effective angular spread in the illumination which is frequently determined by the width of the Bragg reflection.

This paper presents models and a methodology to evaluate tradeoffs between technology and design to obtain the highest frequency in ULSI design projects and quantifies the performance improvement that can be expected. With respect to the standard chip design process, it is well known in the academic community that circuits and chips are required to satisfy specific constraints, most notably the requirement that all signals must have zero slack when the transistors and wires are manufactured at some pre-specified technology node. To amortize the cost of the design process, which is time-consuming and complex, there is a need to migrate the designs to future technology nodes with minimal redesign. However, this problem and the associated implications of design migration are less well known, and at present there are no existing models to help designers evaluate whether migrated designs will operate successfully in a future technology or whether migrated designs will fail and thus cause chip failure. Thus, there is a need for research to evaluate the impact of design changes on chip performance. This paper presents a methodology to evaluate and quantify the performance impact of design changes, where we express the impact on performance as an effective change in dielectic constant in the wire environment. In this study, as in a previous study[1], performance estimates obtained from the model are compared with values obtained for interconnections in 18 ASIC-like control logic designs in the Instruction Fetch Unit (IFU) of the 1.3GHz POWER4 microprocessor.

Power reduction techniques are a critical issue in the design of today's ULSI chips. This paper is concerned with methods to characterize the capacitive load on the POWER4 on-chip global clock distribution [1], which is a large contributor to the overall chip power dissipation. A characterization of the capacitive load is needed because the contributions of the on-chip devices and interconnections are typically overestimated and are not well understood for high performance microprocessors. One problem that results from the lack of this information is excessively high power dissipation in the chip global clock distribution; the global clock distribution is over-designed and stronger than necessary to drive the actual (lower) chip load. Information about the capacitive load is difficult to obtain because the data volume is large, and extracting the interconnect data is a complex task. Sophisticated computer software is needed to extract the circuit and physical design data for hundreds of devices and wire segments within the chip design schedule.This paper presents the first comprehensive characterization of the clock load for ASIC-like control logic designs in the 1.3GHz POWER4 microprocessor core [1], [2]. This characterization was achieved with the use of sophisticated software written for this study to accomplish the task of extracting the data from these designs. Analysis of the data shows that the wire contribution to the chip capacitive load is significant and can increase the capacitive load of a design by 30% on average and by as much as 130% for some designs. The results also suggest that the wire load contribution on each metal layer can be reduced if an alternate interconnect design style is selected. Two alternate design styles are presented and show that a capacitive load reduction of 8.4% to 20% is expected for each design. Extended to the entire chip, the results show that the load reduction for the core is expected to be as high as 10%. These values are large enough that one alternate design style has been implemented in the design methodology of future chips.

Because of the wide impact of Mr. E. F. Rent's work in engineering, the applied sciences, and technology, the original memos of Mr. Rent and historically equivalent (HE) applications to today's complex integrated circuitry were published in the IBM Journal of Research and Development in 2005. It has been shown that evaluating existing wirelength distribution models with this HE interpretation of Rent's memos provides improved qualitative agreement with measurements and more accurate estimates of on-chip wirelength requirements for application-specific integrated circuit designs in the POWER4™ microprocessor core. Because of the increasing impact of Rent's work, including research on integration density for future computers and expansion to the fields of post-CMOS devices and bioengineering, this paper presents a review of these contributions and a new mathematical framework that explains the HE interpretation of Rent's memos. This framework provides topological constraints for today's ultralarge-scale integrated circuits, as well as a model that predicts this HE interpretation. The model arises from the underlying topology of the circuitry and interconnectivity of the circuit components. Using this model, predictions of the HE Rent parameters are obtained and show agreement to within -5% to +12% of the experimental values obtained from published data for the POWER4 microprocessor circuit designs.