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In EUV lithography, the short wavelength and residual mirror surface roughness increase the flare levels across the slit. As a key research point, the flares of different exposure fields are carefully discussed by numerical simulation. To ensure the effectiveness and practicability of our simulations, the test patterns are generated according to the general design rules for 7nm technology node. The NILS, process variation band (PVB) and MEEFs from mask optimizations and source mask optimizations (SMO) results are compared. From the comparisons, the constant flare has a greater influence on NILS and PVB than that on MEEF. In contrast, the flare map caused more reduction on the MEEF values.

When the negative tone development (NTD) process was introduced into photolithography, it brought fidelity improvement with it. However, the NTD process behaves in a manner that is not readily comprehended by the computational techniques used to create high-speed photolithography models for use in the Optical Proximity Correction (OPC) process. These effects are mechanical in nature and are not governed by the diffraction phenomena used to create high speed process models. This study will discuss an attempt to utilize the high speed OPC model methods to deliver an accurate representation of the NTD process. This paper will discuss a compact modeling flow for NTD processes. The flow works to emulate first principle modeling techniques for NTD in an OPC model. This is accomplished through a combination of the new mechanical methods and traditional Dill’s parameters. It also reduces the data volume required to generate the OPC model. The models generated using this method accurately represent NTD SEM image contours. The results will be demonstrated and discussed.

Extreme ultraviolet lithography (EUVL) is a leading candidate for the 22nm node lithography and beyond. However, there are still some critical problems before EUVL may be deployed in high-volume manufacturing. One of the critical problems is to estimate the EUVL aerial image formation for optical proximity correction (OPC) in order to compensate for EUVL effects such as shadowing and flare. This study discusses aerial image formation through modeling of optical transfer function to assimilate optical diffraction, long range layout dependent flare effects, and shadowing effects due to non-telecentric imaging optics in the EUV case. Hence, after optimizing optical process parameters to model the EUV aerial image, this study will investigate OPC modeling methods employed to compensate these optical effects in the mask design flow.

In modern photolithography, as the feature size becomes smaller and smaller, it becomes more and more popular to include sub-resolution assist features (SRAFs) to improve the robustness of the lithography process. Hence, it is vital to simulate the process precisely with SRAFs placement. However, for computational reasons, it is necessary to model features with SRAFs placed using specially developed approximation algorithms. This need arises because of the inherent differences between SRAFs and main features. First, SRAFs are usually hard to verify physically because of their small sizes and, therefore, there is relatively large mask measurement uncertainty on the layout of SRAFs compared to main features. Second, unlike the well-defined main features, the shape of SRAFs is relatively poor, e.g., line edge roughness and critical dimension (CD) variation and, hence, the effective transmission of SRAFs may not be the same as for the main features. Third, the thickness of the mask is comparable to the feature sizes of SRAFs and the three-dimensional (3D) mask effect may play an important role in process simulation. In wafer measurements, the data are usually influenced by all the above effects, and it is practically impossible to identify them individually. In this study we propose a lumped treatment specially designed for SRAFs. The results show significant improvement in the simulation accuracy and reduce the RMS of fitting errors down to the sub-nanometer level for all features with or without placed SRAFs.

This study investigates various approaches to flare mitigation in EUVL. We evaluate the effectiveness of rule-based correction by defining a design where the critical dimension uniformity is used as a measure of the quality of the correction. We also describe the outcome of a model-based correction and the limits of this approach. Finally, we discuss the calculation of accurate full-chip flare maps which are required to implement a rule-based solution. Our results clearly indicate that it is possible to implement an effective flare variation compensation using rule-base correction with current EDA technology, provided that highly accurate full-chip flare maps having the required resolution are available.

Dipole exposure techniques are currently being explored as alternatives to the low k1 problem that hinders the manufacture of sub 100nm logic technology. Recently, there has been a great deal of interest in using a combination of vertical and horizontal dipole exposures capable of producing manufacturing-robust image results for Manhattan features. In this technique, a design is split into two complementary masks that have enhanced contrast at a given dipole imaging condition. The dipole is a strong case of off-axis illumination, and significant resolution enhancement can be achieved, but only for one pattern direction. Complementary dipole exposures are required when dense pitches in horizontal and vertical direction are present. Dipole decomposition approaches that separate vertical and horizontal features in a layout are based on the fact that horizontal features form an improved aerial image with a vertical dipole illumination, and vertical features show the same aerial image improvement with a horizontal dipole illumination. This technique, though conceptually simple, requires a computer algorithm to decompose a design layout into two patterns consisting of features oriented mainly in the horizontal and vertical directions. Some layout features, landing pads or angled lines for example, cannot easily be assigned to a particular mask based on this simple orientation logic. In this work a new approach has been presented in which 45^o decomposition of the pattern is used to improve image contrast, pattern fidelity and focus behavior. The results will be analyzed in terms of contrast, pattern fidelity and focus dependence in order to determine the feasibility of printing manhattan and angled features using a dual dipole approach for sub 100nm processes.

A new pattern analysis concept, referred to as a focus sensitivity model, has one output I"@D that identifies pattern components that are difficult to manufacture during photolithography. I"@D uses the change in modelled intensity with respect to defocus to rapidly determining if a pattern can be robustly manufactured. This paper will demonstrate that the I"@D model output can also be used on patterns without OPC to identify the same manufacturing characteristics found on a pattern that incorporates OPC. This is demonstrated by showing that OPC makes minor changes to the high spatial frequency components of a pattern. Current results show the I"@D analysis of a pattern that has OPC and the same pattern with no OPC is nearly qualitatively identical. The quantitative differences between the two outputs can be removed by changing the I"@D threshold value that is used to quantify pattern quality. However, the spatial frequency changes generated by other RET such as SRAFs is too large and non-linear to be compensated for with a simple change in the I"@D trigger threshold. The ability to remove the OPC correction set from pattern robustness analysis provides a significant advantage; even with the need to use other RET during robustness analysis.

As modern photolithography feature sizes reduce, the use of sub-resolution assist features (SRAFs) to improve the manufacturing process window has become more prevalent. Beyond the assist features placement based on rules, a model based assist feature (MBAF) flow is needed to optimize the shape and the size of SRAFs, so that the process margin of the main features (MFs) is maximized. In the MBAF flow, a vital component is to build an accurate model that specifically checks the printability of SRAFs, which are supposed to leave no trace on wafer. Compared to the traditional optical proximity correction (OPC) model, the SRAF printability check model faces extra challenges, for example, the small size of SRAFs makes their direct transfer to the mask pattern more difficult, the SRAFs are usually not measurable on wafer and the worst-case SRAFs printability is typically at off-nominal conditions. In this paper, we propose an innovative binary modeling method for SRAF printability check model, which does not require the measurement of SRAFs' size on wafer and yet provides accurate prediction of SRAFs printing on wafer. In this modeling method, the binary determination of whether an SRAF prints/does not print (i.e., clean) on wafer was acquired by inspecting the SEMs taken from real wafer measurements. Then the local extrema of the signal intensity around the SRAFs was simulated and used to classify print/clean groups of SRAFs, and a special cost function was designed to separate the print SRAFs and clean SRAFs as much as possible during model calibration.

In modern photolithography, ever smaller critical dimension (CD) budgets require tighter control over the entire process, demanding more accurate practice of optical proximity correction (OPC). In last decade, the model based OPC (MBOPC) has outpaced the rule based OPC (RBOPC) and become widely adopted in semiconductor industry. During the MBOPC process, the physical models are called to compute the signal values at the evaluation points and the design patterns are perturbed such that the final model contours are as close to the targets as possible. It has been demonstrated that in addition to simulating the optics and resist effects, the physical models must accommodate the pattern distortion due to etch process as well. While the etch process may be lumped with optics and resist processes into one model for the 65nm and above nodes, it can no longer be treated as small perturbations on photolithographic effects for more advanced nodes and it is highly desired to build a physics-based etch model formulations that differ from the conventional convolution-based process models used to simulate the optical and resist effect. Our previous studies proposed a novel non-linear etch modeling object in combination with conventional convolution kernels, which simulates the non-optics and non-resist proximity effect successfully. This study examines further the non-linear etch modeling method by checking the different behaviors of N and p doped layers which physically have different etching rates and should be represented differently in etch modeling. The experimental results indicate that the fitting accuracy is significantly improved when the data points are split into N and P groups and calibrated separately. The N and P layer etch models are used in staged MBOPCs and the results are compared with single-layer model as well.

Delta-chrome optical proximity correction (OPC) has been widely adopted in lithographic patterning for semiconductor manufacturing. During the delta-chrome OPC iteration, a predetermined amount of chrome is added or subtracted from the mask pattern. With this chrome change, the change of exposure intensity error (IE) or the change of edge placement error (EPE) between the printed contour and the target pattern is then calculated based on standard Kirchhoff approximation. Linear approximation is used to predict the amount of the proper chrome change to remove the correction error. This approximation can be very fast and effective, but must be performed iteratively to capture interactions between chrome changes. As integrated circuit (IC) design shrinks to the deep sub-wavelength regime, previously ignored nonlinear process effects, such as three-dimensional (3D) mask effects and resist development effects, become significant for accurate prediction and correction of proximity effects. These nonlinearities challenge the deltachrome OPC methodology. The model response to mask pattern perturbation by linear approximation can be readily computed but inaccurate. In fact, computation of the mask perturbation response becomes complex and expensive. A non-delta-chrome OPC methodology with IE-based feedback compensation is proposed. It determines the amount of the proper chrome change based on IE without intensive computation of mask perturbation response. Its effectiveness in improving patterning fidelity and runtime is examined on a 50-nm practical circuit layout. Despite the presence and the absence of nonlinear 3D mask effects, our results show the proposed non-delta-chrome OPC outperforms the deltachrome one in terms of patterning fidelity and runtime. The results also demonstrate that process models with 3D mask effects limit the use of delta-chrome OPC methodology.

Simultaneous source and mask optimization (SMO) has been shown to be an effective method to improve the quality of microlithography aerial imaging. However, the increasing computational complexity is also serious given that current optical proximity correction (OPC) runtime has already been very long. In this paper, we show that SMO can be done efficiently in our previous proposed Abbe-PCA method framework. Different from the Hopkins method, Abbe-PCA directly perform eigen-decomposition on the Abbe sources. In this framework, source modification is easy and efficient. Experimental results show that more than 10X runtime improvement is observed.

Optical proximity correction (OPC) models consist of a large number of components and parameters that must be optimized during model fitting process for best possible matching with empirical data. There are several optimization methods for OPC models. Most of the published methods, if not all, are based on a global optimization method, where all the model parameters are regressed in their search regions to provide a global minimum of the OPC model. However, there are potential risks of overweighting one OPC model component versus another and as a result loosing the physicality of the final model, which reduces model quality in terms of fit and prediction. In this work a stepwise fitting methodology based on staged optimization of the OPC model components is presented. Components are added into an OPC model in the order of more physical to less physical, starting from mask and optics. In each optimization stage a component is optimized using global regression methods and then the optimized parameters are locked and not regressed during further model optimization. The effectiveness of this approach in terms of accurate correction and comparison with global search regression method is demonstrated through computational experiments.

A precise lithographic model has always been a critical component for the technique of Optical Proximity Correction (OPC) since it was introduced a decade ago [1] . As semiconductor manufacturing moves to 32nm and 22nm technology nodes with 193nm wafer immersion lithography, the demand for more accurate models is unprecedented to predict complex imaging phenomena at high numerical aperture (NA) with aggressive illumination conditions necessary for these nodes. An OPC model may comprise all the physical processing components from mask e-beam writing steps to final CDSEM measurement of the feature dimensions. In order to provide a precise model, it is desired that every component involved in the processing physics be accurately modeled using minimum metrology data. In the past years, much attention has been paid to studying mask 3-D effects, mask writing limitations, laser spectrum profile, lens pupil polarization/apodization, source shape characterization, stage vibration, and so on. However, relatively fewer studies have been devoted to modeling of the development process of resist film though it is an essential processing step that cannot be neglected. Instead, threshold models are commonly used to approximate resist development behavior. While resist models capable of simulating development path are widely used in many commercial lithography simulators, the lack of this component in current OPC modeling lies in the fact that direct adoption of those development models into OPC modeling compromises its capability of full chip simulation. In this work, we have successfully incorporated a photoresist development model into production OPC modeling software without sacrificing its full chip capability. The resist film development behavior is simulated in the model to incorporate observed complex resist phenomena such as surface inhibition, developer mass transport, HMDS poisoning, development contrast, etc. The necessary parameters are calibrated using metrology data in the same way that current model calibration is done. The method is validated with a rigorous lithography process simulation tool which is based on physical models to simulate and predict effects during the resist PEB and development process. Furthermore, an experimental lithographic process was modeled using this new methodology, showing significant improvement in modeling accuracy in compassion to a traditional model. Layout correction test has shown that the new model form is equivalent to traditional model forms in terms of correction convergence and speed.

All models currently used for Optical Proximity Correction and related Resolution Enhancement techniques are comprised of an analytical description of the modeled system with coefficients determined by data collected from the physical process. The analytical model is normally based on the Hopkin's approximation of the system because this approximation allows the reticle to be a variable in the exposure system. The analytical component of the model contains terms such as numerical aperture, partial coherence, and wavelength, all of which are physical parameters that can be directly read from the equipment used to generate the empirical process data. Therefore, these physical parameters can be directly used in the process model and do not need to be modified. One case example of a physical parameter is the illuminator shape. In an annular exposure system, the center of the exposure system is blocked to allow illumination by high order illumination components. The annular shape can be achieved in different manners. The scanner manufacturer can use a shape cut in a metal form to achieve an annular illumination condition or the scanner manufacturer can use a lens system to achieve the same illumination condition. Both of these systems have the same inner and outer diameters, resulting in the same annulus and therefore the same illumination technique. However, experimental data show that for the exact same setting values, the annular illumination shape is detectably different. This is a first order system difference that is the result of different implementation methods. Further differences can be found due to scanner to scanner variations in either lens shape or aperture shape. These differences create a need for physical parameters to be regressed during fitting of empirical data to the analytical model. This paper will discuss the need to regress what initially appear to be constant physical parameters during the model fitting process. The study will use equipment variability information to demonstrate the range of physical constant impact upon the accuracy of a process model.

Because of the ever-decreasing feature size in modern photolithography, the complexity of pattern increases dramatically and tape-out time becomes prolonged. It is desirable to transfer OPC process into optical model for the sake of time. In this report, we introduce a novel method of calculating the OPC effect by modifying the optical model, which is equivalent to transferring the OPC effect into the optical model

In the modern photolithography simulation, the computation demand on resolution enhancement techniques (RETs) and optical proximity corrections (OPCs) is proportional to the simulation runtime of the model, which is dependant on the number of the kernels retained with the constrain of the model accuracy. Thus, it is essential to retain as few kernels as possible in the model calibration. Traditionally, the kernels are retained based upon their contribution to the aerial image, which is solely determined by the magnitudes of the eigenvalues. This method works well for arbitrary photolithography masks. However, real masks are never arbitrary and random. Instead, they have regular shapes and arrangements as governed by design rules, indicating the contributions from the retained kernels are statistically correlated to each other. By taking such correlations into account, the system representation can be improved to contain fewer Kernels for constant model accuracy. In this paper, the mathematical derivation of the pattern correlation concept is discussed and the concept is applied to a poly-silicon layer illuminated by a Quasar optical system with λ = 193 nm and NA = 0.8. Significant improvement of model kernel representation is observed, 12 improved kernels vs 20 original kernels, and the new methodology is justified by comparing the difference of the aerial image intensities between the full kernel representation and the retained kernels representation at sampling points.

Process depth of focus analysis has always been an important method for determining semiconductor integrated circuit manufacturability. This is becoming even more apparent as process nodes continue to shrink and more aggressive Resolution Enhancement Technology (RET) techniques are adopted to help retain process latitude. Process window is one of the most important factors in improving yield and reducing production cost. Therefore, pattern verification prior to mask tape-out is essential to save development time, and cost is extremely important. The concept of focus-sensitive hotspot detection has been recently introduced using a Manufacturing Sensitivity Model (MSM). As the MSM interacts with the pattern, the model produces output that judges the quality of the through-process correction in a single piece of interpreted data. The MSM output can then be readily analyzed to find process sensitive patterns. In this study, we will apply a process focus sensitivity detection algorithm to various designs using Focus Sensitive Model (FSM). The results will be compared to conventional depth of focus analysis techniques. The goal is to understand the relationship between the focus sensitivity and the CD error variations. This will be used to understand if focus-sensitive hotspot detection using FSM can be applied for verifying RET process qualities.

Sub-resolution Assist Features (SRAFs) are powerful tools to enhance the focus margin of drawn patterns. SRAFs are sized so they do not print on the wafer, but the larger the SRAF, the more effective it becomes at enhancing through-focus stability. The size of an SRAF that will image on a wafer is highly dependent upon neighboring patterns and models of SRAF printability are, at present, unreliable. Conservative SRAF rules have been used to ensure that SRAFs never print on a pattern. More accurate models of SRAF printing should allow SRAF rules to be relaxed, resulting in more effective SRAF placement and broader focus margins. The process models that are used during Optical Proximity Correction have never been able to reliably predict which SRAFs will print on a pattern. This appears to be due to the fact that OPC process models are generally created using data that does not include subresolution patterns. In addition, the definition of a printing SRAF is not clear, as it can range from a photoresist film left on a wafer to a pattern that is transferred to the substrate during the etch process. This paper will demonstrate a model that identifies SRAFs which appear in photoresist and those which survive the etch step.

Immersion lithography and multiple exposure techniques are the most promising methods to extend lithography manufacturing to the 45nm node. Although immersion lithography has attracted much attention recently as a promising optical lithography extension, it will not solve all the problems at the 45-nm node. The 'dry' option, (i.e. double exposure/etch) which can be realized with standard processing practice, will extend 193-nm lithography to the end of the current industry roadmap. Double exposure/etch lithography is expensive in terms of cost. throughput time, and overlay registration accuracy. However, it is less challenging compared to other possible alternatives and has the ability to break through the κ 1 barrier (0.25). This process, in combination with attenuated PSM (att-PSM) mask, is a good imaging solution that can reach, and most likely go beyond, the 45-nm node. Mask making requirements in a double exposure scheme will be reduced significantly. This can be appreciated by the fact that the separation of tightly-pitched mask into two less demanding pitch patterns will reduce the stringent specifications for each mask. In this study, modeling of double exposure lithography (DEL) with att-PSM masks to target 45-nm node is described. In addition, mask separation and implementation issues of optical proximity corrections (OPC) to improve process window are studied. To understand the impact of OPC on the process window, Fourier analysis of the masks has been carried out as well?

Negative etch bias is often used to decrease the minimum linewidth beyond what is possible with lithography alone, for example 110 nm minimum CD in resist and 70 nm minimum CD after etch. If the minimum space that can be opened in resist is, for example, 30 nm a true 70 nm half-pitch can be achieved when an etch shrink is employed. Due to iso-dense bias and other proximity effects, however, positive etch bias can also occur. This leads to the unfavorable situation where litho must print lines in resist smaller than the lines in the final post-etch silicon. Due to positive etch bias, among other factors, it is possible to create a configuration that can be realized from the point of view of etch, but can not be created due to photolithography or mask constraints. Specific trouble spots include boundary regions which transition between one set of DRC rules and another. With a new highly accurate etch model, problematic configurations can be identified and used to modify the design to make the etch, photolithography, and mask construction processes realizable. This paper will demonstrate unrealizable pattern conditions that can be found using a non-linear etch model for OPC[R], leading to layout configuration changes which improve the mask construction and photolithography processes.

Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to fully control those interactions, different processes typically have variations that can cause significant deviation of the properties of printed integrated circuit. However, if a process variation is predictable and systematic, OPC techniques can successfully be applied to compensate for those process variations by modifying the layout. One such process variation relates to topographic variation on a wafer surface, which can cause defocusing during an optical lithography process. The nominal-focus aerial image of the layout should ideally be coincides with the wafer surface. In reality, topographic variation on the wafer surface can cause portions of the wafer's surface to be deviated from the nominal focal plane. This can result in defocused aerial image on the wafer causing line width variation of transistor gates during manufacturing process. This problem can be minimized by using anti-reflective coatings as well as differential biasing of the n-type, n-type, and field polysilicon. However, even after application of these two techniques, some residual error remains because the ARC layers are not fully absorbent. Moreover, the biasing techniques also induce process problems at the transition point between the biases and unbiased gate regions. In fact, required applied biases gradually become difficult to manage during technology node migrations. This paper presents a system that accurately determines critical dimension layout by compensating for the effects of topography variation on the performance of an optical lithography process. In this study, a model form and its empirical calibration process have been presented.

For low k1 lithography, more aggressive OPC is being applied to critical layers, and the number of mask layers with OPC treatments is growing rapidly. The 130 nm, process node required, on average, 8 layers containing rules- or model-based OPC. The 90 nm node will have 16 OPC layers, of which 14 layers contain aggressive model-based OPC. This escalation of mask pattern complexity, coupled with the predominant use of vector-scan e-beam (VSB) mask writers contributes to the rising costs of advanced mask sets. Writing times for OPC layouts are several times longer than for traditional layouts, making mask exposure the single largest cost component for OPC masks. Lower mask yields, another key factor in higher mask costs, is also aggravated by OPC. Historical mask set costs are plotted below. The initial cost of a 90 nm-node mask set will exceed one million dollars. The relative impact of mask cost on chip depends on how many total wafers are printed with each mask set. For many foundry chips, where unit production is often well below 1000 wafers, mask costs are larger than wafer processing costs. Further increases in NRE may begin to discourage these suppliers' adoption to 90 nm and smaller nodes. In this paper we will outline several alternatives for reducing mask costs by strategically leveraging dimensional margins. Dimensional specifications for a particular masking layer usually are applied uniformly to all features on that layer. As a practical matter, accuracy requirements on different features in the design may vary widely. Take a polysilicon layer, for example: global tolerance specifications for that layer are driven by the transistor-gate requirements; but these parameters over-specify interconnect feature requirements. By identifying features where dimensional accuracy requirements can be reduced, additional margin can be leveraged to reduce OPC complexity. Mask writing time on VSB tools will drop in nearly direct proportion to reduce shot count. By inspecting masks with reference to feature-dependent margins, instead of uniform specifications, mask yield can be effectively increased further reducing delivered mask expense.

In this work, the preliminary results of the holographic imaging technique (HIT) as a resolution enhancement technique (RET) hybrid inverse lithography technique (ILT) optical proximity correction mask correction is presented. The proposed technique is based on the illumination system and free space propagation of the mask. First, an in-line hologram (Gabor hologram) is generated by computing the target pattern diffraction pattern. Second, the computed hologram is synthesized as pattern contours to form a mask for a conventional optical system. In this study, a simple HIT corrected mask is validated with compact lithographic exposure system mathematical model for demonstrating the preliminary validity of the proposed method. Future plans to validate HIT for the most aggressive process nodes are proposed. The proposed technique has not been exercised against conventional ILT or other RET techniques, and does not contain analysis of resolution improvement achievable with those techniques.

In modern photolithography, optical proximity correction (OPC) has been widely adopted to improve the image fidelity of the mask on silicon wafer and, hence, improve the yield and the performance of integrated circuits. In recent years, model based optical proximity correction (MBOPC) has evolved from a nice-to-have feature to a must-have feature, especially, for the advanced nodes, 90 nm and beyond. The purpose of MBOPC is to adjust the designed pattern on the photomask to introduce mask perturbations, such that the layout printed on the wafer is as close as possible to the drawn layout. Before MBOPC is conducted on the full chip, a high quality and yet compact OPC model must be built, which simulates the photolithography process accurately. A high quality OPC model apparently relies on the quality of the empirical critical-dimension data in terms of both metrology noisiness and layout representativeness. Although more measurements on a large number of patterns will keep overall noise at lower levels and provide better input to OPC modeling, it is crucial to choose the representative patterns wisely and minimize the redundancy of gauges due to the limited metrology budget and the requirement of shortening turnaround time. In this article, the authors propose a method that checks the linear response of the optical signal on the one-dimensional (1D) patterns and selects the most representative patterns among all possible 1D structures.

As the leading-edge photolithography is approaching rapidly closer to the theoretical optical resolution limit, model based optical proximity correction (MBOPC) has evolved from a nice-to-have feature to a must-have feature. The purpose of MBOPC is to adjust the designed pattern on the photomask to introduce mask perturbations such that the layout printed on the wafer is as close as possible to the drawn layout. Before MBOPC is performed across a full chip, a process model is calibrated based upon manufacturing process data measured from scanning electron microscope (SEM) pictures of test patterns. The process model is usually composed of two components, signal intensity and threshold, and the intersections of these two components determine the layout contours that will be printed on wafer. It is found that the accuracy of the process model is improved as more kernels are used to represent the model. However, pattern correction runtime is proportional to the number of kernels used for the model, thereby introducing a constraint to incorporate least number of kernels in the process model. In this study, a novel method of computing the signal change in the MBOPC process is proposed, which is used to maintain the correction accuracy and reduce the MBOPC runtime.

In modern photolithography, model based optical proximity correction (MBOPC) has evolved from a nice-to-have feature to a must-have feature and has been widely adopted to improve the process throughput. The purpose of MBOPC is to adjust the designed pattern on the photomask to introduce mask perturbations such that the layout printed on the wafer is as close as possible to the drawn layout. In regular MBOPC process, the polygons are dissected into segments and corrections are conducted segment by segment. While it is relatively easy and straightforward to find the optimal segment size for most one-dimensional features, it is hard for many two-dimensional features, especially line-end areas. By solving a few segments around line-end areas together, multisegment solver (MSS) showed a good contour match. However, this method is expensive on model calculation, as there is more than one segment size to be optimized and a large number of searching iterations is needed, which makes its runtime sensitive to the n...

Because of the ever-decreasing feature size in modern photolithography, the complexity of semiconductor patterns continues to increase dramatically, resulting in prolonged tape-out times. The most time-consuming process in the tape-out flow is model-based optical proximity correction (OPC), which employs two components: a process model and a recipe. The process model predicts how the manufacturing process will behave at a given location on a wafer, whereas the recipe controls how the model information is used to modify the pattern. The recipe uses the model multiple times for each fraction of a polygon in a semiconductor device pattern, resulting in hundreds of billions of complex and time-consuming calculations. To analyze a design-team-drawn device pattern for semiconductor manufacturability, these tape-out calculations need to be performed. This study is designed to reduce the semiconductor pattern manufacturing analysis time by creating an OPC recipe simulation in the process model for use in rapid analysis and filtering of the drawn semiconductor design. In this study, the authors introduce a method of calculating the OPC effect by modifying the optical model, which is equivalent to transferring the OPC effect into the process model.

Isofocal patterns produce the most ideal manufacturing conditions on a reticle, however, most semiconductor designs contain few isofocal features. A new way of looking at defocus conditions based on the change in intensity with respect to nominal focus [L. S. Melvin III et al., J. Vac. Sci. Technol. B 23, 2631 (2005)]—referred to as IΔ—can be used to resize the target pattern to isofocal dimensions. The pattern is quantitatively analyzed using IΔ to find modified pattern shapes that give isofocal target patterns for optical proximity correction and/or resolution enhancement techniques. The target pattern is then made isofocal by resizing the pattern to the modified shape prior to the use of optical proximity correction and/or resolution enhancement techniques. Results of this concept demonstrate excellent improvement in the feature robustness of different features at various defocus conditions. The proposed isofocal targeting method can be applied to layers where trade-offs between pattern shape and final...

As semiconductor manufacturing moves to smaller geometries, the existing methodologies for verifying the manufacturability of a design are increasingly cumbersome. Current practice is to use geometric “design rules”—such as minimum spacing and width constraints—to identify design configurations that are not manufacturable or likely to reduce yield. One manufacturing property that is particularly difficult to capture accurately with geometric rules is the robustness of the layout configuration with respect to variation through the lithographic process window. The nonlinear characteristics of optical partial coherence effects, particularly strong in modern exposure systems with off-axis illumination, are currently incorporated into the design rules through an exhaustive empirical process. The resulting design rules can be overly conservative to insure complete problem pattern capture, and this may result in unnecessary restrictions on the design that reduce the layout density or interfere with circuit perfo...