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A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5 ?m CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5 mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900 e. The power dissipation without the output buffer is about 2.6 mW.

This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology. The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit. The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array. The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function. The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage. Defective pixel correction is also implemented in this circuit. The simulation results show that the TDI function is correctly implemented and the linearity is improved from 96.15% to 97.70% (without the common output stage) at the expense of a little increase of power dissipation.

A fast-settling, temperature-insensitive voltage buffer is analyzed and designed. Class AB output stage in the buffer leads to high slew rate with relatively low power dissipation. The current switch not only sets the quiescent current of the output transistors, but also compensates the variation of Vth with temperature, which makes the buffer workable in a wide range of temperature. Simulation results show that the 0.1% settling time with 2V input step and 2OpF load is always less than 165ns when the temperature varies from 0°C to 100°C while the dissipation is less than 3mW. The die area without pads in 0.5um CMOS process is 350* 150um2.

A design model is proposed to exactly simulate operating principles of gate-coupling NMOS (GCNMOS) ESD protection circuit under ESD stress. Using this model, adequate coupling capacitor C/sub n/ and coupling resistor R/sub n/ can be calculated to improve the efficiency of GCNMOS ESD protection circuit.

An op-amp with a push-pull output stage for infrared focal plane array (IRFPA) readout integrated circuit (ROIC) is described in this paper. It works in the class AB mode with little die area. The op-amp is simulated by the SMIC 0.35-/spl mu/m CMOS process. The circuit is designed to operate from a single 5 V power and drive a capacitive load of 15 pF. The unity gain-bandwidth (GBW) is 30 MHz. the rising slew rate (SR) 34 V/s. and the falling slew rate (SR-) 39 V/s. The common-mode input and the output swing are almost 5 V.

This paper presents a precise compensated bandgap reference without resistors. This bandgap reference uses an improved voltage-transfer unit instead of resistors. A current proportional to T/sup /spl alpha// (/spl alpha/ is a constant) is produced to compensate for the higher order of the V/sub EB/. This bandgap reference is based on 0.5/spl mu/m n-well CMOS technology. The supply voltage is 5V, working from -10/spl deg/C to 90/spl deg/C, the effective temperature coefficient of the output voltage is only 7 ppm//spl deg/C, and the maximum power dissipation is 0.76mW.

A correlated double sample (CDS) stage design is proposed for CMOS image readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive switch capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports integration-while-read (IWR) mode, then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

Microprocessors are extremely versatile and complexity that present significantly test challenges. This paper describes a retargetable functional test platform system design for various microprocessors. Characterized by configurable test environment generator, retargetable assembler and strong ATPG the platform system could automatically produce different test environment and assemble out relative test codes to adapt to the microprocessor under test. Experiments show that the platform system works correctly, flexibly and efficiently.

A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 mW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 mW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 mm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.

A design of a 32-bit microprocessor core PKURS002 for embedded system is presented in this paper. It consumes much less power yet remains the high performance, compared with its prior PKURS001. The core employs low power design techniques at the controller, data path and internal memorial cells. The controller employs distributed logic instead of centralized one to reduce the signal transition by enlarging the self-loop. A new algorithm LSA (Logarithmic Skip Adder) has been provided to implement ALU and bit-split technique is applied to the structure of register file. The core is described by HDL and verified on 0.35 mm CMOS process. Result shows it reduce 30% power consumption compared with its predecessor at the same performance.

This paper describes the optimized design of two kinds of operational amplifier (OPA) in the column readout circuit and output buffer of focal plane array (FPA) circuit, based on 1.2 /spl mu/m double poly double metal (DPDM) CMOS process. Hspice simulation shows that the OPA for column readout circuit works with GBW of 0.9 MHz, power of 35 /spl mu/W, settling time of 3 /spl mu/s. The OPA in output buffer can work at GBW of 12 MHz, power of 1.8 mW, settling time of 144 ns, which may support the dimension of FPA as large as 400*400 pixels at 30 frames/sec.

Thispaperdescribesan8-bit125MHzlow-powerCMOSfully-foldinganalog-to-digitalconverter(ADC). A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5 m CMOS technology and occupies a die area of 2 × 1.5 mm 2 . The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply. In this paper, a novel mixed-averaging distributed T/H circuit is proposed which improves the accuracy and provides a better tradeoff between accuracy, size and power dissipation. In addition, a novel bit synchronization architecture is pre- sented to reduce the number of comparators, and this architec- ture employs folding circuits to produce a bit synchronization signal. Therefore, folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchroniza- tion block. A special low-power CMOS ADC is designed and only 22 comparators are used in the whole ADC. The ADC is implemented in 0.5 m CMOS technology. Measured results show that the power dissipation of the ADC is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

The hysteresis loops observed in the drain current vs. voltage characteristics of metal-semiconductor field-effect transistors (MESFET's) fabricated on semi-insulating GaAs by ion implantation were investigated as a function of the sweep frequency and of the temperature. A model was developed to correlate the extent of the looping to the characteristics of the deep-level traps in the channel. Experimental results were compared with the channel deep-level transient spectroscopic results on the same MESFET.