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This paper reports on the status of a comprehensive ten-year research and development effort toward hybrid system-in-foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion in and on a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity and form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on- and off-chip implementation of sensor, actuator, microwave, and energy supply components are addressed.

This paper presents the design, fabrication and characterization of digital logic gates, flip-flops and shift registers based on low-voltage organic thin-film transistors (TFTs) on flexible plastic substrates. The organic transistors are based on the p-channel organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and have channel lengths as short as 5 μ m and gate-to-contact overlaps of 20 μ m. The organic TFT is modeled which allows us to simulate different logic gate architectures prior to the fabrication process. In this study, the zero-VGS, biased-load and pseudo-CMOS logic families are investigated, where their static and dynamic operations are modeled and measured. The inverter and NAND gates use channel length of 5 μ m and operate with a supply voltage of 3 V. Static and dynamic master-slave flip-flops based on biased-load and pseudo-CMOS logic are designed, fabricated and characterized. A new design for biased-load dynamic flip-flops is proposed, where transmission gate switches are implemented using only p-channel transistors. 1-stage shift registers based on the new design and fabricated using TFTs with a channel length of 20 μ m operate with a maximum frequency of about 3 kHz.

Boundary layer evolution in response to diurnal forcing is manifested at the mesobeta and smaller scales of the atmosphere. Because this variability resides on subsynoptic scales, the potential influence upon convective storm environments is often not captured in coarse observational and modeling datasets, particularly for complex physical settings such as coastal regions. A detailed observational analysis of diurnally forced preconditioning for convective storm environments of South East Queensland, Australia (SEQ), during the Coastal Convective Interactions Experiment (2013–15) is presented. The observations used include surface-based measurements, aerological soundings, and dual-polarization Doppler radar. The sea-breeze circulation was found to be the dominant influence; however, profile modification by the coastward advection of the continental boundary layer was found to be an essential mechanism for favorable preconditioning of deep convection. This includes 1) enhanced moisture in the city of Brisbane, potentiality due to an urban heat island–enhanced land–sea thermal contrast, 2) significant afternoon warming and moistening above the sea breeze resulting from the advection of the inland convective boundary layer coastward under prevailing westerly flow coupled with the sea-breeze return flow, and 3) substantial variations in near-surface moisture likely associated with topography and land use. For the 27 November 2014 Brisbane hailstorm, which caused damages exceeding $1.5 billion Australian dollars (AUD), the three introduced diurnal preconditioning processes are shown to favor a mesoscale convective environment supportive of large hailstone growth. The hybrid high-precipitation supercell storm mode noted for this event and previous similar events in SEQ is hypothesized to be more sensitive to variations in near-surface and boundary layer instability in contrast to contemporary supercell storms.

Flexible electronics combined with new materials and fabrication processes offer unique characteristics such as mechanical flexibility, thin-form factor, large area scaling feasibility, and adaptability to irregular surfaces. In this work, a smart electronic skin adopting the hybrid system-in-foil concept is designed to monitor the uniaxial bending of a robotic gripper. The newly designed smart skin contains an array of printed strain gauges, organic thin-film transistor (TFT) addressing circuits and a 20 μm ultra-thin silicon readout chip, all integrated on the same polymeric foil. The silver-ink printed strain gauges achieve a relative resistance sensitivity ΔR/R of 2% and a gauge factor of 2. In addition, the organic TFT multiplexer containing a three-stage shift register and analogue switches operate at a frequency of 100 Hz and a supply voltage of 3 V. The ultra-thin silicon chip provides the functions of system control, strain gauge readout, analogue-to-digital conversion and serial communication.

Current electronic systems and circuits possess approximately 80 % of passive components. Thus, high performance integrated silicon-based passive components with high density are required to reduce the overall cost and bulkiness of the systems. This paper presents the development of high-density ultra-thin 3D capacitors in silicon, one of the important passive components exploited in approximately all the circuits for SiP, 3D-integration and flexible systems. The 3D structure is achieved by using deep reactive ion etching (DRIE) process. The substrate and the polysilicon act as the two electrode plates with silicon dioxide as the dielectric. Two designs with different pitches are investigated with successful back-grinding of the substrate to 50$\mu$ m thin and 22$\mu$ m ultra-thin singulated capacitors. Capacitive densities of 36.25 nF/mm 2 and 28.75 nF/mm 2 over a frequency bandwidth of 100 KHz are presented. The reduced thickness and flexible nature of these ultra-thin capacitors (

The southeast Queensland (SEQ) region of Australia is recognised for frequent thunderstorms documented through numerous studies including high-impact severe thunderstorm cases which have caused insured losses exceeding $1 billion AUD. Despite a modest body of scientific literature, basic questions regarding the role of climate, synoptic and local-scale (

Understanding wildfire-atmosphere interactions is key to improved accuracy of predictions of wildfire behavior. This is needed for improved preparedness to mitigate loss of life and property during wildfire events, particularly for situations with strong fire-atmosphere coupling. Here we present observations from the passage of a cold front over the Sir Ivan Dougherty wildfire on February 2017 in eastern Australia. We demonstrate that an increase in near-surface atmosphere moisture associated with the cold front, when combined with changes in fire behavior at that time, led to reduced thermodynamic stability that helped to trigger a thunderstorm. This fire-trigged supercell thunderstorm produced lightning, while radar observations identified a mesocyclonic circulation within the pyrocumulonimbus, similar to a supercell thunderstorm. Results highlight the need to monitor the thermodynamic properties of air masses approaching wildfires and the rapid evolution of pyrocumulonimbus, which may develop mesocyclone characteristics. Weather radar offers the most effective capability to achieve such insights.

Hybrid System-in-Foil exploits the complementary benefits of integrating embedded silicon chips with on-foil passive and active electronic components. In this work, the design, fabrication and characterization of three on-foil components, namely a humidity sensor, near field communication antenna and organic thin-film transistors, are investigated.

This paper reports on the status of a comprehensive ten-year research and development effort towards Hybrid System-in-Foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion attached on or laminated in a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity or form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on- and off-chip implementation of sensor, actuator, microwave and energy supply components are discussed.

This paper presents relative humidity sensors based on electrochemical and capacitive principles. The sensors are fabricated on flexible polymer substrates, which are used for ultra-thin chip embedding. The electrochemical sensor consists of spin-coated nanosheets, which shown huge range (about 5 orders of magnitude) and fast response (< 2 s). The sensor film thickness as well as ionic conductivity change upon moisture absorption. The measured sensor relative conductance change on the flexible substrate is 368%. In addition, a 3-pm thick conventional capacitive sensor is fabricated on the polymer substrate, together with a humidity-insensitive reference capacitor. The measured sensor relative sensitivity is about 75% with a response time of about 6 s. Finally, a sensor system-in-foil is demonstrated using discrete components of the ultra-thin capacitive sensor and a 30-pm thick capacitance-to-digital readout chip.

This paper presents analysis of the charge storage behavior in organic thin-film transistors (OTFTs) by means of admittance characterization, compact modeling, and 2-D device simulation. The measurements are performed for frequencies ranging from 100 Hz to 1 MHz and bias potentials from zero to -3 V on top-contact OTFTs that employ air-stable and high-mobility dinaphtho-thieno-thiophene as the organic semiconductor. It is demonstrated that the dependence of the intrinsic OTFT gate-source and gate-drain capacitances on the applied voltages agrees very well with Meyer's capacitance model. Furthermore, the impact of parasitic elements, including fringe current and contact impedance, is investigated. The parameters used for the simulation and modeling of all the dynamic characteristics correspond closely to those extracted from static measurements. Finally, the implications of the admittance measurements are also discussed relating to the OTFTs dynamic performance, particularly the cutoff frequency and the charge response time.

Bottom-gate, top-contact (inverted staggered) organic thin-film transistors with a channel length of 1 μm have been fabricated on flexible plastic substrates using the vacuum-deposited small-molecule semiconductor 2,9-didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C10-DNTT). The transistors have an effective field-effect mobility of 1.2 cm2/V s, an on/off ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 ns per stage at a supply voltage of 3 V. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V.

This paper presents S-parameter characterization and a corresponding physics-based small-signal equivalent circuit for organic thin-film transistors (OTFTs). Furthermore, the impact of misalignment between the source/drain contacts and the patterned gate on the dynamic TFT performance is explored and a simple method to estimate the misalignment from the measured S-parameters is proposed. An excellent fit between theoretical and experimental S-parameters is demonstrated. For this study, OTFTs based on the air-stable organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) having a channel length of 1 μm and a gate-to-contact overlap of 5 or 20 μm and being operated at a supply voltage of 3 V are utilized. The intentional asymmetry between gate-to-source and gate-to-drain overlaps is precisely controlled by the use of high-resolution silicon stencil masks.

International audience; A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

A 3.3 V 6-bit binary-weighted current-steering digital-to-converter converter (DAC) using low-voltage organic p-type thin-film transistors (OTFTs) is presented. The converter marks records in speed and compactness owing to an OTFT fabrication process that is based on high-resolution silicon stencil masks. The chip has been fabricated on a glass substrate and consumes an area of 2.6× 4.6 mm2. The converter has a maximum update rate of 100 kS/s and a maximum output voltage swing of 2 V. The measured DNL and INL at an update rate of 1 kS/s are - 0.69 and 1.16 LSB, respectively. A spurious-free dynamic range (SFDR) of 32 dB has been measured for output sinusoids at 31 Hz (update rate of 1 kS/s) and 3.1 kHz (update rate of 100 kS/s).

This paper presents a novel implementation of variable uniaxial mechanical stress model to be used with DC circuit simulation, e.g. using BSIM3v3 transistor model. Based on transistor measurements under various uniaxial stress conditions two stress-dependent parameters are identified, namely the carriers mobility and to a lesser extend the carrier saturation velocity. The effect of the parasitic source/drain resistance on the piezoresistive coefficient determination is addressed in detail. Using the fundamental piezoresistive coefficients, the model has implemented a general relation to calculate the coefficients for arbitrary directions of current and stress in the (0 0 1) silicon (Si) plane. The extended transistor model allows for simulating the effect of uniaxial stress on any MOSFET geometry, under different operation conditions and for any combination of the drain current and stress orientations in the (0 0 1) silicon (Si) plane. The method proposed in this paper is validated by static and dynamic stress-dependent simulations and comparison with experimental data. The method is simulator-independent and can be adapted to other bulk CMOS technologies including SOI processes.

System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin (

This work presents a compact wide-range fully integrated sinusoidal signal generator for in vivo Electrochemical Impedance Spectroscopy applications. The circuit is based on a novel architecture combining aspects of direct digital synthesis and interpolation digital to analog conversion. The signal generator demonstrates very precise frequency tuning and high spectral purity, while offering a simple architecture and an uncomplicated clocking scheme. The circuit is fabricated using a 0.5µm sea of transistors CMOS process and occupies 0.32mm2 of active die area. Consuming 110µA at a 3V supply, the circuit covers eight decades of frequency from 1mHz to 100kHz and meets the necessary low energy and high precision requirements for implantable bio-diagnostics.

A process for the fabrication of integrated circuits based on bottom-gate, top-contact organic thin-film transistors (TFTs) with channel lengths as short as 1 µm on flexible plastic substrates has been developed. In this process, all TFT layers (gate electrodes, organic semiconductors, source/drain contacts) are patterned with the help of high-resolution silicon stencil masks, thus eliminating the need for subtractive patterning and avoiding the exposure of the organic semiconductors to potentially harmful organic solvents or resists. The TFTs employ a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs and circuits to operate with voltages of about 3 V. Using the vacuum-deposited small-molecule organic semiconductor 2,9-didecyl-dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (C10 DNTT), TFTs with an effective field-effect mobility of 1.2 cm2/Vs, an on/off current ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 nsec per stage at a supply voltage of 3 V have been obtained. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V. In addition to flexible ring oscillators, we have also demonstrated a 6-bit digital-to-analog converter (DAC) in a binary-weighted current-steering architecture, based on TFTs with a channel length of 4 µm and fabricated on a glass substrate. This DAC has a supply voltage of 3.3 V, a circuit area of 2.6 × 4.6 mm2, and a maximum sampling rate of 100 kS/s.

This letter presents the first comprehensive experimental studies on the frequency response of staggered low-voltage organic thin-film transistors (OTFTs) using S-parameter measurements. The transistors utilize air-stable dinaphtho-thieno-thiophene as the organic semiconductor with various channel lengths and gate overlaps. A peak cutoff frequency of 3.7 MHz for a channel length of 0.6 μm, gate overlap of 5 μm, and a supply voltage of 3 V is achieved. In view of the low supply voltage and air-stability, this result marks a record achievement in OTFT technology. The channel length dependence of the cutoff frequency is described in a compact model and a close correspondence to the measured data of OTFTs with variable device dimensions is shown. Moreover, the cutoff frequencies at different gate biases are found to be proportional to the dc transconductance.

Manufacturing ultra-thin chip is an emerging field in semiconductor technology that is driven by 3-D integrated circuits and flexible electronics. Unlike bulk silicon (Si) chips with thickness greater than 400 μm, the thermal management of ultra-thin Si chips with thickness smaller than 20 μm is challenging due to the increased lateral thermal resistance implying stringent cooling requirements. Therefore, a reasonable prediction of temperature gradients in such chips is necessary. In this work, a thermal chip is implemented in an ultra-thin 0.5 μm CMOS technology to be employed in surface steady-state and transient temperature measurement. Test chips are either packaged in a Pin Grid Array (PGA) ceramic package or attached to a flexible polyimide substrate. The experimental results show an on-chip temperature gradient of ∼15 °C for a dissipated power of 0.4 W in the case of the PGA package and ∼30 °C for the polyimide substrate. The time constants are ∼50 s and ∼1 s for the PGA and the polyimide packages respectively. The measurements are complemented by FEM simulations using ANSYS 14.5 workbench and spice simulations using an equivalent lumped-component thermal circuit model. The lumped-element thermal circuit model is then used for the surface temperature prediction, which is compared to measurement results.

The goal of the SCINET project is to investigate the applicability of the scalable-coherent-interface (SCI) for data-acquisition systems in large-scale fusion-reactor experiments. SCI is a standardized, high-speed interconnect for peripheral devices, processors, memories, PCs and workstations that provides for a distributed shared memory with optional cache coherence between computing nodes. Up to 64 K SCI nodes can be closely coupled in one or more rings that are concatenated via SCI switches. In SCINET, it is investigated how data-acquisition computers can be efficiently connected with each other and with their sensors and actuators by means of SCI, what topological structure the network should have, and which bandwidth and latency can be expected. Test stands were established as a sample SCI-based data-acquisition system that showed up to 45 MB s -1 of throughput and < 5 μs latency for end-to-end data transfers.

Organic electronics are gaining increasing interest and attention in electronic device fabrication due to cost advantages and low process manufacturing temperatures, which allow the use of mechanically-flexible polymeric substrates. Different patterning techniques for Organic Thin Film Transistors (OTFT) with sub μm channel length are currently under investigation like inkjet-printing, nanoimprint, optical- and e-beam lithography. This paper describes a new approach for OTFT fabrication by device patterning with Si stencil lithography. This high resolution shadow mask technique allows the parallel patterning of sub μm features without the use of photosensitive resists or chemical solvents, which could lead to a degradation of the sensitive organic semiconductor layer. At first the device pattern is etched into a thin Si membrane layer, creating design-specific sub μm features. Subsequent this stencil mask is aligned and clamped to the substrate and material is deposited through the stencil apertures forming the desired device pattern onto the substrate. By repeating this sequence with different deposition materials a classical top contact TFT architecture with a gate electrode, gate dielectric, organic semiconductor and source drain contacts can be achieved.

System-in-foil (SiF) technology calls for low cost, ultra-thin and, high-performance high-voltage transistors to satisfy the need for high-voltage driving capability in many of the emerging flexible display technologies. An ultra-thin (20 μm) N-type lateral DMOS transistor (N-LDMOS) in Chipfilm™ technology, developed for this application, is presented. The fabrication process is fully compatible with conventional high-voltage CMOS technology using shallow trench isolation (STI). The N-LDMOS has a breakdown voltage >100 volts with a maximum drain current of 4.4 mA at a channel length of 9 μm and a width of 50 μm. At drain voltage V ds = 100 V, self-heating causes a reduction in drain current up to 19% on a silicon carrier wafer and 35% on polyimide (PI) foil relative to the drain current without self heating, thus indicating power dissipation to be one of most serious issues in flexible electronics.

A simulation case study to indicate advancement opportunities for a low-voltage complementary organic thin-film transistor (OTFT) technology is presented. A 3-bit unary current-steering digital-to-analog converter (DAC) is used as circuit test vehicle. The study is based on accurate agreement of simulated and measured data, owing to optimized DC/AC SPICE models for both p- and n-type OTFTs. The model is validated by transient measurements of the driving complementary logic thermometer decoder up to a maximum operating frequency of 1 kHz. The case study shows that an improved circuit performance will result from a smaller source and drain overlap with the gate electrode particularly in the n-type OTFT, from avoiding metal interconnect crossings, and from increasing the channel carrier mobility of the n-type OTFT.

Organic thin-film transistors (OTFT) processed at low-temperatures offer prospects for a vast number of integrated circuit applications in mechanically flexible, inexpensive, large-area and biomedical electronics [1]. In addition, the low-voltage operation capability of recent OTFTs makes them well-suited for battery-powered or radio frequency-coupled portable devices [2]. In such applications, data conversion to interface the digital processors with the analog world is an essential necessity. Here, we demonstrate a compact 6b current-steering D/A converter (DAC) circuit, built in OTFT technology, which is 1000× faster and 30× smaller than the previously published data for a 6b DAC [3]. These considerable improvements result from an OTFT fabrication process based on silicon stencil masks that provide submicron channel length capability and excellent transistor matching [4], [5].

Rapid advancements in the field of flexible display have lifted expectations of the availability of full-flexible display products in near future. A full-flexible, paperlike display requires ultra-thin driver chips embedded in the same flexible substrate. This reduces external connections and cost of product, and it increases system reliability. Organic materials, hydrogenated amorphous silicon (a-Si:H), polysilicon and single-crystal silicon are potential candidates for ultra-thin chips, each with its pros and cons. High mobility transistors are indispensible for video streamings. Threshold instability and self-heating issues demand proper addressing. Different placement schemes of driver chips around TFT matrix and various driving waveforms can be employed to drive heavy loads, especially in case of large-size displays. Technical obstacles must be eliminated in order to realise mass productions of full-flexible display systems.

Mechanical deformation changes the silicon material’s electrical resistivity (Smith, Phys Rev 94(1):42–49, 1954). This is an important property of the material. The effect known as ‘piezoresistive’ has found many applications over time. In micro-electro-mechanical systems (MEMS), for example, it has enabled the integration of pressure sensors with complementary metal-oxide semiconductor (CMOS) circuits that translate the stress into voltage signals. The piezoresistive effect has been also observed and studied in the metal-oxide-silicon field effect transistor (MOSFET), the principal component of a CMOS integrated circuit (IC). In transistors the strain affects the mobility of the carriers and as a result the drain current and the speed of the transistor. Although scaling tends to achieve its limitations, the need to further increase the MOSFET performance by having more power and speed remains. Based on mobility enhancement due to the stress/strain applied to the MOSFET channel, the ‘strained Si’ technique has been chosen as a new degree of freedom to further improve MOSFET performance and to defeat scaling limitations. In this chapter we discuss aspects related to the piezoresistive effect in bulk Si and its modifications in MOSFET Si inversion layer. We analyse the strain effects on Si electronic band structure and its transport properties. Piezoresistive coefficient values from literature for bulk Si and MOSFETs under uniaxial strain are presented and compared.

The paper presents a new solution to achieve rail-to-rail common mode input voltage swing for CMOS operational amplifiers. The common mode input range of a MOS differential stage is limited by the threshold voltage of the input transistors. With a pair of complementary input stages the whole range from GND to VDD can be covered. Their drain currents are summed up but the resulting current as well as the DC voltage of the summing node drastically change when one of the input stages turns off near the power rails. The new method applies a built-in feedback loop with an auxiliary opamp for stabilizing the voltage at the summing node. This way a very stable operating point and ideal CMRR can be assured. With selected transistor aspect ratios nearly constant voltage gain can be achieved for the whole common mode input voltage range.

Apparently anomalous and transient piezoresistive effects are observed from CMOS transistors and diffused resistors fabricated on 20 µm thin, flexible chips for system-in-foil (SiF) applications. We show that this effect results from a transformation of uniaxial to biaxial stress according to the Poisson ratio of the visco-elastic epoxy glue used for chip attachment. This effect is further analyzed through current mirror circuits composed of orthogonally oriented transistors.

Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips in such systems will provide solutions whenever high circuit performance and/or complexity are required.

Analog-to-digital conversion requires input amplitudes in the volts range. On the other hand, optical or magnetic sensors deliver sinusoidal signals in the millivolts range and these signals need to be treated digitally. So, two main units will be needed: (1) a programmable gain amplifier and (2) a digital control circuit to maintain certain voltage at the output of the programmable gain amplifier.

Presented is the design and characteristics of the first CMOS imager chip that has been implanted into a patient's eye with demonstration of partially-restored vision. Also presented and discussed are the design and characteristics of the first miniature APS imager chip based on thin-film-on-CMOS (TFC) photodiode technology targeted at low-cost and disposable diagnostic products. Both sensor designs exploit the high-dynamic range CMOS (HDRC*) pixel circuit providing a continuous lin-to-log transformation of the photo current into a voltage sense signal. This allows for implementing a retinal implant with characteristics similar to that of the human eye and to operate a miniature TFC imager for video inspection under strongly varying light conditions.

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness ⩽20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the builtin devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chipʼs edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.

The last important steps of the tokamak machine assembly are described. A survey of precision and tolerances is given achieved for the vacuum vessel, the toroidal field (TF) magnet and the poloidal field (PF) coils. The first commissioning tests of vacuum vessel, TF magnet and PF coils are described together with certain features of the control and technical supervisory system. Remarks on improvements of the electric power supply system and the fast plasma control system follow. Finally the programme of the next future is briefly outlined.

Beyond optimization of position and shape control, producing high performance plasmas relies on precise and coordinated control of plasma parameters. This requires a universal platform, into which control algorithms can flexibly be integrated to adapt to interesting discharge scenarios. With the multitude of processes expected to be implemented, management of real time processes becomes crucial. In this paper the authors shall demonstrate how this issue is raised by the requirement specification of the controller and how it influences its design, implementation and operation.

Acoustic waves, capable of transmitting through optically opaque objects, have been widely used in biomedical imaging, industrial sensing and particle manipulation. High-fidelity wave front shaping is essential to further improve performance in these applications. An acoustic analog to the successful spatial light modulator (SLM) in optics would be highly desirable. To date there have been no techniques shown that provide effective and dynamic modulation of a sound wave and which also support scale-up to a high number of individually addressable pixels. In the present study, we introduce a dynamic spatial ultrasound modulator (SUM), which dynamically reshapes incident plane waves into complex acoustic images. Its transmission function is set with a digitally generated pattern of microbubbles controlled by a complementary metal–oxide–semiconductor (CMOS) chip, which results in a binary amplitude acoustic hologram. We employ this device to project sequentially changing acoustic images and demonstrate the first dynamic parallel assembly of microparticles using a SUM., Alexander von Humboldt-Stiftung, European Research Council, Projekt DEAL