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As feature resolution and process variations continue to shrink for new nodes of both DUV and EUV lithography, the density and number of devices on advanced semiconductor masks continue to increase rapidly. These advances cause significantly increased pressure on the accuracy and efficiency of OPC and assist feature (AF) optimization methods for each subsequent process technology. To meet manufacturing yield requirements, significant wafer retargeting from the original design target is often performed before OPC to account for both lithographic limitations and etch effects. As retargeting becomes more complex and important, rule-table based approaches become ineffective. Alternatively, modelbased optimization approaches using advanced solvers, e.g., inverse lithography technology (ILT), have demonstrated process window improvement over rule-based approaches. However, model-based target optimization is computationally expensive which typically limits its use to smaller areas like hotspot repairs. In this paper, we present results of a method that uses machine-learning (ML) to predict optimal retargeting for line-space layers. In this method, we run ILT co-optimization of the wafer target and process window to generate the training data used to train a machine learning model to predict the optimum wafer target. We explore methods to avoid ML model overfitting and show the ML infrastructure used to integrate ML solution into a manufacturable OPC flow. Both lithographic quality and runtime performance are evaluated for an ML enabled retargeting flow, an ILT flow and a simple rule table flow at advanced node test cases.

The 5nm and 7nm technology nodes will continue recent scaling trends and will deliver significantly smaller minimum features, standard cell areas and SRAM cell areas vs. the 10nm node. There are tremendous economic pressures to shrink each subsequent technology, though in a cost-effective and performance enhancing manner. IC manufacturers are eagerly awaiting EUV so that they can more aggressively shrink their technology than they could by using complicated MPT. The current 0.33NA EUV tools and processes also have their patterning limitations. EUV scanner lenses, scanner sources, masks and resists are all relatively immature compared to the current lithography manufacturing baseline of 193i. For example, lens aberrations are currently several times larger (as a function of wavelength) in EUV scanners than for 193i scanners. Robustly patterning 16nm L/S fully random logic metal patterns and 40nm pitch random logic rectangular contacts with 0.33NA EUV are tough challenges that will benefit from advanced OPC/RET. For example, if an IC manufacturer can push single exposure device layer resolution 10% tighter using improved ILT to avoid using DPT, there will be a significant cost and process complexity benefit to doing so. ILT is well known to have considerable benefits in finding flexible 193i mask pattern solutions to improve process window, improve 2D CD control, improve resolution in low K1 lithography regime and help to delay the introduction of DPT. However, ILT has not previously been applied to EUV lithography. In this paper, we report on new developments which extend ILT method to EUV lithography and we characterize the benefits seen vs. traditional EUV OPC/RET methods.

EUV lithography is viewed as a highly desirable technology for 5nm and 7nm node patterning cost reduction and process simplicity. However, for the 5nm and 7nm nodes EUV not only needs to function in a low-K1 resolution environment but has several new and complex patterning issues which will need accurate compensation by mask synthesis tools and flows. The main new issues are: long-range flare variation across the chip, feature dependent focus offsets due to high mask topography, asymmetry inducing shadowing effects which vary across the lens slit, significantly higher lens aberrations, illumination source changes (across the lens and with time) and new resist exposure mechanisms. These solutions must be successfully deployed at low K1 values and must be integrated together to create OPC/RET flows which have high resolution, high accuracy, and are fast to deploy. Therefore, the combined requirements of low-K1 resolution, full reticle correction accuracy and process window can be even more challenging than in current optical lithography mask synthesis flows. Advanced computational methods such as ILT and model-based SRAF optimization are well known to have considerable benefits in process window and resolution for low-K1 193 lithography. However, these methods have not been well studied to understand their benefits for lower-K1 EUV lithography where fabs must push EUV resolution, 2D accuracy and process window to their limits. In this paper, we investigate where inverse lithography methods can improve EUV patterning weaknesses vs. traditional OPC/RET. We first show how ILT can be used to guide a better understanding of optimal solutions for EUV mask synthesis. We then provide detailed comparisons of ILT and traditional methods on a wide range of mask synthesis applications.

Background Chronic hepatitis B (CHB) can progress to cirrhosis, hepatocellular carcinoma (HCC) and ultimately liver-related death. Although oral antiviral therapy for patients with CHB reduces the risk of such complications, once cirrhosis is established, the benefits of antiviral therapy are not robustly demonstrated. According to traditional Chinese medicine (TCM), some Chinese herbal medicines promote blood circulation and soften hard masses, and therefore they may block and reverse hepatic fibrosis. The aim of this study is to evaluate the effects of TCM tablets of the compound biejia ruangan (RGT) administered for fibrosis, and entecavir (ETV), on the development of HCC in patients with CHB or hepatitis B virus (HBV)-related compensated cirrhosis. Methods/design This multicenter, centrally randomized, double-blind, placebo-controlled, parallel-group study is planned to complete within 5 years. For the study, 1,000 with CHB or HBV-related compensated cirrhosis are randomly assigned in a 1:1 ratio to a treatment group (0.5 mg ETV once daily; 2 g RGT three times daily) or a control group (0.5 mg ETV once daily; 2 g RGT dummy agent three times daily). The primary end points are the development of HCC and liver-related death. Secondary end points include disease progression and overall survival. Discussion Although antiviral therapy can achieve sustained suppression of HBV replication, thereby preventing cirrhosis, patients with CHB treated with nucleos(t)ide analogs (NUCs) retain a higher risk for HCC compared with patients with inactive disease. Although previous clinical trials with RGT have confirmed the efficacy of blocking and reversing hepatic fibrosis in patients with CHB or compensated cirrhosis, the long-term risk for HCC or disease progression in these patients treated with combination of RGT and NUCs compared with NUCs alone is unclear. Therefore, it is necessary to investigate the effects of the RGT blockade and reversal of hepatic fibrosis on the development of HCC in patients with CHB or HBV-related compensated cirrhosis in large, prospective, multicenter, double-blind, randomized, controlled trials in China. Trial registration ClinicalTrials.gov Identifier: NCT01965418. Date registered: 17 October 2013

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance and need to be enabled for production as one of the leading candidates for low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in production. In a prior publication [1], it has been shown at clip level that the Inverse Synthesizer (IS™) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT n eeds to be studied at full chip level with various aspects including mask data fracturing, MRC co nstraints, writing time, and inspection. The computation of ILT mask usually starts with the calcu lation of an optimized contoured mask then followed by manhattanization step to convert contour into horizontal-ver tical segments. By varying the segmentation length during manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of segmentation length impact on writing time and lithography perfor mance at full-chip is presented. MRC is another important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and inspectability at various selected MRC rules are also presented in the paper. Keywords: Inverse lithography technology (ILT), Sub-resolution assist feature (SRAF), Resolution enhancement technology (RET), Lithography simulation

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

As reticle line widths shrink and RET complexity increases, even a single sub-micron defect can reject a photomask. High-end reticle manufacturers striving for increased yield and reduced cycle times are relying on low incoming rawstock defect levels and handling via SMIF mini environments for critical manufacturing steps. However, even in SMIF compatible reticle fabs, human handling is often required to load or unload a reticle to/from a SMIF environment. In an effort to provide a fully integrated solution to manufacturing 65 nm and below photomasks, Photronics has introduced a blank inspection/management system developed by Hitachi High Technologies and Fortrend Engineering. The clustered system is capable of robotic transfers in conjunction with blank storage, inspection, and material tracking capabilities. It consists of four major systems: a horizontal mask blank transfer system with state-of-the-art blank sorting capability, an integrated Hitachi GM3000 Mask Blank Surface Inspection System, a totally self-contained and sufficient Mask Blank Storage Station, and a material logistic control software system for material management and SPC. The Fortrend Lamina sorting system has a bright light inspection module for gross particle contamination detection, and a robotic transfer module for mask exchanges between SMIF and other shipping/transport boxes employed in the mask manufacturing facilities. The clustered Hitachi inspection system is an integral part of the solution allowing for additional inspections of stored and incoming blanks by optically detecting foreign particles and pinholes. The data is transferred and stored in the Foretrend handling system control module and may be used for rawstock management and screening based on a predefined criteria. The integrated system provides a total solution to mask manufacturing challenges at 65 nm and below.

A robust photomask etching process was studied and developed for 65 nm node photomask production with zero CD process bias. The fabrication process, including pattern generation and transfer do not use data sizing, saving photomask delivery time, improving yield, and reducing fabrication costs. The photomask patterns, without using data sizing cover chrome loads from about 1 percent to 80 percent. For 65 nm critical layer EAPSM, the CD bias of Cr and MoSi etching together is equal to or less than about 20 nm for high and low load photomasks. The etch process and dose adjustment on the 50 keV e-beam writer allow for zero CD process bias, i.e. the data sizing becomes unnecessary in the 65 nm node photomask fabrication. The SMIF pot utilization in both pattern generation and transfer processes significantly improved the defectivity control. Cr and MoSi etch endpoints of 1% load photomasks were clearly detected. Point-to-point CD etch contributions for dark and clear features are 5 nm (3 sigma) or less and final CD value ranges are 8 nm or less. CD etch linearity and other etch properties on SRAF and serif are also discussed. An equation was proposed for calculating phase angle non-uniformity distribution, and phase angle range can be controlled in the range of 1.4±0.3 degree. "Self-mask", i.e. using AR sub-layer as hard mask for beneath chromium sub-layer etch was also discussed.

As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes unpredictable; and, high MEEF imposes much more stringent demands on mask quality. Therefore, in order for any new lithography technology to be adopted into production, mask manufacturability must be studied thoroughly and carefully. In this paper we will present the mask manufacturability study on mask patterns created using Inverse Lithography Technology (ILT). Unlike conventional OPC methodologies, ILT uses a unique outcome-based technology to mathematically determine the mask features that produce the desired on-wafer results. ILT solves the most critical litho challenges of the deep sub-wavelength era. Potential benefits include: higher yield; expanded litho process windows; superb pattern fidelity at 90, 65 & 45-nm nodes; and reduced time-to-silicon - all without changing the existing lithography infrastructure and design-to-silicon flow. In this study a number of cell structures were selected and used as test patterns. "Luminized patterns" were generated for binary mask and attenuated phase-shift mask. Both conventional OPC patterns and "luminized patterns" were put on a test reticle side by side, and they all have a number of variations in term of correction aggressivity level and mask complexity. Mask manufacturability, including data fracturing, writing time, mask inspection, and metrology were studied. The results demonstrate that, by optimizing the inspection recipe, masks created using ILT technology can be made and qualified using current processes with a reasonable turn-around time.

To accelerate the time-to-market of advanced photomasks, Photronics launched its 90nm program in spring 2003. The program included three learning cycles and a technology transfer phase. Both 90nm test masks and product masks from leading integrated device manufacturers (IDMs) and foundries were exercised through the cycles. Stringent success criteria were set based on a survey of leading customers’ requirements and the International Technology Roadmap for Semiconductors (ITRS). Hundreds of binary masks, embedded attenuated phase shift masks (EAPSMs), and alternating aperture phase shift masks (AAPSMs) were produced throughout the program. All targets were exceeded. This paper describes program success criteria, complexity of customer requirements, 90nm test vehicle design, and efforts on improving critical dimension (CD) uniformity and registration. Results in positive and negative chemically amplified resist (CAR) and tunable etching for AAPSM are shown. Details on AAPSM undercut optimization, intensity and CD imbalance are reported.

A comprehensive set of numerical, mask pattern operators is developed and applied for the purpose of understanding photomask fabrication tolerances supporting aggressive, optical lithography resolution enhancement. Using these numerical operators, the content and fidelity of the photomask is systematically degraded and wafer level results predicted using experimentally calibrated simulation. The concept of a mask sensitivity matrix is introduced and used as a bridge to full Monte Carlo analysis of photomask fabrication errors. A statistical approach to analyze mask defect tolerances for resolution enhancement options is presented within the same numerical framework. Such methodical and detailed analysis of mask construction parameters is a vital step toward understanding the complex interaction between mask quality and printed image and hence the delivery of 65 nm node lithography capability.