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This brief presents a low-power, area-efficient three-stage CMOS operational transconductance amplifier (OTA) suitable for very large capacitive loads, ${C} _{L}$ . A single Miller capacitor and an inverting current buffer embedded in the input stage are exploited to implement the frequency compensation network. An additional feed-forward path and a slew rate enhancer are also utilized to improve the large-signal transient response. Detailed small-signal analysis reveals that the proposed OTA does not exhibit an upper limit of drivable ${C} _{L}$ . The OTA is fabricated in a standard 0.35- ${\mu }\text{m}$ technology and occupies 0.0027 mm2 of die area. Under 1.4-V supply and 6.36- ${\mu }\text{A}$ quiescent current consumption, it provides a dc gain greater than 110 dB and is stable for any ${C} _{L}$ larger than 5 nF. Comparison with the state of the art shows remarkable improvement of both small- and large-signal performance.

The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

ASTRI-Horn is a prototypal telescope of an imaging atmospheric Cherenkov telescope developed by the Italian National Institute of Astrophysics (INAF), proposed for the Cherenkov Telescope Array (CTA) Observatory. The CTA Observatory represents the next generation of imaging atmospheric Cherenkov telescopes and will explore the very highenergy domain from a few tens of GeV up to few hundreds of TeV. It will be composed of large-, medium-, and small sized telescopes; ASTRI-Horn is an end-to-end prototype proposed for the Small Sized array. The main scientific instrument of the ASTRI-Horn telescope is an innovative and compact Camera with Silicon- Photomultiplier based detectors and a specifically designed fast read-out electronics based on a custom peak-detector mode. The thermo-mechanical assembly is designed to host both the entire electronics chain, from the sensors to the raw data transmission system and the calibration system, and the complete thermoregulation system. This contribution gives a high level description of the T/M and electrical design of the Cherenkov Camera, it describes the assembling procedure of its different subsystems and their integration into the complete camera system. A discussion about possible design improvements coming from the problems/difficulties encountered during assembly is also presented. Finally, results from engineering tests conducted in-field are also presented.

Within the framework of the Cherenkov Telescope Array (CTA) observatory, the Italian National Institute for Astrophysics (INAF) is leading the “Astrofisica con Specchi a Tecnologia Replicante Italiana” (ASTRI) Project mainly devoted to the definition and development of a set of small-size class telescopes with dual-mirror optical design (SST-2M) for the CTA southern site. The prototype of such telescopes, named ASTRI SST-2M, is installed in Italy at the INAF “M.C. Fracastoro” observing station located in Serra La Nave, Mount Etna, Sicily. In addition to the dual-mirror optical design based on the Schwarzschild-Couder configuration, the ASTRI SST-2M telescope adopts a focal plane camera formed by an array of monolithic silicon photomultiplier sensors coupled with a specifically designed front-end electronics and back-end electronics that represent a further innovative solution for the detection of atmospheric Cherenkov light. The ASTRI SST-2M prototype is currently under completion of the overall commissioning phase: structure, mirrors, camera, control software, data archiving and analysis pipeline. This contribution focuses the attention on the software devoted to the control and monitoring operations of the ASTRI camera. We will provide a brief description of the electronic assemblies and of the software architecture designed, according to software engineering modularization, in terms of functional blocks and how they are deployed in the back-end electronics. Then, we will show how all these functionalities are accessible by the user through the graphical user interface developed and currently used for the engineering tests performed on site.

This paper introduces a new effective single-Miller capacitor compensation topology for three-stage amplifiers with very large capacitive loads, realized through an active-feedback capacitor together with an inner half-feedforward stage. Moreover, an optimized design strategy which profitably exploits the two left half-plane zeros is presented. To improve the amplifier large signal transient response, the topology also includes an external feedforward path, that only marginally affects the frequency compensation, and a novel slew-rate enhancer section. To validate the solutions presented, a three-stage OTA driving a 10-nF load has been designed and implemented in a standard 0.35- $\mu\text{m}$ CMOS technology. The amplifier occupies less than 0.003-mm2 of die area, provides 2.7-MHz gain-bandwidth product and 0.55-V/ $\mu\text{s}$ average slew-rate, while consuming only 25- $\mu\text{A}$ quiescent current.

The design of a power-efficient three-stage CMOS operational amplifier capable of driving extremely high capacitive loads is proposed. The compensation network entails only a single Miller capacitor, thus avoiding the use of additional transistor and current consumption. Theoretical analysis is reported and an implementation in a 0.35-μm technology is presented and simulated. A 1.46-MHz gain-bandwidth product is achieved with a 10-nF load, while consuming only 8.54 μW from 1.4-V supply. As compared to other previously reported solutions, the amplifier shows a remarkable increase in small-signal and large-signal performance.

The Muon Portal is a recently started Project aiming at the construction of a large area tracking detector that exploits the muon tomography technique to inspect the contents of traveling cargo containers. The detection planes will be made of plastic scintillator strips with embedded wavelength-shifting fibres. Special designed silicon photomultipliers will read the scintillation light transported by the fibres along the strips and a dedicated electronics will combine signals from different strips to reduce the overall number of channels, without loss of information. Different silicon photomultiplier prototypes, both with the p-on-n and n-on-p technologies, have been produced by STMicroelectronics during the last years. In this paper we present the main characteristics of the silicon photomultipliers designed for the Muon Portal Project and describe the setup and the procedure implemented for the characterization of these devices, giving some statistical results obtained from the test of a first batch of silicon photomultipliers.

This work addresses a systematic and in-depth electro-optical characterization of the Multi-Pixel Photon Counter (MPPC) sensors constituting the camera detection system at the focal plane of the ASTRI telescope prototype. The paper reports the experimental results of a large set of measurements on the MPPC devices in order to provide a reliable qualification of the detector performance and evaluate its compliance with the telescope focal plane requirements. In particular, breakdown voltage, internal gain, dark count rate, cross-talk and extra-charge probability, and absolute photon detection efficiency measurements are performed on the basic sensor device unit as a function of the detector operating conditions.

In this paper, the traditional equivalent electrical model of silicon photomultipliers (SiPMs) is profitably extended to include the important effects of the read-out electronics on the shape of the output pulse waveforms. An improved analytical expression has been developed, which accurately reproduces the fast detector ignition, the avalanche self-quenching and the slow recharging operations, also taking into account both loading effect and bandwidth limitation of the coupled front-end. By means of the adopted analytical model, the SiPM dynamic response can be accurately mimicked and predicted, and reliable simulations can be also performed. Experimental tests on real detection systems corroborate the SiPM model and analytical results.

The present work introduces an improved SPICE equivalent electrical model of silicon photomultiplier (SiPM) detectors, in order to simulate and predict their transient response to avalanche triggering events. In particular, the developed circuit model provides a careful investigation of the magnitude and timing of the read-out signals and can therefore be exploited to perform reliable circuit-level simulations. The adopted modeling approach is strictly related to the physics of each basic microcell constituting the SiPM device, and allows the avalanche timing as well as the photodiode current and voltage to be accurately simulated. Predictive capabilities of the proposed model are demonstrated by means of experimental measurements on a real SiPM detector. Simulated and measured pulses are found to be in good agreement with the expected results.

This paper presents the latest characterization results of a novel Low Cross-Talk (LCT) large-area (6×6-mm 2 ) Multi-Pixel Photon Counter (MPPC) detector manufactured by Hamamatsu, belonging to the recent LCT5 family and achieving a fill-factor enhancement and cross-talk reduction. In addition, the newly adopted resin coating is demonstrated to yield improved photon detection capabilities in the 290–350 nm spectral range, making the new LCT MPPC particularly suitable for emerging applications like Cherenkov Telescopes. For a 3×3-mm 2 version of the new MPPC under test, a comparative analysis of the large pixel pitch (75-µm) detector versus the smaller pixel pitch (50-µm) detector is also undertaken. Furthermore, measurements of the 6×6-mm 2 MPPC response versus the angle of incidence are provided for the characterized device.

The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is the front-end chip of the camera for the ASTRI SST-2M, one of the prototypes for the small sized telescopes of the Cherenkov Telescope Array, CTA. The telescope, operating in the energy range from a few TeV to beyond 300 TeV, is characterized by innovative technological solutions. The optical system is arranged in a dual-mirror configuration and the focal plane camera consists of a matrix of multi-pixel Silicon Photo-Multipliers. Among others, one of the most important project issue consists in the thermal characterization of the camera that, in the ASTRI SST-2M prototype, is thermo-controlled in a narrow temperature range. A set of at least nine similar telescopes will form the ASTRI mini-array proposed to be installed at the CTA southern site. In the cameras of the ASTRI mini-array telescopes the thermal control could be relaxed with a considerable gain in terms of power consumption, cost and simplicity. So, a study of the temperature dependence of the camera components is needed. The present work addresses this issue showing the results of the measurements carried out on CITIROC as a function of the temperature. We focused our investigation on the pedestal stability, linearity of the charge output signal, preamplifier gain and trigger uniformity in the temperature range 15-30°C. Our results show, for each of the above-mentioned measurable quantities, that temperature dependency is at the level of a few percent.

ASTRI SST-2M is an Imaging Atmospheric Cherenkov Telescope (IACT) developed by the Italian National Institute of Astrophysics, INAF. It is the prototype of the ASTRI telescopes proposed to be installed at the southern site of the Cherenkov Telescope Array, CTA. The optical system of the ASTRI telescopes is based on a dual mirror configuration, an innovative solution for IACTs, and the focal plane of the camera is composed of silicon photo-multipliers (SiPM), a recently developed technology for light detection, that exhibit very fast response and an excellent single photoelectron resolution. The ASTRI camera electronics is specifically designed to directly interface the SiPM sensors, detecting the fast pulses produced by the Cherenkov flashes, managing the trigger generation, the digital conversion of the signals and the transmission of the data to an external camera server connected through a LAN. In this contribution we present the general architecture of the camera electronics developed for the ASTRI SST-2M prototype, with special emphasis to some innovative solutions.

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances

The present work proposes an improved PSPICE implementation of the equivalent electrical model of silicon photomultipliers (SiPMs) to simulate and predict their transient re-sponse to avalanche trigger events. In particular, the developed model provides a detailed investigation of magnitude and timing of the read-out signals and can therefore be exploited to perform reliable circuit-level simulations. The modeling approach used is strictly related to the physics of each basic microcell constituting the SiPM device, and allows the avalanche timing as well as the photodiode current and voltage to be accurately simulated. Predictive capabilities of the proposed model are demonstrated by means of experimental measurements on a real detector. Versatility of the proposed model is also confirmed.

The Muon Portal Project [1] is a joint initiative between research and industrial partners, aimed at the construction of a real size detector protoype (6×3×7 m3) for the inspection of containers by the muon scattering technique, devised to search for hidden high-Z fissile materials and provide a full 3D tomography of the interior of the container in a scanning time of the order of minutes. The muon tracking detector is based on a set of 48 detection modules (size 1 m × 3 m), each built with 100 extruded scintillator strips, so as to provide four X-Y detection planes, two placed above and two below the container to be inspected. Two wavelength shifting (WLS) fibres embedded in each strip convey the emitted photons to Silicon Photomultipliers (SiPM) which act as photosensors. After a research and development phase, which led to the choice and test of the individual components, the construction of the full size detector has already started. The paper describes the results of the mass characterization of the photosensors and the construction and test measurements of the first detection modules of the Project.

The Muon Portal Project has as its goal the design and construction of a real-size working detector prototype in scale 1:1, to inspect the content of travelling containers by means of the secondary cosmic-ray muon radiation and to recognize high-Z hidden materials (i.e. U, Pu). The tomographic image is obtained by reconstructing the input and output trajectories of each muon when it crosses the container and, consequently, the scattering angle, making use of two trackers placed above and below the container. The scan is performed without adding any external radiation, in a reasonable time (few minutes) and with a good spatial and angular resolution. The detector consists of 8 planes each segmented in 6 identical modules. Each module is made of scintillating strips with two WaveLength Shifting fibers (WLS) inside, coupled to Silicon photomultipliers. The customized read-out electronics employs programmable boards. Thanks to a smart read-out system, the number of output channels is reduced by a factor 10. The signals from the front-end modules are sent to the read-out boards, in order to convert analog signals to digital ones, by comparison with a threshold. The data are pre-analyzed and stored into a data acquisition PC. After an intense measurement and simulation campaign to carefully characterize the detector components, the first detection modules ( $1 \times 3 ~\hbox{m}^{2}$ ) have been already built. In this paper the detector architecture, particularly focusing on the used electronics and the main preliminary results will be presented.

A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented. The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed a CMOS OTA in a 0.35- $\mu{\rm m}$ technology that occupies only $4.4\cdot 10^{-3}\ {\rm mm}^{2}$ , is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 ${\rm mV}/\mu{\rm s}$ with the 200 pF load. Comparison with prior art shows an improvement factor in the figures of merit higher than 5.

The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera., 25 pages, 16 figures, 1 table

In this paper a comprehensive analytical analysis is performed based on a new accurate electrical model of silicon photomultiplier (SiPM) detectors. The proposed circuit model allows to accurately reproduce the SiPM output time response regardless of the particular technology adopted for the fabrication process, and can also be profitably exploited to perform reliable circuit-level simulations. A novel expression of the detector photoelectron response due to a single photon absorption is systematically developed. The obtained waveform accurately reproduces the fast detector ignition, the ensuing avalanche self-quenching and the final slow recharging operation. Predictive capabilities of the adopted analytical model are demonstrated by means of experimental measurements on a real SiPM device.

In the context of the Cherenkov Telescope Array observatory project, the ASTRI SST-2M end-to-end prototype telescope, entirely supported by the Italian National Institute of Astrophysics, is designed to detect cosmic primary gamma ray energies from few TeV up to hundreds of TeV. The ASTRI SST-2M prototype camera is part of the challenging synergy of novel optical design, camera sensors, front-end electronics and telescope structure design. The camera is devoted to imaging and recording the Cherenkov images of air showers induced by primary particles into the Earth’s atmosphere. In order to match the energy range mentioned above, the camera must be able to trigger events within a few tens of nanoseconds with high detection efficiency. This is obtained by combining silicon photo-multiplier sensors and suitable front-end electronics. Due to the characteristic imprint of the Cherenkov image that is a function of the shower core distance, the signal dynamic range of the pixels and consequently of the front-end electronics must span three orders of magnitude (1:1000 photo-electrons). These and many other features of the ASTRI SST-2M prototype camera will be reported in this contribution together with a complete overview of the mechanical and thermodynamic camera system.

This paper addresses a comprehensive analytical analysis of a new accurate electrical model of silicon photomultiplier (SiPM) detectors. The adopted circuit model allows to truly reproduce the SiPM output signal waveform apart from the specific technology employed for the fabrication process, and can also be profitably exploited to perform reliable circuit-level simulations. A novel analytical expression of the transient single-photoelectron response due to photon absorption is systematically developed. The attained function accurately reproduces the fast detector ignition, ensuing avalanche self-quenching, and final slow recharging operation. Predictive capabilities of the adopted analytical model are demonstrated by means of experimental measurements on a real detector.

The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of the measurements performed to characterize EASIROC in order to evaluate its compliance with the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger time walk and the jitter effects as a function of the pulse amplitude. The EASIROC output signal is found to vary linearly as a function of the input pulse amplitude with very low level of electronic noise and cross-talk (, 21 pages, 14 figures

UVSiPM is a light detector designed to measure the intensity of electromagnetic radiation in the 320-900 nm wavelength range. It has been developed in the framework of the ASTRI project whose main goal is the design and construction of an end-to-end Small Size class Telescope prototype for the Cherenkov Telescope Array. The UVSiPM instrument is composed by a multipixel Silicon Photo-Multiplier detector unit coupled to an electronic chain working in single photon counting mode with 10 nanosecond double pulse resolution, and by a disk emulator interface card for computer connection. The detector unit of UVSiPM is of the same kind as the ones forming the camera at the focal plane of the ASTRI prototype. Eventually, the UVSiPM instrument can be equipped with a collimator to regulate its angular aperture. UVSiPM, with its peculiar characteristics, will permit to perform several measurements both in lab and on field, allowing the absolute calibration of the ASTRI prototype., Comment: Accepted for publication in Nuclear Physics B (Proceedings Supplements)

The present paper addresses an improved and compact low-power high-speed buffer amplifier topology for large-size liquid crystal display drivers. The proposed buffer achieves fast driving performance, draws a low quiescent current and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing and settling capabilities by realizing a dual-path push-pull operation of the output stage. No additional bias network is required to fix the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself without auxiliary power dissipation. Simulation results demonstrate that the suggested buffer can drive a 1000-pF column line capacitive load with a 5.8-V/µs slew-rate and a 0.75-µs settling time, while drawing only 3-µA quiescent current from a 3-V power supply.

This work addresses a new compact low-power highspeed output buffer amplifier topology for large-size LCD applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities by exploiting the push-pull output sections of two basic complementary-type input amplifiers to realize a dual-path push-pull operation of the output stage. An auxiliary bias network integrated in the input differential stage allows the quiescent conditions of the class-AB output stage to be inherently controlled without additional power dissipation. Post-layout results confirm that the proposed amplifier can drive a 1-nF capacitive load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current.

In this paper the reversed nested Miller compensation (RNMC) approach is reviewed and its design equations are presented. After introducing two new compensation techniques, a coherent and comprehensive comparison of the available solutions is performed by means of a figure of merit expressing the trade-off among gain-bandwidth product, load capacitance and total transconductance, for equal values of phase margin. The proposed comparison outlines useful design guidelines for the optimization of the overall amplifier performance. Simulations proving the effectiveness of the suggested design methodology and analytical comparison are included, showing the substantial advantage of one of the proposed solutions.

The present paper addresses a new compact low-power high-speed output buffer amplifier topology for large-size liquid crystal display applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by simultaneously exploiting the push---pull output sections of two basic complementary-type input amplifiers to realize a dual-path push---pull operation of the output stage. An auxiliary biasing network integrated in the input differential stage allows the quiescent bias conditions of the class-AB output stage to be inherently controlled without additional current dissipation. Post-layout simulation results confirm that the proposed amplifier can drive a 1-nF column line load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current. Monte Carlo simulations are finally carried out, showing a good degree of robustness of the proposed output buffer against process and mismatch variations.

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1-nF column line load with 8.5-V/µs slew-rate and 0.8-µs settling time, while drawing only 8-µA static current from a 3-V power supply.

This paper proposes and develops two simple efficient techniques for optimizing the closed-loop transient response of three-stage amplifiers for large capacitive load applications. The proposed approaches exploit a current comparator in the inner amplifier nodes to sense the input voltage transients and switch on an auxiliary driving device providing slew-rate enhancement and settling time improvement without extra static power dissipation. SPECTRE simulations are carried out on a three-stage amplifier adopting a recently proposed RNMC strategy with a voltage follower and two resistors. Simulation results confirm the effectiveness of both proposed techniques, showing a symmetrical step-response with a significant improvement in large-signal speed performance. Both discussed solutions are suitable for any particular three-stage amplifier topology and are also independent of the adopted compensation network.

This paper proposes and develops an original power-efficient reversed nested Miller compensation technique for low-power three-stage amplifiers driving large capacitive loads. The proposed approach exploits dual-active buffers in the compensation network, along with a feedforward gain stage providing enhanced speed performance. A well-defined design procedure for the compensation elements is also developed using the loop-gain phase margin as the main design parameter. To confirm the effectiveness of the proposed technique, SPECTRE simulations on a three-stage amplifier driving a 1-nF capacitive load are carried out adopting the model parameters of a standard 0.35µm CMOS technology. Simulation results are finally found to be in excellent agreement with the theoretical analysis, showing a considerable improvement of the proposed strategy over other traditional solutions in terms of small-signal and large-signal performance.

This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. Simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance.

This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. SPECTRE simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance. Monte Carlo simulation results finally prove the proposed technique to be well-guarded against process parameter variations.

A novel frequency compensation technique for three-stage amplifiers is introduced. The proposed solution exploits two Miller capacitors, two resistors and an additional feedforward stage which can be implemented without entailing extra transistors. Design equations using the phase margin as design parameter are carried out. The technique is used to design, with a standard CMOS 0.35-mum process, a 2-V three-stage amplifier driving a 500-pF load capacitor. The amplifier dissipates only 70muA at DC and achieves a 1.2-MHz gain-bandwidth product, showing a significant improvement in (MHz-pF)/mA performance

Two simple efficient techniques to optimise the closed-loop transient response of three-stage amplifiers for large capacitive load applications are proposed and developed. The proposed approaches exploit a current comparator in the inner amplifier nodes to sense the input voltage transients and to switch on an auxiliary driving device providing slew-rate enhancement and settling time improvement without extra static power dissipation. SPECTRE simulations are carried out on a three-stage amplifier adopting a recently proposed reversed-nested Miller compensation strategy with a voltage follower and two nulling resistors, for which a novel design methodology is provided as well. Simulation results confirm the effectiveness of the two proposed techniques, showing a symmetrical step response with a significant improvement in large-signal speed performance. Both proposed solutions are suitable for any particular three-stage amplifier topology and are also independent of the adopted compensation network.