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We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m matching, $A_{v0}=62dB$ gain (L=200nm), $f_{T}=126GHz$ cut-off frequency and $f_{MAX}=182GHz$ maximum operating frequency (L=35nm). Junction Less transistor performances even exceed those of inversion-mode ones in terms of back-bias capability, low-frequency noise, hotcarrier degradation and fMAX. This is explained by junction less physics: channel length modulation, bulk conduction and high channel-depth sensitivity to back bias.

In this paper, we experimentally demonstrate, for the first time, gate-all-around (GAA) nanosheet transistors with a record number of stacked channels. Seven levels stacked nanosheet (NS) GAA transistors fabricated using a replacement metal gate process, inner spacer and self-aligned contacts show an excellent gate controllability with extremely high current drivability $(3\mathrm{mA}/\mu \mathrm{m}\ \mathrm{at}\ \mathrm{V}_{\mathrm{DD}}=1\mathrm{V})$ and a 3 x improvement in drain current over usual 2 levels stacked- NS GAA transistors.

Context. Within the framework of the second-generation instrumentation of the Very Large Telescope Interferometer of the European Southern Observatory we have developed the four-telescope beam combiner in integrated optics. Aims. We optimized the performance of such beam combiners, for the first time in the near-infrared K band, for the GRAVITY instrument dedicated to the study of the close environment of the galactic centre black hole by precision narrow-angle astrometry and interferometric imaging. Methods. We optimized the design of the integrated optics chip and the manufacturing technology as well, to fulfil the very demanding throughput specification. We also designed an integrated optics assembly able to operate at 200 K in the GRAVITY cryostat to reduce thermal emission. Results. We manufactured about 50 beam combiners by silica-on-silicon etching technology. We glued the best combiners to single-mode fluoride fibre arrays that inject the VLTI light into the integrated optics beam combiners. The final integrated optics assemblies have been fully characterized in the laboratory and through on-site calibrations: their global throughput over the K band is higher than 55% and the instrumental contrast reaches more than 95% in polarized light, which is well within the GRAVITY specifications. Conclusions. While integrated optics technology is known to be mature enough to provide efficient and reliable beam combiners for astronomical interferometry in the H band, we managed to successfully extend it to the longest wavelengths of the K band and to manufacture the most complex integrated optics beam combiner in this specific spectral band.

International audience; This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.

Best paper award; session 9: Novel Materials and Technologies; International audience; Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

International audience; We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.

A three dimensional 300mm wafer scale nano imprinting lithography was developed. Two process flows were investigated to manufacture sub 100nm resolution multilevel silicon stamps. Using 193nm optical lithography and dry etching processes in a standard Integrated Circuit pilot line, we succeeded in manufacturing 5 levels stamps. Depending of the pattern designs and number of required levels onto the stamp, we proposed manufacturing process rules. We also demonstrated that sub 20nm overlay accuracy over 300mm wafer was achievable between each level patterned into the stamp. These 3D stamps were then printed over 300mm wafer coated with 200nm thick thermoplastic resist layer. We demonstrated that large surface 3D printing with sub 100nm resolution was achievable with an equivalent patterning throughput of 4cm^2/s. Both the use of silicon hard and polymer soft 3D stamps were investigated to underline the impact of the stamp's mechanical stiffness onto the residual layer thickness distribution over large surfaces.

Due to the unavoidable short channel effects associated with planar bulk silicon MOSFET scaling, FinFET and FDSOI have become the most used solutions for the latest generations of CMOS. Gate control over the channel is excellent and performances are enhanced due to the increased effective width in the case of FinFET [1], and due to the forward body biasing solution in the case of FDSOI. However, after several generations of industrially produced FinFET and FDSOI, one crucial question will arise: how far can those technologies be scaled down? Currently, nanowire (NW) transistors have been proven to be excellent candidates for advanced technology nodes. Specifically, electrostatic control is improved over FinFET for better performance and energy savings. Over the last ten years, many developments on nanowire fabrication and nanowire FETs have been proposed [2] [3] [4] [5]. Today, stacking several nanowires at such scale paves the way for a significant increase in the effective width and current density along with substantial savings in device footprint. Stacked nanowires can be implemented with different geometries such as circular or square cross-sections. However, we recently confirmed [5] among other studies [6] that thin and wide devices, also labelled as nanosheets, provide the best performances with respect to the FinFET technology. A further attractive aspect for the use of nanowires in transistors, is that it may be possible to keep some of the flexibility from the planar technologies. In contrast, FinFET technology imposes a discrete partitioning of the active area. In order to increase the output current of a given FinFET based gate, it may be necessary to add another fin to increase the footprint by one fin pitch. Using nanosheets transistors, channel width can be tuned to obtain the required amount of current with limited impact on footprint as discussed in [7]. Stacked nanowire technology is also appealing as one possible solution due to the fact that their integration can be derived from FinFET. Several groups are currently working on their integration trying to minimize the variations from FinFET Gate-Last process [8]. Two options were identified and labelled as NW first and NW last referring to the fabrication of the NW stack. In the former, several successive epitaxies are performed and patterned to form the active zone as a vertical fin, after which silicon or silicon germanium needs to be removed in order to leave suspended silicon or silicon germanium channels. In the NW last integration, selective removal of silicon germanium happens in between the spacers after the removal of the sacrificial gate. In this case, an etch stop layer must be created to prevent the final gate penetrating under the spacers. This etch stop layer must also be low K in order to recreate the missing spacer material in between the NWs. Due to this requirement, an alternative integration has also been investigated. In the NW first option the selective removal of silicon germanium is done before the first spacer patterning and deposition. This method is also coupled with the use of a hydrogen silsesquioxane (HSQ) resist. This flowable oxide can be exposed through the silicon nanowires and the remaining material left after developing can be used as a sacrificial gate during the gate last process. The spacer deposited afterward is able to wrap around the NWs and the oxide temporary gate. As a consequence, this method provides self-aligned gate and spacer. In recent years, we have also come to focus on carrier transport in NW devices. We have produced several NW-FETs in trigate and Ω-gate shapes on SOI in which we measured electron and hole mobility. Face related transport was observed and improved by using proper strain engineering. Strained SOI and silicon germanium raised source and drain were found to have a significant impact on mobility [4]. Currently, this work is also being integrated in order to boost the performances of our stacked NW-FETs. In this paper we propose a review of the NW architecture and of different integration concepts. Several key points for the performance optimization will be pointed out. [1] Natarajan, S. et al. IEDM, 2014 [2] Ernst, T. et al. IEDM 2006 [3] Coquand, R. et al. VLSI 2013 [4] Barraud, S. et al. VLSI 2013 [5] Gaben, L. et al. SSDM 2015. [6] Kim, Seong-Dong et al. S3S 2015 [7] Lacord, J. et al. SSDM 2012. [8] Lauer, I. et al. VLSI 2015

An original technique is used to induce a compressive strain in the channel of Fully Depleted (FD)SOI MOSFETs thanks to an Embedded Buried Nitride stressor. Strain measurements are performed by Grazing Incidence X-ray Diffraction (GIXRD) and compared to mechanical simulations. Both results are in agreement and prove that the strain level can achieve -0.6 percent (-780 MPa) in the channel of a transistor, depending on the active region geometry and the nitride properties (intrinsic strain and thickness). This technique is thus very promising in order to boost pMOSFETs on thin films.

In this paper we report on advances in DUV dry photolithography both for etching and implantation of silicon photonic devices. We explain why silicon patterning is a critical building block in silicon photonics and what are the challenges related to that process. Furthermore, it also occurs that some silicon photonic devices need implantation lithographic conditions which are also specific to the technology. For that purpose, we developed a dedicated DUV 193nm implantation lithography to address that need.

Ω-gate nanowires (NW) P-FETs on compressively-strained-SiGe-on-insulator (cSGOI) substrate obtained by the Ge enrichment technique are presented. Effectiveness of cSGOI channel is demonstrated for ultra-scaled P-FET NW (L G =15nm and W NW =25nm) with an outstanding I ON current (I ON =860µA/µm at I OFF =140nA/µm) and a good electrostatics immunity (DIBL=110mV/V). For the first time, Si 0.8 Ge 0.2 -channel transistors highlight a mobility improvement for narrow NWs down to short gate length compared to Si one (92% for L G =30nm). The hole mobility improvement provided by the strong uniaxial compressive strain coming from cSiGe and cCESL leads to an ION current improvement of 95% at L G =15nm.

For 11nm and below, several alternatives are still potential candidates to meet the patterning requirements. Spacer patterning, Mask Less Lithography (i.e. Electron beam lithography) and Direct Self Assembly are alternatives under development at CEA-LETI. We have demonstrated the integration of these alternative techniques in front end of line and back end of line levels. Common challenges such as minimum achievable CD, CD control through the integration steps, mask budget and LWR were compared for these techniques.

Thanks to a well-controlled CMOS FDSOI technology we have recently been able to demonstrate breakthroughs in the combined use of field effect and Coulomb blockade phenomena. On one hand, we have demonstrated room temperaturehybrid circuits based on single electron transistors and MOSFETs. On the other hand, we have shown the practical performance of electron pumps designed with a single silicided Coulomb island and MOSFETs as tunable barriers for metrologic applications.

In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.

Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

In this paper we show that on scaling nanowire width from 20 nm down to sub-7 nm regime, together with achieving excellent short channel effect control (DIBL = 12 mV/V for LG = 20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing ID–VG of a FET to oscillating ID–VG of a Single Electron Transistor. This transition in transport mechanism is brought about by process induced channel potential variability. It poses a challenge to further scaling of nanowire MOSFETs. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at VD = ±0.9 V) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of Beyond Moore devices.

We report an experimental study of the carrier transport in [1 1 0]-oriented long channel tri-gate (TG) and omega-gate (ΩG) silicon nanowire (SiNW) transistors cross-section down to 11 nm × 10 nm. Electron and hole mobilities have been measured down to 20 K to evaluate the contribution from the dominant scattering mechanisms. We have studied and discussed the influence of channel shape, channel width and strain effect on carrier mobility. In particular, we have shown that the transport properties are mainly driven by the relative contribution of the different inversion surfaces, without noticeable differences between TG and ΩGNWs. We have also demonstrated the effectiveness of an additional uniaxial tensile strain in NMOS NWs down to 10 nm width.

The operation of hybrid circuits consisting of a single hole transistor coupled to a metal oxide semiconductor field effect transistor (MOSFET) is demonstrated at 350 K. The devices are designed at ultimate scaling with complementary metal oxide semiconductor technology on 300 mm diameter silicon on insulator wafers using deep ultra-violet lithography. Coulomb blockade oscillations up to 350 K are measured from silicon nanowire transistors with 20 nm Ω-gate length and diameter under 5 nm. These oscillations are exploited to produce inverter/amplifier, literal gate, negative differential resistance and memory loop circuits for multivalued (MV) logic and MV memory applications, via hybridization with MOSFET in SETMOS configuration. The fabrication and the operation of these SHT-MOSFET hybrid circuits at high temperature should spur single charge transistor integration into circuits for innovative applications in nanoelectronics.

For the first time we evidence the transition from a MOSFET operation to Single Electron Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper we show that on scaling nanowire width from 20 nm down to 5 nm regime, together with achieving excellent short channel effect control (DIBL=12 mV/V for L G =20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing to periodically peaked I D -V G 's. This transition is brought about by process induced channel potential variability (due to disorder) in nanowires and poses a challenge to further scaling. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at V D =±0.9 V!) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of beyond Moore devices.

A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with respect to SOI NW). This improvement is maintained even by using H 2 annealing used for Ω-Gate. On short gate length, a strain-induced I on gain as high as 40% at L G =45nm is achieved for multiple-NWs active pattern.

We present the integration scheme we have optimized to fabricate very short gate length MOSFETs with 2D and 3D arrays of silicon nanowires (NW) and higk-k/metal gate stacks. Aggressively scaled NWs with sub-5nm diameters are obtained. In particular, we report a 3D matrices technology with up to 13 levels of stacked single-crystal Si nanowires that can be most interesting for memory applications. In addition, we present a careful study of the electrical properties of such devices. Our electrical measurements reveal that the NWs' size, shape and surface treatment have a significant influence on transport properties. We identify peculiar transport and interface properties and we show that surface effects are significant for diameters equal or lower than 20nm. The use of nanowires (whatever the process) in standard sub-11nm CMOS nodes circuits will depend mainly on lithography progress in the coming years, but also on contact and metal interconnects. Ultra dense 3D arrays of Si nano-wires can however be fabricated in R&D facilities for high current, ultra-dense transistors or capacitors, sensors and NAND flash memories purposes. They are also useful for mobility and gate dielectric/nanowire interface characterization.

We report for the first time the fabrication and the electrical operation of a Ge and Si based CMOS planar scheme with GeOI pFETs and SOI nFETs, taking advantage of the best mobility configuration for holes (Ge) and electrons (Si). The hybrid Ge/Si wafers have been obtained by the local Ge enrichment technique on SOI wafers. A sub 600 C CMOS transistor process featuring High-K/Metal Gate and silico-germanidation was used to obtain functional high mobility CMOS transistors (down to L = 160 nm). Excellent low-field mobility values for electrons in Si nFETs and holes in Ge pFETs were achieved (275 and 142 cm 2 /V/s resp.).

We report a patterning strategy for building the first monoelectronic device complementary metal oxide semiconductor (CMOS)-compatible platform, including a single-electron transistor (SET) and multiple coupled quantum dots. Aggressive hybrid lithography (e-beam and deep UV are combined) and plasma etching are used to form adapted silicon active areas and gates, with a minimum size of 14 nm and a pitch of 80 nm after etching. These aggressive dimensions enable the study of double dots, a key structure for the more complex quantum circuits emerging now.

We demonstrate that the integration of in-situ doped Si Source and Drain (S/D) in three-dimensional Multi-Channel Field-Effect Transistors (MCFETs) leads to improved electrical performances. The combination of in-situ doped Selective Epitaxial Growth (SEG) and ion implantation indeed enables to drastically reduce the S/D resistance (down to 72 Ω.µm for nFET and 227 Ω.µm for pFET). Ion implantation induces a small mobility degradation, which becomes negligible in short gate length (L G ) MCFETs. Gate width down-scaling otherwise needed to suppress the overall mobility degradation with L G and obtain the best electrical properties.

Although single dopant signatures have been observed at low temperature [1–2], the impact on transistor performance of a single dopant atom at room temperature is not yet well understood. Here, for the first time, we provide an in-depth understanding of single dopant influence on NMOSFETs characteristics by linking low and room temperature transport. We demonstrate that, for gate length of 30 nm and below (channel length down to 10 nm), the presence of a single dopant dramatically alters the subthreshold behaviour when the dopant is located in the middle of the channel. Moving the dopants away from the channel leads to enhanced variability above the threshold voltage V t .

For the first time, interface properties between high-k and Si or SiGe nanowires (NWs) have been experimentally investigated by adapting charge pumping technique and low-frequency noise measurement. It is found that the interface state density (D it ) of circular Si NWs is ∼3 times higher than that of rectangular ones with a deleterious impact on the low field mobility. The oxide trap density in SiGe NWs is otherwise ∼3.5 times higher than that of Si NWs which limits the mobility enhancement for this material.

We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22nm nodes. We demonstrate pFET devices with promising electrical behavior (ION=790µA/µm; I OFF =60nA/µm @ V DS =-1.2V; L g =30nm), suitable for high performance applications. Excellent SCE control is also reported down to 30nm (DIBL=50mV/V), through the use of Double Gate transistors.

Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF ( 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.

For the first time, ultra low IOFF (16.5 pA/mum) and high IONN,P (2.27 mA/mum and 1.32 mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on SOI with a metal/high-K gate stack. This leads to the best ION/IOFF ratios ever reported: 1.4 times 108 (0.8 times 108) for 50 nm n- (p-) MCFETs. We show, based on specifically developed integration process, characterization methods and analytical modeling, how those performances are obtained thanks to specific 3D MCFET features, in particular, transport properties, saturation regime and electrostatic behavior.

Three level stacked Si nanowires transistors with HfO 2 /TiN/poly-Si gate all around stacks (transistors called hereafter 3NWG) were processed, thanks to a self-aligned process. A current gain of 4.3 for NMOS and 4.7 for PMOS compared to planar SOI was demonstrated for V D = 1.2 V and V G − V T = 0.8 V, thanks to a 3D integration scheme (stacked and aligned nanowires). Those 3NWG devices revealed a current gain of 4.9 for NMOS and 4.2 for PMOS for V D = 50 mV when getting rid of the access resistance impact. Thanks to capacitance measurements, we found an expected inversion charge gain per plan-view surface of 6.4, highlighting the potentiality of the 3NWG device. The split-CV technique was used to extract electron and hole effective mobilities. The transport in 3NWG (on etched surfaces) was compared to the one in planar SOI devices.

Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed

For the first time, TiN metal gate and high K gate dielectric (HfO/sub 2/) have been successfully integrated on non planar /spl Omega/FETs transistors, with gate lengths down to 10nm. NMOS transistors exhibit an excellent I/sub ON//I/sub OFF/ ratio of 5.10/sup 5/, the best value ever reported for a 10nm non planar device. The use of HfO/sub 2/ reduces the gate leakage current by several orders of magnitude, for EOT of 1.92nm. Very low off-currents are measured with high on-currents, demonstrating the interest of such devices for low power applications.

In this paper, the first SON (Silicon On Nothing) devices with metal gate are presented. Extremely thin fully depleted Si-films are recognized to be integrable with single-metal gate (mid-gap) due to their intrinsically low threshold voltage. In this work we present mid-gap CoSi/sub 2/ metal gate by total gate silicidation on SON transistors with Si-conduction channel thickness down to 5 nm. Due to its architecture and to the continuity between SD areas and the bulk, SON transistors allow deep silicidation processing down to the gate oxide, meaning that no more polysilicon is left. SON PMOS devices were performed with 55 nm CoSi/sub 2/ gate length with 5 nm of Si-channel thickness, and show excellent performances (350 /spl mu/A//spl mu/m I/sub on/ with only 0.1 nA I/sub off/ at -1.4 V with T/sub ox/=20 /spl Aring/). The polydepletion is of course suppressed and the gate resistance (

In this paper, the first 80 nm SON MOSFETs are presented, demonstrating the electrical viability of the SON architecture. The transistors have a 20 nm thick Si-film channel, isolated from the bulk by a 20 nm dielectric layer. The electrical results show significant improvement (/spl sim/30%) compared with bulk reference devices. In particular, drive current and transconductance are improved due to the better effective field-inversion charge compromise, and SCE due to the thinness of the junctions and of the channel. These electrical results are then used to calibrate the ISE simulator and to make predictions on SON performances with more aggressive gate length and Tox. These predictions show the potential of the SON architecture for future CMOS generations.

We evidence a unique feature of junctionless Fully-Depleted Silicon-On-Insulator (JL FDSOI) transistors: the presence of both bulk and accumulation conduction renders standard VT-variability studies incomplete. For JL transistors, we rather propose an original analysis of the (local and global) variability in all-operation-regimes, from subthreshold to accumulation. We evidence that the current variability around VT is highly sensitive to back-bias VB and film thickness $(\mathrm{t}_{\mathrm{si}})$ uniformity. We demonstrate experimentally for the first time up to 70% lower drain current (ID) local variability for Junctionless Accumulation Mode (JAM) vs. inversion mode (IM) at 1V gate voltage (V G), $\mathrm{L}=18$ nm gate length and $\mathrm{W}=20\mathrm{nm}$ width. This is attributed to the impurity screening, lowering the impact of Random Dopant Fluctuations variability.