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Advances over the last decades in electronic design automation (EDA) for the design of digital integrated circuits (ICs), have led to the development of a robust set of tools and methodologies that automate almost all low-level phases of the digital design workflow. In contrast, analog IC design remains a mostly handmade, time-consuming and knowledge-intensive process. The amount of design iterations can be heavily cut down by the use of realistic value tables through the $g_{m}/I_{D}$ design technique; however, the process still remains time-consuming and error-prone, with an end result of limited applicability beyond the scope of the initial specifications. The slice-based design methodology, first introduced in this paper, is a new approach to analog IC design, suitable for implementation in EDA tools, that aims to reduce the amount of time and expertise required from the user. This methodology, inspired by the $g_{m}/I_{D}$ design technique, is based on the use of pre-designed circuit cells, which can be connected in parallel to scale important performance metrics. Although not limited to any particular fabrication process, the present paper explores the application of the proposed design methodology to CMOS technologies, and in the context of a particular target application: low-noise charge-sensitive amplifiers (CSA) used for instrumentation in particle physics experiments. The methodology was successfully applied and validated through the design, fabrication and testing of a CSA with configurable noise performance.

Continuous monitoring of ventilatory parameters such as tidal volume (TV) and minute ventilation (MV) has shown to be effective in the prevention of respiratory compromise events in hospitalized patients. However, the non-invasive estimation of respiratory volume in non-intubated patients remains an outstanding challenge. In this work, we present a novel approach to respiratory volume monitoring (RVM) that continuously predicts TV and MV in normal subjects. Respiratory flow in 19 volunteers under spontaneous breathing was recorded using respiratory inductance plethysmography and a temperature-based wearable sensor. Temperature signals were processed to identify features such as temperature amplitude and mean value, among others. The feature datasets were then used to train and validate three machine-learning (ML) algorithms for the prediction of respiratory volume based on temperature-related features. A model based on Random-Forest regression resulted in the lowest root mean-square error and was subsequently chosen to predict ventilatory parameters on subject test data not used in the construction of the model. Our predictions achieve a bias (mean error) in TV and MV of 16.04 mL and 0.19 L/min, respectively, which compare well with performance metrics reported in commercially-available RVM systems based on electrical impedance. Our results show that the combination of novel respiratory temperature sensors and machine-learning algorithms can deliver accurate and continuous estimates of TV and MV in healthy subjects.

Ferroelectric (FE) materials are being studied for a variety of applications in memory, logic, and neuromorphic computing, for which predictive models of FE polarization are essential. In this paper, we present a Monte Carlo simulation framework capable of predicting the dynamic, history-dependent response of an FE under arbitrary input waveforms. The simulation is developed by generalizing the physics-based nucleation-limited switching model for polarization reversal in a polycrystalline FE. Measured polarization reversal data from fabricated FE Hf0.5Zr0.5O2 capacitors are used to extract the statistical distribution of FE grains. After parameter extraction, the model is able to predict the dynamics of the FE capacitor without further calibration. Finally, the model is applied to characterize the dynamic response of FE–dielectric bilayer structures and quantify the reduction in memory window due to device variability.

Deeper understanding of memristive behavior is the only safe way towards maximum exploitation of the favorable properties and the analog nature of this new device technology in innovative applications. This can be achieved through experimental hands-on experience with real devices. However, lab experiments with memristors are a challenging step, especially for the uninitiated. In this direction, this paper presents some important considerations to carry out reliable measurements using an experimental setup composed of off-the-shelf components and an affordable data acquisition system. We specifically show how a transimpedance amplifier can be used to protect the memristor from damage via current compliance limiting, and allow full control over the voltage drop on its terminals. Using the proposed setup, a set of key experiments were carried out on commercial memristors from Knowm Inc., revealing fundamental dependencies of memristor state-tuning properties on the characteristics of the applied pulses and the initial conditions of the devices.

Ferroelectric Zr-doped HfO2 (HZO) is a promising candidate for steep slope transistors and memory technology. For these applications, it is essential to understand and optimize the switching dynamics of the ferroelectric film. In this letter, we characterize the polarization reversal of an 8 nm-thick HZO film deposited by the atomic layer deposition with voltage pulses varying in amplitude (0.8–2 V) and duration (200 ns–7.6 ms). We show that the measurements are well described by a nucleation limited switching model, which enables extraction of the minimum switching time and the probability distribution of local electric field variations in the polycrystalline film. The close model fit spanning 5 orders of magnitude in pulse duration indicates the applicability of this model to HZO. This characterization framework can be used to quantify, compare, and optimize the switching dynamics of ferroelectric HZO.

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Resistive switching devices - memristors - present a tunable, incremental switching behavior. Tuning their state accurately, repeatedly and in a wide range, makes memristors well-suited for multi-level (ML) resistive memory cells and analog computing applications. In this brief, the tuning approach based on a memristor-resistor voltage divider (VD) is validated here experimentally using commercial memristors from Knowm Inc. and a custom circuit. Rapid and controllable multi-state SET tuning is shown with an appreciable range of different resistance values obtained as a function of the amplitude of the applied voltage pulse. The efficiency of the VD is finally compared against an adaptive pulse-based tuning protocol, in terms of circuit overhead, tuning precision, tuning time, and energy consumption, qualifying as a simple hardware solution for fast, reliable, and energy-efficient ML resistance tuning.

A foreground calibration algorithm is proposed to digitally self-calibrate a switched-capacitor (SC), pipelined, analog-to-digital converter (ADC). Static errors resulting from capacitor mismatch, charge transfer loss (from limited amplifier dc gain) and variance in Multiplying DAC (MDAC) voltages are estimated and compensated for. The proposed algorithm reuses the electrical components of the pipeline stages to instantiate ∆Σ converters in the stages’ interfaces. By feeding to those converters self-generated input signals and storing the output stream of codes, the algorithm is able to infer the electrical parameters of the reused elements. The algorithm does not require external stimulus or specialized circuitry to be used as true ground but depends on the stages sub-ADC threshold levels precision, diminishing its performance in circuits where error is dominated by sub-ADC input offset. A number of 10-bit ADC’s with a mean uncalibrated Effective Number Of Bits (ENOB) of 6.3 bits where simulated, and a resolution improvement between 2.5 bits, for the best case, and 1 bit for the worst, were observed.

The European physical journal / C Particles and fields C 79(7), 579 (2019). doi:10.1140/epjc/s10052-019-7077-9, A new design of a detector plane of sub-millimetre thickness for an electromagnetic sampling calorimeter is presented. It is intended to be used in the luminometers LumiCal and BeamCal in future linear e+e− collider experiments. The detector planes were produced utilising novel connectivity scheme technologies. They were installed in a compact prototype of the calorimeter and tested at DESY with an electron beam of energy 1–5 GeV. The performance of a prototype of a compact LumiCal comprising eight detector planes was studied. The effective Molière radius at 5 GeV was determined to be (8.1 ± 0.1 (stat) ± 0.3 (syst)) mm, a value well reproduced by the Monte Carlo (MC) simulation (8.4 ± 0.1) mm. The dependence of the effective Molière radius on the electron energy in the range 1–5 GeV was also studied. Good agreement was obtained between data and MC simulation., Published by Springer, Heidelberg

The linearity of charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) is affected by systematic mismatch in its capacitor array. Fabrication phenomena, such as copper dishing, lead to radial gradients in the array, and the detrimental effect of these gradients cannot be mitigated by the use of common centroid layout techniques. In this work, a technique that uses the foreknowledge of radial gradients in order to shape the linearity of data converters is introduced. By choosing the order in which the capacitors within the physical array are connected during a conversion, it is possible to manipulate the converter linearity, and several integral nonlinearities (INLs) shapes can be obtained. This technique, also applicable for any ADC where the static linearity depends upon the mismatch within an array of regularly-placed circuit elements, has been successfully tested for a 10-bit SAR ADC implemented in a 180-nm CMOS process.

© Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ Resistive switching (RS) device (memristor) technology is continuously maturing towards industrial establishment. There are RS devices that demonstrate an “incremental” (analog) switching behavior, whereas others change their state in a binary form. The final achieved resistance is generally a function of the applied pulse characteristics, i.e. amplitude and duration. However, variability —both from device to device but also from cycle to cycle— and the stochastic nature of internal RS phenomena, still hold back any universal tuning approach based solely on these two magnitudes, making also difficult the qualitative comparison between devices with different material compounds owing to the required SET/RESET voltages being dependent on the biasing conditions. In this work we demonstrate experimentally using commercial RS devices from Knowm Inc. that the switching energy is very insensitive to the biasing conditions. We explored experimentally the SET-RESET behavior of bipolar RS devices from the energy point of view. We figured out the quantitative effect of the injected energy to the resistive state of the devices, and proposed an analytical model to explain our observations in the energy consumed by the device during the switching process. Our results lay the foundations for the definition of “resistance change per energy unit” as a performance parameter for this emerging device technology.

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.

The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered 'what is the quantitative effect of the injected energy on the device state?' Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the 'resistance change per energy unit' (dR/dE) can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.

The maximum exploitation of the favorable properties and the analog nature of memristor technology in innovative applications can be guaranteed only by the deeper understanding of their behavior. Fully functional memristors are commercially available. However, lab experiments with memristors are a challenging step. In this direction, this paper presents some important considerations to carry out reliable measurements. Most importantly, the proposed experimental setup is composed of off-the-shelf components and an affordable data acquisition system, showing the way on how to bypass the need for expensive research equipment and expand memristor experimentation beyond research labs and into classrooms.

Charge-sensitive amplifiers (CSAs), widely used as front-ends in pulse processors for capacitive detectors, require a feedback network to set the operation point, deal with leakage currents and restore the baseline voltage upon the arrival of signals. Passive feedback networks are simple and reliable solutions that accomplish the task, but cannot modify the operation point in order to accommodate an input with different polarity, and do not offer sufficient flexibility to deal with a wide range of leakage current or input rates. The Krummenacher feedback solves these drawbacks at the cost of a large compensation capacitor, which is required for stability purposes. In this work, a novel configurable feedback network is presented. Based on the same principle as the Krummenacher network, this circuit relies on the design parameters to ensure stability. This work shows analysis, design and test results from a recent implementation in a 500-nm CMOS process.

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fully differential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along with its theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sized capacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and 39.3fJ per conversion step without considering the clock generator power consumption.

Research progress in neuromorphic hardware, capable of biological perception and cognitive information processing, is leading the way towards a revolution in computing technology. Current research efforts have focused mainly on resistive switching devices, the electronic analog of synapses in artificial neural networks (ANNs), and the crossbar nanoarchitecture, for its huge connectivity and maximum integration density. In this context, this work presents the design and simulation of a memristive crossbar-based ANN for text recognition tasks, implementing a novel computing algorithm. In such case study, important issues during the application mapping process are identified and properly addressed at device and circuit level. The computing capabilities of the proposed system are highlighted through SPICE-level circuit simulations, which show excellent agreement with theoretical simulation results.

The Compact Linear Collider (CLIC) is an option for a future e+e- collider operating at centre-of-mass energies up to 3 TeV, providing sensitivity to a wide range of new physics phenomena and precision physics measurements at the energy frontier. This paper is the first comprehensive presentation of the Higgs physics reach of CLIC operating at three energy stages: sqrt(s) = 350 GeV, 1.4 TeV and 3 TeV. The initial stage of operation allows the study of Higgs boson production in Higgsstrahlung (e+e- -> ZH) and WW-fusion (e+e- -> Hnunu), resulting in precise measurements of the production cross sections, the Higgs total decay width Gamma_H, and model-independent determinations of the Higgs couplings. Operation at sqrt(s) > 1 TeV provides high-statistics samples of Higgs bosons produced through WW-fusion, enabling tight constraints on the Higgs boson couplings. Studies of the rarer processes e+e- -> ttH and e+e- -> HHnunu allow measurements of the top Yukawa coupling and the Higgs boson self-coupling. This paper presents detailed studies of the precision achievable with Higgs measurements at CLIC and describes the interpretation of these measurements in a global fit., 42 pages, 29 figures, accepted for publication in the European Physical Journal C

The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multilevel programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve

FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain human brain-like functionalities at circuit-level. In this context, the memristor has been proposed as the electronic analogue of biological synapses, but the price of commercially available samples still remains high, hence motivating the development of HW emulators. In this work we present the first digital memristor emulator based upon a voltagecontrolled threshold-type bipolar memristor model. We validate its functionality in low-cost yet powerful FPGA families. We test its suitability for complex memristive circuits and prove its synaptic properties in a small associative memory via a perceptron ANN.

The BeamCal detector, one of the calorimeters in the forward region of the International Linear Collider detector, will serve three purposes: ensure hermeticity of the detector for small polar angles, reduce the backscattering from pairs into the detector center, and provide a low-latency signal for beam diagnostics. The BeamCal specifications in terms of noise suppression, signal charge, pulse rate and occupancy pose unique challenges in the front-end and readout electronics design. The Bean - BeamCal Instrumentation IC - is a 32-channel front-end and readout IC that will address the BeamCal instrumentation requirements. By employing switched-capacitor filters and a slow reset-release technique, the Bean will process the signal charge at the International Linear Collider pulse rate. Each channel will have a 10-bit successive approximation analog-to-digital converter and digital memory for readout purposes. The Bean will also feature a fast feedback adder, capable of providing an 8-bit, low-latency output for beam diagnostic purposes. This work presents the design and characterization of the Bean prototype, a 3-channel IC that proves the principle of operation described.

In automatic control education, real examples always improve students' learning and motivation. Considering this fact, a hardware-in-the-loop, low-cost altitude control system for a radio-controlled (RC) airplane has been developed to improve automatic control education. This system constitutes a high-impact demonstrator for teaching automatic control topics, applied to a real-life problem. The airplane has an altitude sensor; students can safely remotely control this variable in a computer real-time environment. This paper addresses the system analysis and description, controller design, and real demonstrations. This device was tested in a basic automatic control course for undergraduate electrical engineering students and received good results; students reacted with curiosity and enthusiasm and encouraged the lecturers to design more experiences like this one.

Metal-oxide-metal (MOM) capacitors represent an attractive alternative to metal-insulator-metal (MIM) capacitors in mixed-signal integrated circuits. Since they are made of metal lines, they can be integrated in standard CMOS processes, and tailored over a wide range of sizes. Mismatch data of MOM capacitors, however, is scarce and typically conservative. Presented is the design and the test results of a custom ADC that employs an array of 1024 MOM capacitors sized at 2 fF. Static performance metrics are presented and compared with those for an ADC based on MIM capacitors. Mismatch data is computed from the results.