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The quality factors and noise performances of superconducting resonators play an important role in microwave SQUID multiplexer (MW-MUX). Since we develop microwave SQUID multiplexer for transition edge sensor arrays, the operation temperature is around 100 mK where the effects of two level system (TLS) can be significant. In this paper, we have investigated the electrode-material or wafer dependence of noise performance of MW-MUX by characterizing four types of resonators. Although the temperature dependence of resonance frequency and the power dependence of ${{\boldsymbol{Q}}_{\boldsymbol{u}}}$ show clear difference among the materials, frequency noises which contribute the readout noise of MW-MUX are similar. Theoretical model predicts that not TLS but other loss dominates ${{\boldsymbol{Q}}_{\boldsymbol{u}}}$ in the power region suitable for the low-noise operation of our MW-MUX. Further, the estimated flux noise calculated from the measured frequency noise and the conversion coefficient from frequency to flux were 1–5 $({{{\mathbf \mu }}{{{\mathbf \Phi }}_0}/\sqrt {{{\mathbf Hz}}} })$ @ 1 Hz, 0.2–0.8 $({{{\mathbf \mu }}{{{\mathbf \Phi }}_0}/\sqrt {{{\mathbf Hz}}} })$ @ 3 kHz. These results indicate the noise of our MW-MUX has small material dependence and the compatible low noise operation to typical dc SQUIDs would be possible. Therefore, the MW-MUX with our materials would not suffer from the low frequency noise due to TLS.

Accepted: 2016-02-17, 資料番号: SA1150323000

We report very-low-noise, fast-response, middle-scale multiplexing in a microwave superconducting quantum interference device multiplexer (MW-Mux) as a transition-edge sensor (TES) readout. Our MW-Mux is able to read 40 channels with 500 kHz sampling and has a low readout noise of 0.9 μ Φ 0 / Hz (where Φ 0 is the magnetic flux quantum), equivalent to 9 pA / Hz. By contrast, a multiplexer of less than 10 pixels with 500 kHz sampling and ∼ 2 μ Φ 0 / Hz readout noise has so far been reported in the literature. Owing to the 500 kHz sampling, our MW-Mux exhibits a fast response to detect a TES pulse with a rise time around 12 μ s. We demonstrated simultaneous readout of 38 pixels from an array of x-ray TES microcalorimeters. The measured full-width values at half-maximum spectral resolution ranged from 2.79 to 4.56 eV, with a median value of 3.30 eV at 5.9 keV, including a ∼ 10 % contribution of readout noise, i.e., 0.9–1.7 eV.

We designed and fabricated rapid single-flux-quantum (RSFQ) circuits using a new 20-kA/cm 2 process based on conventional Nb/AlO x /Nb Josephson junction (JJ) technology. Circular JJs were fabricated to improve their uniformity. They had sufficiently low spread of the critical currents for large-scale RSFQ circuits. We selected the circuit design parameters carefully, including the bias voltage and McCumber-Stewart parameter, balancing the energy consumption, switching speeds, margins, and integration density. We demonstrated several logic gates and shift registers at a clock frequency of 154 GHz with the designed bias voltage of 2.5 mV, and demonstrated energy-efficient shift registers using the low-voltage RSFQ (LV-RSFQ) technique at 83 GHz.

We have fabricated two- and three-dimensional nanostructured superconductors, and observed vortex penetrations by magneto-optical imaging. In the case of two-dimensional superconducting networks with square holes on a square lattice, anomalous diagonal penetrations are widely observed. Two kinds of diagonal vortex penetrations at high and low temperatures have been interpreted as originating from the repulsive interaction of vortices and sharp fan-shaped vortex penetration from the corners of the square holes, respectively. In the case of three-dimensional stack of superconducting strip arrays with double and triple layers, vortex avalanches have been observed in a wide temperature and dimension ranges due to enhanced demagnetization effect. While spotlike avalanches are observed when the overlap of strips is small, anomalous linear avalanches traversing many strips in different layers are observed when the overlap is large. In triple-layer strip arrays, in addition to the spotlike and linear avalanches, vortex penetrations along the line of strips are also observed. Origins of the anomalous diagonal penetration and vortex avalanches are discussed.

We have fabricated three-dimensional double- and triple-layer strip arrays of Nb and observed flux penetration into these strip arrays with an applied field perpendicular to the plane by using the magneto-optical imaging method. In the triple-layer strip arrays with large overlaps between the strips, we observed flux avalanches and one-dimensional penetrations perpendicular to the strip similar to the case of double-layer strip arrays. In thicker triple-layer samples, we also observed flux avalanches parallel to the strip. Enhanced demagnetization effect, thermal conductivity between the neighboring layers, and the driving force parallel to the strip are believed to cause these avalanches.

We describe a large-scale integrated circuit (LSI) design of rapid single-flux-quantum (RSFQ) circuits and demonstrate several reconfigurable data-path (RDP) processor prototypes based on the ISTEC Advanced Process (ADP2). The ADP2 LSIs are made up of nine Nb layers and Nb/AlOx/Nb Josephson junctions with a critical current density of 10 kA/cm2, allowing higher operating frequencies and integration. To realize truly large-scale RSFQ circuits, careful design is necessary, with several compromises in the device structure, logic gates, and interconnects, balancing the competing demands of integration density, design flexibility, and fabrication yield. We summarize numerical and experimental results related to the development of a cell-based design in the ADP2, which features a unit cell size reduced to 30-μm square and up to four strip line tracks in the unit cell underneath the logic gates. The ADP LSIs can achieve ∼10 times the device density and double the operating frequency with the same power consumption per junction as conventional LSIs fabricated using the Nb four-layer process. We report the design and test results of RDP processor prototypes using the ADP2 cell library. The RDP processors are composed of many arrays of floating-point units (FPUs) and switch networks, and serve as accelerators in a high-performance computing system. The prototypes are composed of two-dimensional arrays of several arithmetic logic units instead of FPUs. The experimental results include a successful demonstration of full operation and reconfiguration in a 2×2 RDP prototype made up of 11.5k junctions at 45 GHz after precise timing design. Partial operation of a 4×4 RDP prototype made up of 28.5k-junctions is also demonstrated, indicating the scalability of our timing design. key words: advanced process, cell-based design technique, high-end computing, large-scale integration, rapid single-flux-quantum circuits

We have fabricated three-dimensional double-layer strip arrays of Nb and observed flux penetrations into these strip arrays with applied field perpendicular to the plane by using the magneto-optical imaging method. In strip arrays with large overlaps between strips we observed flux avalanches even at 1.5 K below the critical temperature. Novel flux avalanches showed up as one-dimensional penetrations perpendicular to the strip arrays in samples with the maximum overlap. Enhanced demagnetization effect and thermal conductivity between the top and bottom layers are believed to cause these avalanches.

A cryogenic current comparator (CCC) is an instrument of great importance in electrical metrology, which provides a ratio of two currents with ultimate accuracy based on superconductivity. It is used for dc resistance calibration in many national metrology institutes. Conventional CCCs consist of multi-turn coils of wire windings, a multi-layered shield of superconductor foils and a separate SQUID sensor. This implementation results in a bulky device too massive to cool with a mechanical cryocooler, making a system inconvenient. A new implementation of CCC, an integrated CCC (ICCC) consisting of thin-film spiral coils, a thin-film superconducting shield and a SQUID sensor integrated on a single chip, enables a user-friendly system operated with a compact cryocooler. Prototype ICCC chips were designed and fabricated by using a superconducting Nb integrated circuit technology with chemical-mechanical polishing. The basic operation of the prototype ICCCs was confirmed by monitoring periodic flux-voltage characteristics of the SQUIDs.

We have been developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. The SFQ floating-point adder (FPA) is one of the principal and most complicated circuit blocks in an LSRDP. In this study, we designed and implemented component circuits of an SFQ bit-serial half-precision FPA using the cell library for a 10-kA/cm2 Nb process and performed on-chip high-speed tests. We demonstrated correct operation of the four-bit shifter for the significand at the clock frequencies of up to 76 GHz. The dependence of the measured DC bias margin on the operating frequency agrees reasonably well with the margin calculated using a digital simulation. The operation of the normalizer for the significand has been also confirmed at low speeds.

This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2 and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.

We investigated the most suitable device structure for large-scale SFQ circuits and propose a new Nb 10-layer device structure that is composed of active layers including junctions at the top, PTL layers in the middle and DC power layers at the bottom. This device structure enables us to reduce the influence of the magnetic field due to large bias currents and to form a Nb/AlOx/Nb junction layer in the last part of the fabrication sequence. To achieve this structure, we developed a higher quality planarization that could remove the residual slight roughness after standard caldera planarization. We fabricated a diagnostic chip that is composed of test elements such as junctions, contacts, resistors and many kinds of process test patterns. We obtained sufficient characteristics for the diagnostic chips. Moreover, to evaluate the fabrication process, we designed and fabricated several shift registers. We confirmed the correct operation of an up to 2560-bit shift register having 10,281 junctions.

We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm2 Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.

We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2 deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.

We have studied single-flux-quantum (SFQ) propagation properties in passive transmission lines (PTLs) based on a 10-Nb-layer device structure (ADP2). In ADP2, we can use the PTLs with a line width about 5 mum, one seventh of conventional line width by adopting a strip line (SL) structure and increasing the characteristic impedance. The evaluation has been conducted on the PTL length and the via-hole structure by using ring oscillators. We found that the decrease in the operating region was larger for longer PTL, compared with that in a conventional device structure (STD2). The results would be caused by the increase in the surface resistance. The via-holes connecting the PTLs on different layers have more complicated structure than those of STD2. We have designed the via-hole structure using the electromagnetic wave simulator HFSS. As a result, we have demonstrated sufficiently large operating margins at any data rates up to 80 Gb/s even for the ring oscillator with 30 via-holes.

We have evaluated the effects of a DC power (DCP) layer in a 10-Nb-layer device using SQUIDs and large-scale Josephson transmission lines (LS-JTLs). The 10-Nb-layer device has recently been developed for SFQ LSIs, with an active layer including Josephson junctions (JJs) at the top, two passive transmission line layers in the middle, and the DCP layer for bias current feeds at the bottom. The evaluation with SQUIDs revealed that the 10-Nb-layer device structure drastically reduced the magnetic flux induced by DC currents flowing through the DCP line, in comparison with the previous advanced process device structure. A major factor for this reduction was an increase in the number of ground layers between the DCP layer and the active layer. In the test of the LS-JTLs containing about 12000 JJs, we obtained the operating margins as wide as numerically simulated ones. We also observed no difference in the margins between a method for extracting ground return currents through ground layers and that through the dedicated layer. These results demonstrated that the 10-Nb-layer device structure is suitable for SFQ-LSIs.

We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.

We have developed an advanced fabrication process for fabricating Nb integrated circuits with up to nine planarized Nb layers, and with critical current density of Josephson junctions of 10 kA/cm2. We have continued to improve this advanced process. For nine-layer integration, we readjusted film thickness of Nb and SiO2 layers in order to reduce the strain of films and substrate. Total film thickness of the nine-Nb layered structure was about 3 mum; this was kept nearly as thin as that of the six-Nb-layered structure. The resulting thinner SiO2 layers enabled narrower passive transmission line wiring, which had the advantage of smaller occupation area. The room temperature measurement of process monitoring patterns is useful for screening defective wafers in the middle step of the process. For higher circuit reliability, we modified fabrication processes such as junction planarization. As a result, the reliability of SiO2 insulation between an upper and a lower Nb wire adjacent to a Josephson junction was improved.

To achieve larger scale and higher speed single flux quantum (SFQ) circuits, we have been developing a 10-kA/cm2 Nb multi-layer fabrication process composed of more than six pla- narized Nb layers, an Nb/AlOx /Nb junction layer, a Mo resistor layer, and SiO2 insulator layers. To evaluate reliability of the fabrication process, we have designed superconducting random access memories (RAMs) with four different memory capacities: 256, IK, 4 K, and 16 K bits. Although the circuit configuration of these RAMs is almost the same as that of previously developed ones that have conventional latching devices, we modified the circuit parameters and layout design based on specifications of the new fabrication process. We have obtained operations for the 256-bit RAM with a bit yield of 100%, the lK-bit RAM with a bit yield of 99.8%, and the 4K-bit RAM with a bit yield of 96.7%. The number of defects in the 4K-bit RAM was estimated to be approximately 10. We confirmed that evaluations using the RAMs were effective at detecting defects due to the fabrication process.

Large-scale SFQ integrated circuits require a large amount of dc-bias current. The magnetic fields induced by the dc-bias currents and the return currents flowing in a ground plane have a great influence on the performance of SFQ circuits. As an approach to reduce the influence, the dc-power (DCP) layer placed under a ground plane is newly introduced in SRL advanced Nb process. We have experimentally evaluated the effects of the DCP layer using SQUIDs and large-scale Josephson transmission line (JTL) circuits with more than 10,000 junctions. The SQUIDs showed that there was small magnetic flux coupling between the DCP lines and themselves and that the coupled flux was enhanced by the return current. The coupled flux decreased with increasing line width of the DCP lines and with increasing distance from the centerlines of them. In the large-scale JTL tests, the cells with DCP patterns showed wider operating margins than the CONNECT OPEN cells with partial magnetic shielding of bias current lines. The test results also showed that a line shape along the periphery of a cell was more effective than a plane shape within a cell as a DCP layer pattern for bias current feeds.

Submicron Nb/AlOx/Nb junctions having high critical current density of more than 20 kA/cm2 are required for realizing single-flux-quantum (SFQ) circuits operating at a high speed of more than 100 GHz. We have developed a 20 kA/cm2 process having submicron circular junctions. 1000-serially-connected circular shape junctions having six different diameters of 0.5 μm, 0.564 μm, 0.7 μm, 0.9 μm, 1.1 μm, and 1.3 μm have been designed. The 0.564 μm junction is designed to be 50 μA with critical current density of 20 kA/cm2, which is a minimum current value of a target SFQ circuit design. We totally fabricated 12 wafers with the 20 kA/cm2 process. The 1σ spread of critical currents (Ic) depending on junction sizes and the run-to-run reproducibility of critical current densities are reported as a summary of these fabrications. We obtained Ic scattering of 1σ≤ 2% even in the minimum circular junction of 0.25 μm2 in several fabrication runs.

The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.

We developed a 10 kA/cm 2 Nb fabrication process, whose device structure was composed of six planarized Nb-layers, an Nb/AlO x /Nb junction layer, an Mo resistor layer, and SiO 2 insulator layers to make larger scale, higher speed single-flux-quantum (SFQ) circuits that have more than 100 k junctions.It is very important to evaluate the process reliability in relation to the uniformity of the device parameters and the defect rate of the fabrication process. To evaluate the process reliability, we designed and tested many kinds of process test circuits, including 100 k junctions and 60-k serially connected contacts. We obtained excellent insulation properties, even in the six-Nb-layer structure. The standard deviations of the critical currents for 2000 1.2-μm-square junctions were less than 1.9%. We obtained a critical current of more than 8 mA, even for the 60-k serially connected contacts. Based on these results, we obtained sufficient reliability to realize the SFQ circuits including more than 100 k junctions.

Series Nb/AlO x /Nb junction array circuits are commonly used for evaluation of a critical current ( I c ) spread as an important parameter on Nb-based LSI chips. We present a junction array circuit suitable for accurate evaluation of the spread. The circuit has a tolerance for the I c suppression caused by external noises and synchronous switching which are often observed in measurements. Key elements of the circuit are the low value resistors, large value capacitors, and high value resistors inserted between wires and chip bonding pads. This paper describes effects of these key elements on current–voltage characteristics of junction arrays.

To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

The authors evaluated the effect of photomask pattern shape for a counter-electrode on critical current I/sub c/ uniformity and controllability in Nb/AlOx/Nb junctions. Circular, square, and 2 kinds of optical proximity correction (OPC) square patterns were used as the mask pattern shape. Although there was no difference in the I/sub c/ uniformity between square and OPC junctions, the OPC junctions exhibited smaller shrinkage in junction size than the square junction. In addition, the OPC junctions improved the chip-to-chip variation in the shrinkage. The circular junction exhibited the smallest variation in the shrinkage, and had an advantage in I/sub c/ uniformity for smaller than 1.0 /spl mu/m/sup 2/ junctions in comparison with the other junctions. The shrinkage of the circular junction was the largest of all the junctions. This paper describes the recommended choice of the photomask pattern shape for several Nb LSI technologies.

Mechanical polishing (MP) is a key technology for fabricating multi-layer, large-scale integrated Nb SFQ circuits. This process, however, could possibly influence junction characteristics. We studied the impact of a planarization process based on MP on the junction characteristics. The process, performed either before or after junction fabrication, did not significantly degrade the junction characteristics. We successfully demonstrated multi-layer integrated circuits with six Nb layers planarized by MP.

We have been developing a 10-kA/cm2 advanced Nb process in order to fabricate larger scale and higher speed SFQ circuits with over 100k junctions. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, 4 Nb wiring layers, a Nb layer for DC power, a Nb ground plane, SiO2 insulator layers, and a Mo resistor layer. Process technologies for fabricating 1.0-μm2 junctions with high JC of 10 kA/cm2 and 1σ of 1.4% and Mo resistors with R□ of 2.4 Ω have been developed. A new planarization technology called caldera, which is applicable to patterns of various sizes, has been developed. This process consists of reactive ion etching (RIE) with a reverse mask, bias sputtering, and mechanical polishing planarization (MPP). We have now successfully developed all the component technologies required for the advanced Nb process. We have implemented these technologies for the through process and fabricated a structure with six planarized Nb layers, including Nb/AlOx/Nb junctions, Mo resistors, and contacts. In this structure, we obtained excellent current–voltage characteristics for the junctions, sufficient superconducting characteristics for the contacts, and good insulation characteristics between the wiring layers.

We have been developing a 10 kA cm−2 Nb advanced fabrication process to make larger scale and higher speed SFQ circuits that have over 100k junctions. The main challenges in implementing this process are related to increasing the critical current density of junctions, decreasing design rules and increasing the number of Nb layers. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, Nb wiring layers, Nb shield layers, a Nb layer for dc power, a Nb ground plane, SiO2 insulator layers and a Mo resistor layer. In fabricating this multi-layer structure, we have developed a new planarization technology which enables the flattening of the SiO2 insulator surface over the Nb wiring layer independent of the pattern sizes of the Nb wirings. This planarization technology consists of SiO2 bias sputtering, reactive ion etching with a reversal mask of the Nb wiring and mechanical polishing planarization. The SEM photographs showed excellent flatness for the planarized multi-layer structure.

We have made a prototype superconducting double-loop lowpass sigma–delta modulator with a parallel multiple-flux-quantum feedback driver. The feedback driver consists of multi-stage SFQ splitters and SQUID-gates connected in series. The multi-stage splitters forming a binary-tree structure produce multiple numbers of flux quanta for the feedback gain and switching of the SQUID-gates gives feedback to the first integrator. A simulation showed that the feedback duration of the SQUID-gate type was only 20 ps, whereas our earlier type with a ladder circuit of gain 20 requires 526 ps. This reduction of the feedback duration enables much higher speed operation. The fabricated modulator with SQUID-gates was operated at the sampling frequency of 1.2 GHz and showed noise shaping roughly of the second-order.

In order to establish double-loop feedback design, we have fabricated a prototype superconducting double-loop lowpass sigma-delta modulator. For digital feedback gain, multiple flux quanta are produced by a ladder circuit and carried through Josephson Transmission Lines (JTLs) to the feedback driver. The feedback driver consists of a single Josephson junction or two serially-connected junctions. Direct injection of the pulse current from the JTLs through a low-value resistor drives the feedback driver. The sigma-delta modulator was operated at the sampling frequency of 1.1 GHz and the measured power spectrum showed the noise shaping roughly of 12 dB/octave, which is characteristic of the second-order sigma-delta modulator.

In order to develop superconducting Digital Signal Processors (DSP's), we have been studying a superconducting 1-bit Arithmetic Logic Unit (ALU). This ALU has the simplest function of AND, OR, ADD (addition), and SUB (subtraction). The ALU operates in a 3-stage pipeline. All logic functions such as AND, OR, and SUM (summation) can be executed within a single stage of the pipeline. In order to achieve the high-speed operation of the ALU, we proposed and designed a novel 3-input XOR gate, which can operate in only one logic stage. Our simulation study showed that all components of the ALU can operate up to 50 GHz. These ALU components were fabricated and tested at low speed. Large bias margins of more than /spl plusmn/37% were achieved. The designed ALU's were laid out and fabricated with an Nb process. The ALU occupied the area of 1200 /spl mu/m /spl times/ 2600 /spl mu/m, which contains 560 Josephson junctions (JJ's).

We have been developing a superconducting second-order sigma-delta analog-to-digital converter with a large bandwidth and a large dynamic range for software radio applications. In a superconducting second-order sigma-delta modulator utilizing a passive integrator and single-flux-quantum (SFQ) feedback, gain to compensate the large attenuation in the passive integrator of the modulator is required to obtain a large dynamic range. In this paper, a second-order modulator utilizing multi-flux-quantum (MFQ) generators creating the needed gain is reported and the design and experimental test results of the elementary circuits including a comparator, a first-order modulator, and the MFQ generator are described. The digital outputs of the comparator and the first-order modulator were experimentally evaluated, where the input dependence of the comparator switching probability and the noise-shaping properties of the modulator were clearly observed. The low speed operation of the MFQ generator creating three SFQ pulses was experimentally confirmed. The other circuits were also tested at low frequencies.

We report simulated results of-rapid single flux quantum (SFQ) circuits having driver, receiver, and passive transmission lines for propagating SFQ pulses to investigate the design criteria. We have studied the equivalent input/output resistance of the driver/receiver in various bias conditions and found that the resistance is almost proportional to the bias current of the driver/receiver. Furthermore, we have proposed inserting a series resistor at the end of the superconducting passive transmission line (PTL) for avoiding undesirable flux trapping in the loop and for isolation in regard to the DC current. We also found that the reduction of the bias margin due to the resistance is rather small when the resistance is much smaller than the impedance of the PTL. An operating margin of more than 30% was obtained in the driver/receiver circuits including the PTL and the series resistor.

A mechanical polishing planarization (MPP) process is developed with an endpoint detection method. MPP makes it possible to form self-aligned contacts on small junctions and to decrease parasitic inductance. It can also control the thickness of the insulation layers precisely. MPP was used to fabricate a 22 /spl mu/m/spl times/22 /spl mu/m vortex transitional memory cell and the cell operated correctly. The reliability of interlayer insulation was increased for 64-Kbit memory cell arrays fabricated using MPP. It is concluded that MPP is an effective technology for fabricating high-density Josephson circuits.

A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power consumption and very small switching energy. In this paper, we report a new AQFP cell library designed using the AIST 10 kA cm−2 Nb high-speed standard process (HSTP), which is a high-critical-current–density version of the AIST 2.5 kA cm−2 Nb standard process (STP2). Since the intrinsic damping of the Josephson junction (JJ) of HSTP is relatively strong, shunt resistors for JJs were removed and the energy efficiency improved significantly. Also, excitation transformers in the new cells were redesigned so that the cells can operate in a four-phase excitation mode. We described the detail of HSTP and the AQFP cell library designed using HSTP, and showed experimental results of cell test circuits.

We have developed a Josephson 4-Kbit RAM with improved component circuits and a device structure having two Nb wiring layers. A resistor coupled driver and sense circuit are improved to have wide operating margins. The fabrication process is simplified using bias sputtering, as a result, its reliability is increased. The RAM is composed of approximately 21000 Nb/AlO/sub x//Nb Josephson junctions, Mo resistors, Nb wirings, and SiO/sub 2/ insulators. Experimental results show a minimum access time of 380 ps and power dissipation of 9.5 mW. Maximum bit yield of 84% is obtained in minimum magnetic field of about 20 /spl mu/G. We confirm that most of fail bits are caused by trapped magnetic flux, and the RAM functions properly for 98% of the memory cells after measuring fail bit map several times. >

We have developed the smallest Josephson nondestructive read-out (NDRO) memory cell, called a vortex transitional (VT) memory cell, for a Josephson high-speed 16-Kbit RAM. Its size is 22/spl times/22 /spl mu/m/sup 2/, which is only 16% of the size of previously developed VT memory cells used in Josephson 4-Kbit RAM. This is achieved by developing a vertically integrated device structure and refining small-junction technology. The cell consists of Nb/AlO/sub x//Nb junctions, three Nb wirings, SiO/sub 2/, insulators and Mo resistors. The VT memory cells operate properly, with a large operating margin of /spl plusmn/20%. >

To confirm a gigahertz frequency power supply in a multichip system, three-stage superconductive filter-type powering device (SFPD) chips and a resistive load chip for a 500 gate Josephson device were designed and fabricated. Low-loss capacitors required for this gigahertz operation were also developed. The authors tested the operation of the three-stage SFPDs in a multichip configuration with resistive load. A superconductive power supply with frequencies as high as 2.0 GHz was demonstrated in a multichip system for the first time. For a 2.0-GHz SFPD, normal operation was confirmed with a resonant frequency of 2.1 GHz, a resonant level of -31 dB, and a current gain of 22.4. The 0.1- Omega input impedance of the device system was successfully transformed to 49.9 Omega . >

A fully decoded 4-kb Josephson nondestructive readout high-speed RAM with vortex transitional memory cells was designed and operated successfully. The 4-kb Josephson RAM is composed of 64-b*64-b cells, polarity-convertible drivers, address decoders using resistor coupled Josephson logic (RCJL) gates, and a resistively loaded sense circuit. The memory cells use vortex transitions in their superconducting loops for writing and reading data. The cells are activated by two control signals without timing control, while all peripheral circuits are activated by an AC power supply. This memory configuration eliminates the timing sequence needed for memory operations, resulting in a decrease in the memory operation time for an actual memory chip. The 4-kb Josephson high-speed RAM was fabricated using niobium planarization technique with a 1.5- mu m design rule. The RAM circuit size is 4.8*4.8 mm/sup 2/ and the memory cell is 55*55 mu m/sup 2/. More than 25000 Nb-AlO/sub x/-Nb Josephson junctions with approximately 1200 A/cm/sup 2/ critical current density are contained in the RAM chip. An access time of 580 ps and a power consumption of 6.7 mW are obtained for the nondestructive memory operation.

White noise of dissipationless microwave radio frequency superconducting quantum interference device (RF-SQUID) multiplexers has been experimentally studied to evaluate their readout performance for transition edge sensor (TES) photon counters ranging from near infrared to gamma ray. The characterization has been carried out at 4 K, first to avoid the low-frequency fluctuations present at around 0.1 K, and second, for a feasibility study of readout operation at 4 K for extended applications. To increase the resonant Q at 4 K and maintain low noise SQUID operation, multiplexer chips consisting of niobium nitride (NbN)-based coplanar-waveguide resonators and niobium (Nb)-based RF-SQUIDs have been developed. This hybrid multiplexer exhibited 1 × 104 ≤ Q ≤ 2 × 104 and the square root of spectral density of current noise referred to the SQUID input √SI = 31 pA/√Hz. The former and the latter are factor-of-five and seven improvements from our previous results on Nb-based resonators, respectively. Two-directional...

We have been developing a superconducting sigma-delta analog to digital converter (ADC) with a large dynamic range for software-radio applications. For an ADC with a larger dynamic range, we propose a new double-loop sigma-delta modulator utilizing single flux quantum (SFQ) pair generation. In circuit simulation, a dynamic range of 72 dB was obtained at 100 MHz for a 12 GHz clock, where the modulator was designed for the NEC Niobium standard process. Preliminary operation of a sigma-delta modulator has also been tested experimentally for a single-loop modulator to confkm our modulator design.

We have developed a coding technique to drive an overdamped Josephson junction array (JJA) using modulated optical pulses for voltage standard applications. Our system is composed of a multi-channel pulse pattern generator (PPG), a LiNbO3 (LN) modulator with an electrical multiplexer (MUX), a photodiode (PD), and an over-damped JJA cooled with 4 K GM cryocooler. The modulated optical pulses are transmitted via an optical fiber to a PD that is installed close to the JJA on a cold stage, and they are then converted into an electrical current pulse train in order to drive the JJA. To avoid a problem in our LN modulator system, i.e., the duty-ratio dependence of the output pulse waveform, pseudo signals that maintain the duty ratio at approximately 50% are inserted in the original bit stream. We demonstraited that this technique is applicable for arbitrary return-to-zero (RZ) binary bit streams.

In order to establish a quantum ac voltage standard at NMIJ/AIST, we have developed a Josephson arbitrary waveform synthesizer based on overdamped Josephson junction arrays (JJAs) using optoelectronics and a liquid helium free compact cryocooler. We have succeeded in the generation of sine waves at 60 Hz and 152.6 kHz. To verify the performance of the system, two different types of JJAs with different characteristic frequencies have been developed. An application to a quantized voltage noise source for Johnson noise thermometry is also discussed, with experimental results.

The authors have developed a Josephson 4 Kbit RAM with vortex transitional memory cells and resistor coupled drivers. The RAM is fabricated by 1.5 mu m Nb technology with approximately 21000 Nb/AlO/sub x//Nb Josephson junctions. 380 ps access time, 98.6% bit yield, and 9.5 mW power dissipation have been experimentally obtained in the 4 Kbit RAM chip. >

Josephson 1-kbit random access memories (RAM's) have been fabricated using Nb multilayer planarization technology with Nb/AlO/sub x//Nb junctions and Mo resistors. The RAM design has been reported previously. The RAM consists of a 32*32-bit nondestructive readout (NDRO) memory cell array and peripheral circuits. The NDRO memory cell consists of a loop storing three flux quanta and two 3-junction interferometer gates. The peripheral circuits consist of decoders with address inverters, drivers, a sense circuit and reset circuits, where resistor-coupled Josephson logic (RCJL) circuits are used as basic circuits. The RAM circuit size is 4.4*4.4 mm/sup 2/, and the memory cell size is 65*65 mu m/sup 2/. About 10000 Nb/AlO/sub x//Nb junctions with 1030-A/cm/sup 2/ critical current density were contained in the RAM. Minimum line and space widths were 3 and 2 mu m, respectively. The Mo resistors had 1.2 approximately 1.3 Omega sheet resistance. About 40 percent of the bits were successfully operated with a +or-18-percent bias margin. A minimum 570-ps access time with 13-mW power dissipation was obtained for the highest peripheral circuit bias conditions. >