Search

A 5 bit sample-and-hold less pipelined ADC is presented for high speed and low power applications. The architecture is designed using 32nm CNFET model in Hspice and simulation is carried out at 10 GSPS sampling rate. From the simulation results, the SNDR is found out to be 32.89dB at Nyquist frequency and the ERBW is found to be 3GHz from 2 to 5GHz in which ENOB is guaranteed to be above 4.6. The average power consumed is 5.031mW for a supply voltage of 1.4V and FoM is 53.32fJ/step.

Valued Logic (MVL) is emerging as a promising choice for future computing technology. MVL has seen major advancement in the recent past due to several advantages offered by them over the binary logic, thus making it a thrust area for further research. The instruction set of the processor is its inherent entity. This paper presents design and implementation of an efficient instruction set for a ternary processor using Very-High-Speed Integrated Circuits, VHSIC Hardware Description Language (VHDL). Twenty one instructions including various addressing modes such as register, direct and immediate mode are designed and implemented for 4-trit ternary processor. The required control signals are appropriately identified in the proposed design and enable the smooth operation of instructions. The designed 4 - trit instruction set signifies encouraging results that will pave the path for further developments in ternary processors.

The Scaling of conventional CMOSs (Complementary Metal Oxide Semiconductors) has been facing problems such as short channel effect due to hot electron effect and leakage power. To solve the problems, FinFETs (Fin Field Effect Transistor) device structures are solution. Binary System occupies large area there for the circuit complexity is increasing on a VLSI chip and thus, degrading the performance of binary system. MVL (Multi valued logic) is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip, we have designed ternary Static Random Access Memory (SRAM) Cell using Shorted Gate FinFET (SG-FinFET). FinFET is double gate transistor architecture to extend scaling over planar device. Two gates have better control over the short channel effects. The paper presents a novel design of 6 Transistor ternary SRAM cell, with separate read and write lines. The proposed SRAM cell designed using Tanner tool version 13 and simulated with the help of W-Edit version 13.

The design of a high Gain microstrip patch antenna array using microstrip line feed is presented in this paper. The design has been done for C band application at 5.81GHz for Rainfall RADAR also called as Precipitation Occurrence Sensor System (POSS). Array consisting of 16 elements of 4×4 were designed and simulated using HFSS v13 on Taconic TLY substrate of dielectric constant 2.2 and height of substrate equal to 1.58 mm. For the proposed antenna, the achieved gain is 19.5 dBi, return loss is ≤ 30 dB, 3 dB bandwidth of 170 MHz with low side lobes and back lobe. The Array antenna was excited by uniform amplitude and phase feeding method. A comparative analysis was done between 1×2, 2×2 and 4×4 array. It was found that gain increases at cost of bandwidth.