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A combined heat and power (CHP) system generates electricity from thermal energy and generates heat by utilizing the remaining thermal energy. The system efficiency of the cogeneration system is 75–85 %, which is very high compared to existing only power generation facilities, so it is very useful for energy conservation and environmental protection. For this reason, interest in the cogeneration system is increasing worldwide. Generally, a cogeneration plant consists of a steam turbine alone or the combined power generation of a gas turbine and a steam turbine depending on the scale. The steam turbine is divided into a back-pressure type turbine and a condensing type turbine depending on the operational methodology of the steam turbine. In both cases, the shift in the return temperature of the district heating users influences the performance of the cogeneration plant, thus affecting the power generation costs of the power plant. It is possible to accurately estimate the change in the unit cost of the power generation caused by these changes, and to inflict it on the user, thereby changing the usage pattern of the user and reducing the energy consumption accordingly. In this study, the commercial combined cycle cogeneration system using back - pressure type turbine was simulated, and the change of performance of the combined heat and power plant was analyzed while changing the user facility’s total return temperature. Based on the results of this analysis, a possible loss in the plant according to the change of return temperature was predicted. Also the effect of each user’s return temperature on the plant loss was analyzed using an actual user’s return temperature data. The economic-mechanical approach, such as this study, can alleviate dissatisfaction with the user’s charge and to consume energy in a more rational way. It eventually can play a role in reducing carbon emissions.

In this study, MoFe alloy decorated onto reduced graphene oxide (RGO) nanohybrids is successfully synthesized with various volume ratios of Fe to Mo precursors using a dry plasma reduction method at a low temperature and under atmospheric pressure and is introduced for the first time as an electrocatalyst for counter electrodes (CEs) in dye-sensitized solar cells (DSCs). As observed by HRSEM and TEM analyses, MoFe is successfully immobilized on a 3D network structure of RGO. Well-dispersed MoxFe1−x (0 ≤ x ≤ 1) NPs ranging in size from 2 to 6 nm are stabilized with RGO after co-reduction of the metal precursor ions and graphene oxide. The developed catalysts are then applied as CEs in DSCs. As a result, the Mo0.7Fe0.3/RGO nanohybrid exhibited the highest electrocatalytic activity, corresponding to the lowest charge transfer resistance of 0.11 Ω, among the electrodes tested. The DSC employing Mo0.7Fe0.3/RGO CEs exhibits 5.44% efficiency, which is higher than the 1.26, 4.54 and 4.53% efficiency rates for cells using RGO, Mo0Fe1/RGO and Mo1Fe0/RGO electrodes, respectively, due to the optimization of the catalytic activity and the electron conductivity of the developed materials. Note that the efficiency of the device using a Pt electrode was 5.36% under identical conditions. This study concludes that the CE based on the MoFe/RGO nanohybrid is a prospective substitute for Pt which can provide new opportunities for advancing high-efficiency DSCs. Furthermore, the developed catalysts can be applied to other applications, such as methanol oxidation and oxygen reduction reactions. Keywords: Dry plasma reduction, MoFe alloy, Reduced graphene oxide, Counter electrode, Dye-sensitized solar cell

The development of Ni-based nanoalloys has been extensively explored due to their low cost, high activity, and durability in the hydrogen evolution reaction (HER). Structural design of Ni-based nanoalloys is a promising approach to attain excellent electrocatalytic activity as well as stability of these catalysts. This study reports a facile method to prepare NixRhy nanosponges while using NaBH4 as a reducing agent without any surfactant. The ratio of Ni and Rh has been changed to obtain various NixRhy electrocatalysts (Ni, Ni3Rh1, Ni1Rh1, Ni1Rh3, and Rh), respectively. Among the prepared catalysts, Ni1Rh3 electrocatalyst exhibits a high electrocatalytic activity with an overpotential of 48 mV at a current density of −10 mA cm−2 and a superior stability even after 2000 cycles of CV in 0.5 M H2SO4 electrolyte. In addition, the Ni1Rh3 electrocatalyst shows good electrocatalytic activity in 1.0 M KOH electrolyte compared to commercial Pt/C (20 wt% of Pt) (c-Pt/C). Moreover, the overall water splitting system of the Ni1Rh3 cathode and the commercial RuO2 anode is evaluated, not only exhibiting excellent performance with a potential of 1.52 V at a current density of 10 mA cm−2, but also proving very stable operation for over 100,000 s in 1.0 M KOH electrolyte.

To realize a flexible and ultra-low power non-volatile resistive random access memory (NVRRAM), we propose a 3 × 3 resistive memory array comprised of crossbar memristors and a pull-up resistor connected to each column bar (1R-CM). This architecture forms a voltage divider network, which directly reads a parallel data of a row in the form of voltage instead of current. In the proposed structure, the optimum value of the pull-up resistor was found to be 10 MΩ. Poly(4-vinylphenol) (PVP) material is utilized in the memristor to achieve high OFF/ON resistance ratio of ∼1000 as a high resistance state (HRS) is 10 GΩ and a low resistance state (LRS) is 10 MΩ. The operating voltage for writing and reading are ±2 V and 0.5 V in current bound of 10–100 nA, respectively, and consumes ultra-low power (

Nanoscale memristors can be used as synapses in brain-mimicking neuromorphic systems. Here, the fine tuning of memristor conductance is important in controlling the synapse weights precisely, because the coarse tuning of memristor synapses can cause a significant error in neuromorphic processing. In this paper, we propose a new Pulse Amplitude Modulation (PAM) method for the fine tuning of memristor conductance. The new PAM scheme is verified by the experimental measurement of real memristors, where the new PAM could reduce the pulse-to-pulse fluctuation in conductance change per pulse by 84.8%, compared to the previous linear PAM. For comparing the linear and new PAM schemes, they are tested in programming memristor synapses in the memristor-based Cellular Neural Networks (CNN). The simulation result confirms that the new-PAM-programmed CNN shows better quality of edge detection than the linear-PAM-programmed CNN.

Pattern matching or pattern recognition is one of the elemental components that constitute the very complicated recalling and remembering process in human’s brain. To realize this neuromorphic pattern matching, we fabricated and tested a 3 × 3 memristor synaptic array with the winner-take-all method in this research. In the measurement, first, the 3 × 3 Ta2O5 memristor array is programmed to store [LLL], [LHH], and [HLH], where L is a low-resistance state and H is a high-resistance state, at the 1st, 2nd, and 3rd columns, respectively. After the programming, three input patterns, [111], [100], and [010], are applied to the memristor synaptic array. From the measurement results, we confirm that all three input patterns can be recognized well by using a twin memristor crossbar with synaptic arrays. This measurement can be thought of as the first real verification of the twin memristor crossbar with memristive synaptic arrays for neuromorphic pattern recognition.

By utilizing electro-hydrodynamic (EHD) technique, we propose an organic non-volatile memory cell capable of storing one bit data. It consists of an organic resistor and a memristor, which stores a bit in the memristor and be read by a voltage divider operation. The proposed device is fabricated by utilizing the materials poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) for resistor and zirconium dioxide ( ZrO 2 ) for memristor. The fabricated device is in the size of 4 mm × 2 mm, and thickness of the memristor and the resistor are 76 nm and 1 μm, respectively. To verify the device, reliable read/write operations are presented for more than 100 cycles. The device is also measured a stable performance against bending, and a minimum applicable bending diameter is 12 mm. The device is analyzed for surface morphology by taking SEM images.

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

A modular compact model for memristors which describes a wide range of memristive devices is presented. Its modular structure enables the modeling of various device behaviors by adopting different functions inside the comprising blocks. Rooted from the theoretical analysis on ideal memristors, the window function of the model is uniquely based on the constitutive relationship between charge and flux. This not only solves the stability issue from previously reported models, but also reveals that an equivalent charge-flux constitutive relationship can always be obtained from a variety of memristive devices. Simulations on three types of memristive devices demonstrate that the model is able to reflect common memristive device properties such as limited memristance switching range, linear/nonlinear memristance switching rate, threshold voltages for SET/RESET, nonlinear I-V characteristics, and device parameters with variations.

Memristors-based resistive logic computation units are introduced. By controlling the memristors' conditional set operation adaptively to one of the input polarities, bipolar signal multiplication of an input and a stored reference bit is performed by unipolar memristor devices and control switches. The multiplication result is registered in an output nonvolatile memristor so that the computed output can be accessed anytime later on by reading the output memristor's state. A memristive multiplier circuit demonstrates a fast and highly sensitive pattern recognition for highly complex inputs.

A compact circuit model and physical hardware emulation for floating memristors are presented. By utilizing memristor 'resistance' as a state variable, and constructing a hardware emulator using a low-complexity modular structure, the model-based emulation can replicate diverse behaviors of different device types. Our hardware emulator for a voltage-actuated, threshold sensitive, two-terminal, floating memristor demonstrates experimentally memristor dynamics. The emulator is capable of computing any arithmetic operations without any disturbance associated with composition of modular structures.

Content Addressable Memory (CAM) is beneficial to applications that require high-speed pattern searching as it provides fast associative lookup operations. As the amount of data to search continues to grow, reducing power consumption while minimizing the costs for speed and area is the main thread of research in designing large capacity CAMs. In this work, we are presenting an active memory architecture incorporating a searchable resistive memory. The proposed architecture incorporates processing logic in close proximity to the RRAM and the RRAM-based TCAM, where the unit TCAM cell is comprised of five transistors and two memristors. Analyzed and simulated performance (e.g., latency, energy consumption, and storage density) of the RRAM-based TCAM at various technology nodes are presented and compared to those of prior CAM/TCAM designs.

In this paper, a 2 × 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for design and analysis of n x m passive memory arrays of memristive devices. This data-dependent 2 × 2 model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and no limit on the memory array size. We propose self-adaptable sense resistors that can find their statistical optimum values for reading stored data patterns by composing them with either a replica of a part of resistive random access memory (RRAM) array or a part of RRAM array itself. Self-adaptable resistors can increase the average voltage detection margin by 46%, and reduce the average current consumption by 14% for the case of a 128 × 128 passive array with OFF-to-ON resistance ratio of 103.

A frequency synthesizer with low-power and very short settling time is introduced, which utilizes two-point channel control paths. While the main-path is the same as normal channel controls, a digital-to-analog converter (DAC) with tunable gain is used for the compensation-path to form a feed-forward direct voltage-controlled oscillator (VCO) control path. When the two paths are ideally matched, the two-point control can show zero settling time regardless of the amount of frequency change. However, the settling time performance can be significantly degraded if there exists any mismatch between the two paths. In order to remove the mismatch, a simple compensation method combining a linearized VCO with a resistor-loaded tunable DAC is presented. We show that the overall mismatch can be effectively tuned out by controlling the DAC load resistor, since the mismatch caused by process–voltage–temperature variations is dominated by the resistor variation. We have achieved near-zero settling time for 75thinspaceMHz frequency jumping from 2.4 GHz even with the use of narrow phase-locked loop (PLL) bandwidth of 20 kHz. When the phase noise at 1 MHz offset from 2.4 GHz is − 116.6dBc/ Hz, the total PLL power consumption using 0.18 µm CMOS technology is only 4.2 mW. Copyright © 2011 John Wiley & Sons, Ltd. (A frequency synthesizer with two-point channel control composed of main-and compensation-paths is introduced for fast settling time performance. Any mismatch between the two paths is effectively tuned out by controlling the combined gain of a linearized VCO and a resistor loaded tunable DAC. Even for a narrow 20 kHz PLL bandwidth, the synthesizer achieved near zero settling time at 2.4 GHz, with phase noise of −116.6 dBc/Hz at 1 MHz offset and total power consumption of 4.2 mW.)

This paper demonstrates that memristors can be used to implement programmable analog circuits, leveraging memristor's fine-resolution programmable resistance without causing perturbations due to parasitic components. Fine-resolution programmable resistance is achieved by varying the amount of flux across memristors. The resistance programming can be achieved by controlling the input pulsewidth and its frequency. For demonstration, a memristor is designed for a pulse-programmable midband differential gain amplifier with fine resolution.

This paper introduces compact models for memristors. The models are developed based on the fundamental constitutive relationships between charge and flux of memristors. The modeling process, with a few simple steps, is introduced. For memristors with limited resistance ranges, a simple method to find their constitutive relationships is discussed, and examples of compact models are shown for both current-controlled and voltage-controlled memristors. Our models satisfy all of the memristor properties such as frequency dependent hysteresis behaviors and also unique boundary assurance to simulate memristors whether they behave memristively or resistively. Our models are implementable in circuit simulators, including SPICE, Verilog-A, and Spectre.

A memristor-based architecture for neuromorphic computing is proposed. With memristors mimicking key characteristics of synapses and neurons, such nanoscale neural networks exhibit learning and memory effects with high integration density and scalability. Simulations demonstrate important features including adjustable spike generation, spike-timing and spike-rate dependent plasticity.

This paper investigates a new analog memristor application to nanopore-based DNA sequencing systems, where the memristors' property of dynamic resistance is utilized to effectively amplify the DNA translocation induced block-to-open ratio of the pore resistance to sense. For a demonstrative case with memristors' off-to-on resistance ratio of 100 and nanopore's block-to-open channel resistance ratio of 10, this paper shows that the utilization of a memristor as the feedback resistor of a transimpedance amplifier can boost the sensing window by additional ratio of 10.

A memristors-based Ternary Content Addressable Memory (mTCAM) is presented. A unit mTCAM cell consists of 5T2R, five transistors and two memristors to store the ternary information, having higher storage density than conventional CMOS TCAMs together with the memristors' unique non-volatility. In the write mode, each memristor in the cell is programmed individually such that high impedance is always present between searchlines to reduce the direct current. A two-step write scheme is proposed to reduce the write voltage compliance, and the search voltage used to drive the search content was chosen to optimize the sensing margin. Simulation results for a 2×4 mTCAM array demonstrate the functionality and feasibility of the proposed mTCAM structure, in both write and search modes.

This chapter reviews recent technology, circuits, and systems trends in memristive electronics, with particular attention to ultra-dense and energy-efficient resistive logic gates and signal processing. A reconfigurable nonvolatile computing platform that harnesses memristor properties is devised to deploy massive arrays of nanoscale resistive memory devices and advance their computing capabilities with much lowered energy consumption than the conventional charge-based VLSI systems. With application of memristive devices for stateful logic gates and multipliers, nonvolatile latches with high integration density and CMOS compatibility, combining the memristor technology with the prevailing CMOS technology pose. To prolong the Moore’s Law beyond the hitherto observed technological limitations.

This paper introduces a memristor-based neuronal spike event generator, in which the memristor models the nonlinear behavior of opening and closing of sodium and potassium ion channels. The neuronal action potential describing both the integrate-and-fire spiking events and the refractory period of nerve membrane cells is enabled by utilizing dual time-constants offered by the bistable resistance state of practical memristive devices. A memristor macromodel which is capable of representing both the threshold effects and boundary assurance is also presented.

A unified modeling approach is proposed to cover a broad range of memristive devices. The modular structure of the model enables it to represent behaviors of different types of devices. Resulted from theoretical analyses, the window function is uniquely controlled by the memristive flux. This not only solves the stability problem at boundaries present in previous models, but also reveals that an equivalent charge-flux constitutive relationship can be obtained from various types of memristive devices. Simulations on three device examples show that our model exhibits the device properties such as the frequency-dependent hysteresis, the limited memductance switching range with boundary assurances, the linear/nonlinear dopant drift, and the threshold voltages for read/write mode.

In this paper, we present a method of real-time graphical presentation from empirical data for welding tasks under virtual reality (VR) environments. To express virtual situations with datasets produced from real operations, we expressed virtual objects considering both the welding shape and datasets related to real world. Additionally, we also carried out a comparison study between empirical data and virtually generated data under the same conditions, the predicted results of graphical presentation had more than 90% accuracy.

The safety of electrode-tissue interface under electrical neural stimulation is a critical matter and thus precise control of the electrode voltage needs to be warranted. Analytical study on the electrode potential profile during electrical stimulation justifies the need of using a closed-loop system to regulate the electrode voltage. A neural stimulator with cancellation of excessive charge is proposed. The design procedure and methodology are presented to provide general guidelines for similar system designs. Simulation results demonstrate that neural stimulation safety can be achieved by the proposed design methodology.

New memristors-based neuronal spike event generator is introduced. By using the dynamic properties of conditional resistance switching of a practical bistable memristive device, the neuronal action potential is generated describing both the integrate-and-fire spiking events and the long enough refractory period of nerve membrane cells. The memristor offers the dual time-constants which model the unbalanced charging and discharging periods of the spike signals. With a Pt/TiO 2 /Pt memristive device having the R OFF /R ON resistance ratio of 3000, the memristor-based spike generator offers spike trains with about 0.03% duty.

New memristors-based resistive logic computation units are introduced. By controlling the memristors' conditional set operation adaptively to one of the input polarities, bipolar signal multiplication of an input and a stored reference bit is performed by unipolar memristor devices and control switches. The multiplication result is registered in an output nonvolatile memristor so that the computed output can be accessed anytime later on by reading the output memristor's state. The memristive multiplier circuits demonstrate a fast correlation computing for highly complex inputs.

This chapter reviews recent technology trends in memristive analog and digital electronics, with particular attention to programmable analog and digital circuits, ultra-dense nonvolatile resistive memory architectures, and zero leakage nonvolatile logic gates. A reconfigurable nonvolatile computing platform that harnesses memristor properties is used to deploy massive local nonvolatile memories and advance computing capabilities with much lowered energy consumption than the conventional charge-based VLSI systems. With application of memristive devices for nonvolatile memories, programmable interconnects, stateful logic gates, and nonvolatile latches with high integration density and CMOS compatibility, combining memristor technology with the prevailing CMOS technology poses to prolong the Moore’s Law beyond the hitherto observed technological limitations.

This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for the sense resistance. The complementarily written memory array exhibits data-pattern independent voltage detection performance as well as regulated much smaller current consumption compared to the conventional non-complementary passive resistive memories.

This paper demonstrates that memristors can be used to form a fine resolution programmable resistance without perturbations by parasitic components. By exploiting the memristor characteristics, fine resolution programmable memristance is achieved by varying the amount of charges flowing or flux across the memristor. Under the same circuit configuration with same or even less amount of parasitics, memristance is reconfigured with fine resolution by controlling the input pulse width and its frequency. This paper shows an example of pulse programmed memristors and their analog circuit applications.

A memristor-based ternary content addressable memory (mTCAM) is presented. Each mTCAM cell, consisting of five transistors and two memristors to store and search for ternary data, is capable of remarkable nonvolatility and higher storage density than conventional CMOS-based TCAMs. Each memristor in the cell can be programmed individually such that high impedance is always present between searchlines to reduce static energy consumption. A unique two-step write scheme offers reliable and energy-efficient write operations. The search voltage is designed to ensure optimum sensing margins with the presence of variations in memristor devices. Simulations of the proposed mTCAM demonstrate functionalities in write and search modes, as well as a search delay of 2 ns and a search of 0.99 fJ/bit/search for a word width of 128 bits.

An integrated circuit structure for a dual-band transcutaneous bio-implant system that can remove the problematic power interference coupled into the weak data telemetry signal is presented. The unwanted effect of coupled power interference is efficiently suppressed through a feedback cancellation that directly annihilates the interference with an optimally tuned fraction of the received power signal by the implanted power receiver.