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We propose a wideband lumped element directional coupler using lossy negative capacitance (NCAP). NCAP provides a broadband resonance effect combined with passive inductors and capacitors in a circuit, enabling the coupler to exhibit wideband directivity performance. In addition, a 3-dB loss in the NCAP enhanced the bandwidth at the expense of the transmission gain, which decreased by only 0.3 dB. The proposed coupler was implemented in the IBM 7RF 180-nm CMOS technology. The size of the core chip is $1180\,\,\mu \text {m} \times 570\,\,\mu \text{m}$ . The designed NCAP provides a capacitance of −13 pF using a supply voltage of 2.7 V and a current of 9.6 mA. The coupling was designed to be −10 dB at the center frequency of 1 GHz. The bandwidth was defined by the frequency range, which exhibited a directivity of more than 30 dB. The S-parameter measurements showed an absolute bandwidth ranging from 0.86 to 1.12 GHz, and a fractional bandwidth of 26%. In the bandwidth, the coupling had a 0.5-dB variation, the transmission loss was smaller than 2.14 dB, and the noise figures were 1.8–2.5 dB.

Herein, we present a floating 2-port nonreciprocal negative capacitance (NCAP) circuit that employs a unilateral gain boosting technique by including an asymmetric cross-coupled differential cascode transistor pair. The proposed circuit provides an asymmetric gain characteristic. The forward gain ( $S_{21}$ ) is increased at the cost of the backward gain ( $S_{12}$ ). The technique not only provides a boosted forward gain but also stable operation resulting from this reduced backward gain. We further investigate the stability of the NCAP circuit in terms of the output resistances of the current sources in the circuit. The proposed NCAP circuit was implemented in IBM 7RF 180-nm CMOS technology and was designed to have a supply voltage of 3 V and a current of 10 mA. The S-parameter measurements showed a self-resonance frequency of 2.25 GHz. The maximum $S_{21}$ was −0.2 dB at 1 GHz. In the frequency range from 0.5 to 1.5 GHz, the capacitance was approximately −4 pF, and the difference between $S_{21}$ and $S_{12}$ was 8.7–9.6 dB. The size of the core chip was $150 \times 190~\mu \text{m}^{2}$ .

This paper presents a power amplifier module (PAM) that operates efficiently in low-power mode for IEEE 802.11g Wi-Fi applications. The PAM consists of a power amplifier (PA), a buck converter, and a power detector. Two packaging technologies were used to integrate the compact module: a low-temperature co-fired ceramic (LTCC) technology and a ferrite-filled printed circuit board (PCB) technology. The LTCC portion includes radio-frequency inductors, capacitors, transmission lines, and interconnection lines to minimize the overall size, while a power inductor for the buck converter is implemented in ferrite-filled PCB. The PA and the buck converter are designed in 2- $\mu \text{m}$ InGaP/GaAs heterojunction bipolar transistor technology and 0.35- $\mu \text{m}$ CMOS technology, respectively. The output power level is converted into a voltage by the power detector, and the voltage controls the buck converter, thereby optimizing the supply voltage of the PA. This adaptive supply voltage helps to improve the power-added efficiency (PAE) in the low-power regime while maintaining linearity. The PAM showed an error vector magnitude of less than 4% up to an output power of 22 dBm. The PAE is 8% and 11% at output powers of 11 and 16 dBm, respectively, representing respective improvements of 60% and 43%. The overall size of the PAM is $5 \times 7.5 \times 1.2$ mm $^{\mathrm {\mathbf {3}}}$ .

This letter presents a power amplifier (PA) with an on-chip power detector for 2.4-GHz wireless local area network application. The power detector consists of a clamp circuit, a diode detector, and a coupled line directional coupler. A series inductor for an output matching network in the PA is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from two metamaterial units along the coupled line.

This paper presents error vector magnitude (EVM) behavior under two different modes of a reference voltage (Vref); one is a static EVM with a constant Vref and the other is a dynamic EVM with a pulsed Vref. A 2.4-GHz two-stage power amplifier (PA) is implemented by GaAs HBT technology to investigate EVM behavior for IEEE 802.11 g wireless local area network application. A square wave pulse with the duty cycle of 50% is applied as Vref for dynamic operation mode. In this paper, it is shown that a dynamic EVM is worse than a static EVM because a transient response of PA output distorts preamble and signal in orthogonal frequency division multiplexing signal bursts. This transient response is explained by a two-pole thermal network in this study, and transient response experiments with a resistor-capacitor (R-C) network at a power supply were performed for verification

This paper presents a power amplifier with an on-chip power detector for 2.4 GHz wireless local area network (WLAN) application. The power detector consists of a clamp circuit, a diode detector and a coupled line directional coupler. A series inductor for an output matching network in the power amplifier is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from 2 metamaterial units along the coupled line.

An ultra-wideband power divider with out-of-band filtering and DC blocking functions is presented. The divider consists of three parallel-coupled lines, a short-circuited shunt stub and a resistor. The divider was implemented in a two-layer printed circuit board with a high dielectric constant. The measurements show a minimum insertion loss of −0.4 dB in the middle band and a rejection of −17 to −18 dBc at 1.5 and 11.5 GHz, respectively.

A CMOS voltage controlled oscillator(VCO) with additional parallel resistors in its LC resonator has been proposed to improve the tuning (frequency-to-voltage) linearity and reduce the tuning sensitivity KVCO. The VCO is linearly tunable from 806 to 1,113 MHz with a 34% tuning range controlled linearly by the tuning voltage. The phase noise of the VCO is −100.4 dBc/Hz at 100-kHz offset frequency from 903MHz carrier. The supply voltage was 1.8V with the current of 2.5 mA flowing through the differential core. The chip size is 0.815 × 0.680 mm2, which has been fabricated in a standard 180-nm CMOS technology.

Presented is the linearity improvement technique of a power amplifier (PA) using a digitally-controlled tunable output matching network implemented in GaAs BiFET technology. The load impedance of the heterojunction bipolar transistor (HBT) power device in the last stage of the PA is adjustable in terms of output power levels by a metal-insulator-metal (MIM) capacitor array with pHEMT switches in the output matching network. A 2.4 GHz two-stage PA for IEEE 802.11g, Wireless Local Area Network (WLAN) application, is implemented to demonstrate the technique. Not only is the maximum linear output power of the PA increased by 2.5 dB, but the linearity is also improved by 4 dB at the output power of 15 dBm for the error vector magnitude specification of −28 dB.

Presented is a systematic approach for the layout optimisation of a Si-based power device by a distributed large model considering all the layout parasitic components resulting from the interconnections. The optimisation in terms of gain, PldB and PAE is shown with the SiGe power devices. Using the optimised power devices, a preliminary two-stage power amplifier was implemented for PCS application.