Search

A novel low voltage tunable linear transconductor is presented. The approach is based on quasi-floating gate transistors achieving higher transconductance and better dc common mode rejection than previous implementations. A dynamic biasing technique improves the sensibility of the linearity to process variations. Measurement results of the circuit, designed in a 0.5 μm CMOS process from 1.4 V power supply, confirm the advantages of the proposed approach with a very high speed operation of 50 MHz of gain-bandwidth product, a IM3 of ?40 dB and a nominal power consumption of only 490 μW.

A high speed, low power and programmable readout front-end system is presented for silicon detectors to be used in nuclear physics applications. The architecture consists of a folded cascode charge sensitive amplifier, a pole-zero cancellation circuit to eliminate undershoots and a shaper circuit with Gm-C topology. All building blocks include a regulated cascode technique based gain enhancement. Experimental results show that the whole front-end system can be programmed for peaking times of 100 ns, 200 ns and 400 ns maintaining the amplitude of the output voltage. Programmability is achieved by switching different resistors for all poles and zeros. The system has been designed in a 130 nm CMOS technology and powered from a 1.2 V supply. The output pulse has peak amplitude of 200 mV for an input energy of 5 MeV from the detector. A power consumption low noise tradeoff will be considered.

This paper presents a design of a single readout front-end channel for energy spectroscopy. The front-end electronic system comprises a charge sensitive amplifier and a pulse shaping amplifier. Novel techniques based on regulated cascode circuits to increase the gain are proposed. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. The analog system has been designed in a 90 nm technology and optimized to match a detector capacitance of 5 pF. Simulation results confirm the advantages of the proposed approaches in terms of gain, speed, linearity and power consumption.

A technique is presented to evaluate mean values and standard deviations of transient analog cell specifications under random fluctuations of the primitive component parameters. Its precision and generality are similar to those of Monte Carlo analysis of electrical simulations while its CPU time is considerably smaller. The advantages of the proposed technique are demonstrated via the statistical evaluation of two CMOS cells.