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Designing power supplies, especially for power adapters, requires that the designer possess a particular level of expertise and insight into implementing the best architecture. This level of expertise is especially relevant when using a power architecture known as Active Clamp Flyback (ACF). This article will demonstrate, to designers, a practical design method to obtain a reliable, robust, efficient, and high power density, ACF architecture with the bonus of fast time-to-market. Designers can eliminate that conventional Resistor Capacitor Diode (RCD) snubber circuit in their flyback converter design and learn the more efficient ways of active clamp operation. The ultimate solution is an all-Silicon design in a single package which also includes continuous advanced adaptive cycle-by-cycle digital control circuit for im proved performance over varying line/load/temperature as well as component tolerances. The outcome of the proposed design is high efficiency and power density, low EMI, and stringent line/load regulation.

Isolated high-output-current DC/DC converters are critical technologies for future datacenter power architecture. LLC converters with matrix transformers are suitable for these applications due to their high efficiency and high power density. Previously, The Center for Power Electronics Systems (CPES) proposed a PCB-winding based matrix transformer for a 400V/12V 1MHz unregulated LLC converter. This paper aims to further improve the efficiency of the converter, without compromising on the power density, by optimizing the switching frequency of the converter, and mitigating the current sharing issues associated with center-tap rectifiers and shielding in matrix transformers with multiple outputs. The elimination of these issues is critical because they can lead to non-uniform increases in device temperatures and a reduction in the overall efficiency of the converter. The proposed improvements are verified by developing a 1 kW prototype with a peak efficiency of 98.05% and a power density of 940 W/in3

Power consumption of data centers has increased rapidly over recent years. Of late, 48 V power architecture has attracted more interest in data centers as it offers more efficient architecture. This paper focuses on the implementation of the DC-DC stage of the power supply unit for narrow range 48 V datacenter bus architecture. The paper presents a nearly 99% efficient 400 V-48 V LLC with a very high power density and low profile fully integrated on PCB. The LLC topology is chosen as it can achieve soft-switching, allowing one to push the switching frequency and increase the power density. A matrix of four transformers is used to reduce the termination loss of the secondary synchronous rectifier and achieve better thermal management. The number of secondary turns is optimized to achieve the best trade-off between winding loss, core loss, and power density. A matrix of four resonant inductors is also designed to reduce the proximity effect between inductor windings and reduce inductor PCB winding loss. The converter integrates a matrix of four transformers and resonant inductors on a 6-layer PCB and single-core for easier manufacturability and lower cost. A prototype is tested for the proposed converter at 250 kHz with 98.8% efficiency and 600 W/in3 power density with an 11 mm profile.

Universal serial bus power delivery (USB-PD) chargers are more attractive to consumers with multiple output ports. Existing multiple port charger designs take multi-stage approach thus increase power loss and charger size. Also, ports are normally designed with different power capability thus the high-power port becomes under-used if the connected device is fully charged while the other lower power ports cannot take over the unused power. This is mainly limited by the power architecture design. This paper addresses this issue by presenting a multiplexing based multi-port quasi-resonant flyback converter. The design achieves true power-sharing with high efficiency, small size, and simple analog implementation. This paper discusses the operating principle and design considerations. A GaN-based 60 W dual port charger verifies the proposed scheme while achieving 76% size reduction and 1% efficiency improvement than state-of-the-art.

In recent years, the use of distributed power sources, such as photovoltaic power generators and fuel cells, has become widespread. In particular, next-generation power distribution systems for residences based on direct current (DC) power supply and distribution are being actively researched in Japan. In this context, this paper investigates the effects of operating home appliances with a DC power supply using a special winding transformer on each device were investigated. To this end, a smart house equipped with DC power supplied by a transformer with a special winding structure was configured. Experimental observations confirmed that all digital home appliances exhibited proper functions on the aforementioned DC power architecture.

Power consumption of data centers is increasing rapidly over recent years. Recently, 48V power architecture has attracted more interest in data centers as it offers more efficient architecture. This paper focuses on the implementation of the DC-DC stage of the 3 kW power supply unit. Full-bridge regulated LLC converter is designed with a matrix of two transformers. This paper focuses on the magnetic design of the PCB-based transformer and resonant inductor of the LLC converter. The dimensional effects on core loss are discussed and evaluated. A matrix of two transformers implemented on UI core with rectangular core shape is proposed to minimize the eddy core loss of the transformer core. The termination of the secondary Full-bridge rectifier is also optimized to reduce the conduction loss of the transformer. A low-profile prototype of the designed converter is demonstrated with a peak efficiency of 98% and power density of 700W/in3.

Medium-voltage DC (MVDC) distribution system is considered as the promising power architecture of future shipboard power system. Fault-tolerance ability is of great importance for power system on ships. In this paper, zonal DC-DC conversion system based on modular multilevel converter (MMC) and three-phase bridge rectifier are proposed with its hierarchical fault-tolerant scheme. The topology configurations of the front-end MMC with multi-winding medium frequency transformer (MFT) under normal and post-fault circumstances are presented. The recon-figuration scheme and fault-tolerant control strategy are also proposed to ride-through sub-module (SM) level fault, phase level fault and bus level fault. Based on the hierarchical fault-tolerant scheme, redundant configuration of the MMC sub-module is further analyzed with the hierarchical reliability modelling. The effectiveness of the proposed control strategy is verified by the experimental results.

Light-emitting diode (LED) technology has become one of the most important luminaire, due to its environmentally-friendly behavior, high efficiency, quality of light and large lifespan. Different LED drivers based on power converters have been presented. However, most of these solutions are focused principally on low-power lighting systems, above 100 W. This paper presents a novel modular solution for 1200 W LED driver with very high efficiency. The proposed power architecture is based on a cascade connection of a DC transformer (DCX) and a partial power converter (PPC). A comprehensive comparison between different PPC configuration is presented and supported by simulations to validate the theoretical results.

Supercapacitor (SC) assisted low dropout regulator (SCALDO) is a very low-frequency DC-DC converter technique, with high end-to-end efficiency, where the load receives a high slew rate capable low noise output of a linear regulator. This technique can be easily extended with a transformer isolated input stage to achieve the 48-V DC rack power architecture proposed by Google recently. One specific advantage of this new design approach is the two-stage DC-UPS capability by over-sizing the SC bank. In this new SCALDO-derived technique with transformer isolation, by inserting an SC in the input side of the converter, energy transfer towards the load side occurs at a higher frequency, in a combination of forward and flyback modes to reduce the overall volume of the converter. The paper details the magnetics design aspects of the technique providing experimental results of a proof of concept prototype.

The high-efficiency, high-current and low-cost power solutions are required for data centers application, in order to reduce the transmission loss on cables, the high input-voltage dc distribution power architecture has been adopted, the 380-12 V high output current isolated converter is widely used in this application. This paper presents a 300-kHz 1-kW LLC resonant converter using novel integrated transformer and Gallium nitride device that are designed and optimized for the LLC resonant converter. The novel integrated transformer structure is proposed and designed for reducing core-loss, secondary conduction-loss and achieving no gap-loss. In the end, a laboratory prototype is designed and tested. The experimental results have verified the performance of the proposed LLC resonant converter with novel integrated transformer.

Sever power supplies and board level voltage regulators are currently the bottleneck limiting efficiency of overall server power architecture efficiency. In order to address this Google has proposed and implemented a 48 volt server architecture that brings a higher voltage level throughout the server rack to reduce distribution losses, and conversion losses upstream of the server power supply. However this change places additional burden on the board-level regulators that must now regulate from 48 volts down to below 1 volt for some components. The most common approach is a two stage approach called the "Intermediate Bus Architecture". A novel topology for an Intermediate Bus Architecture was proposed at APEC 2018. This topology featured extremely high efficiency, very simple control and low component count. However two other critical metrics for a bus converter are scability and power density. The work proposed in this paper demonstrates that the Zero-Inductor Voltage (ZIV) Converter can be easily scaled to multiple phases, and shows a very high density design while maintaining efficiency above other cutting edge solutions. The two-phase prototype achieves up to 800W/in3 power density, 99.2% peak efficiency, and 97.9% full load efficiency for 840W output while maintaining good current sharing across all load conditions. The two-phase prototype requires no additional control, and is highly scalable to different power levels through paralleling.

With its simplicity and the lowest component count incorporating both energy storage and isolation, the flyback converter is an ideal candidate for power levels up to several hundred watts. One inherent drawback of the topology, however, is its poor cross regulation when used in multiple-output applications [1]. Much effort, therefore, has gone into techniques for improving cross regulation [2]. A novel multiplexed approach to the power architecture, where energy packets are steered by a controller to where they are needed, eliminates this drawback and achieves cross regulation within a fraction of 1% while significantly improving system efficiency when compared to conventional post regulation techniques. The new architecture supports multiple outputs driving both constant current and constant voltage loads, enabling the design of a single switch-mode power conversion stage that powers logic circuitry, USB ports, audio channels, and LED strings simultaneously. Examples of working designs along with respective operating characteristics are presented.

Multi-antenna phased array radar is widely used in airborne detection, and the weight of its power system is affected by the number of antenna and power architecture. Based on the morphological differences of secondary power supply, the power architecture is divided into independent unit architecture, independent module architecture and distributed architecture. By analyze the weight composition and characteristics of power system in multi-antenna radar, the applicable scenarios of various architectures are obtained, and the influencing mechanism of antenna number on power weight is demonstrated. Finally, based on typical airborne fire control radar, the specific weight composition of power system of various architectures in single-antenna radar and three-antenna radar is compared, and the specific effect of antenna number on power weight is obtained.

Energy efficiency of power converters used in computer server farms is a major issue today since these facilities consume huge amounts of energy on a continuous basis. In 2016, Google introduced a 48 V rack power architecture at the Open Computing Project (OCP) summit to replace 12 V, and announced their plans to shift towards 48 V DC rails with DC-UPS. This was with the main target of reducing ohmic losses in the DC-distribution by 16 times and transformer losses by 30%. Compared to well-developed switching converter techniques, a new linear high efficiency RFI/EMI free DC-DC converter technique, namely SCALDO, has the potential to be used for these 48 V DC server power supplies. This paper presents analytical and simulation details of an electrically isolated, 48 V DC, 20 A extended-SCALDO based design. Experimental validation of this technique has been established by developing a proof of concept prototype, a scaled down 30-to-6-V DC converter. The paper highlights the advantages of combining the fly-back and forward modes similar to a switching converter, for charging a supercapacitor bank which acts as energy reservoir, where the final 48 V DC rail is regulated by a simple SCALDO converter extended to supply 20 A, and achieving DC UPS capability by over-sizing the supercapacitor.

With the power architecture transition from a 12 to 48 V rack in modern data centers, there is an increased interest in improving 48 V power conversion efficiency and power density. In this paper, we will analyze system optimization for a 48–12 V non-isolated, fully regulated, intermediate bus converter (IBC) to maximize efficiency and power density. This includes detailed analyses on the impact of power semiconductor device, gate driver as well as an exhaustive treatise on the choice of the optimal inductor. The final experimental prototype, a fully regulated, digitally controlled, 720 W, five phase, GaN transistor-based 48–12 V buck IBC demonstrates exceptional efficiency and power density, respectively, exceeding 95% and 1000 W/in3.

In the emerging field of wearable systems for remote monitoring of physiological parameters, the measurement of bioimpedance has the potential to provide many useful information. On the other hand, in this scenario, an optimization of power consumption of the circuit is crucial. A low power architecture for the measurement of bioimpedance was identified in this work. It reduces the consumption in the most critical blocks of the system: the current driver, the signal sensing and the demodulator. The device was prototyped and electrically characterized. The compromise between power consumption reduction and the increase in electrical noise was analysed and an effective signal processing technique was developed, showing that it is possible to achieve a signal to noise ratio good enough to enable applications like respiration monitoring (breathing rate and amplitude) or cardiac output estimation. Preliminary tests on healthy subjects showed a good correlation with spirometer, for breathing monitoring, and with Doppler echocardiography, for cardiac output. Thanks to the good functionality and the reduced current consumption (750 μA at 2.8 V power supply was obtained with a discrete-components implementation) the module resulted suitable for the integration in wearable devices for remote monitoring of physiological parameters, or other low power applications.

To reduce the cost and footprint of a Magnetic Resonant Imaging (MRI) scanner setup in a hospital, a modification in the existing power architecture of the MRI system has been proposed. A high frequency alternative for the frontend bulky low frequency transformer has been proposed. The implementation challenges and workaround solutions for the High Frequency Power Distribution Unit (HFPDU) has been explored and the experimental setup and results are discussed in the paper.

This contribution presents the analysis, design and characterization of a high gain Doherty power amplifier implementing an integrated Driver stage in the Auxiliary branch. Guidelines and design equations are demonstrated, fulfilling the full integration of the whole new architecture. The development of a microwave monolithic integrated circuit prototype based on TriQuint GaN technology for 7 GHz applications is reported. 10.5 dB of Gain, 38.1 dBm of saturated output power and 42% of efficiency at 7 dB of output back-off have been demonstrated by experimental results. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:498-507, 2014.

This paper presents the design and development of a high performance and low power MIPS microprocessor and implementation on FPGA. In this method we for achieving high performance and low power in the operation of the proposed microprocessor use different methods including, unfolding transformation (parallel processing), C-slow retiming technique, and double edge registers are used to get even reduce power consumption. Also others blocks designed based on high speed digital circu its. Because of feedback loop in the proposed architecture C-slo w retiming can enhance designs that contain feedback loops. The C-slow retiming is well-known for optimization and high performance technique, it automatically rebalances the registers in the proposed design. The proposed high performance microprocessor is modeled and verified using FPGA and simulation results. The proposed methods in microprocessor have been successfully synthesized and imp lemented in Quartus II 9.1 and Strat ix II FPGA, to target device EP2S15F484C3, and power is analyzed with Xpower analyzer. Results demonstrate that the proposed method has high performance.

In this paper, we designed and fabricated a high performance, low power image processing unit for payload camera subsystem for a nano satellite. The nano satellite has very limited power source produced from solar panels as the dimension of this panel is 10×10 cm. The camera system is the most subsystem in the satellite, which consumes high power during the image processing stage. We presented, a low power architecture for the matrix — vector multiplier of a constant matrix by a vector, which transforms the main part of the Discrete Cosine (DCT) in the compression circuit of an image unit. The image processing unit has been designed using FPGA technology, lower power is achieved on the architectural level. We have fabricated the PCB using FPGA (SPARTAN 3E 200), with SD Card for image storage and EEPROM for FPGA programming. This PCB is 4 layers and is designed with miniature dimensions to be more reliable and can be easily installed in the nano satellite inside camera module.

Narrow Vdc (NVDC) power architecture is one of initiatives to extend battery life in mobile computing system. Advantages and application limit of it are analyzed for two generations NVDC architectures in detail. All design considerations for such possible concerns as charger controller selection, precharge issue, thermal stress, and energy star compliance related are presented, and solutions to some concerns are also provided in this paper. Finally, tests are conducted in a typical notebook system to verify all theoretical analysis and proposed solutions to those concerns.

The Intermediate Bus Converter (IBC) is a middle stage converter in the distribution power architecture, characterized with high efficiency, high frequency and high power density, to realize the DC voltage transform and isolated function. In this paper, the unregulated LLC DC transformer's (LLC-DCT) inherent problem which leads to a large conduction loss in IBC application has been discussed. A new intuitive topology with third order harmonic current injection has been proposed to reduce the RMS of the resonant and secondary current. At the end, the theoretical analysis and the proposed optimal topology design are verified by an 800W, 100kHz, 400V/12.5V LLC-DCT prototype.

There is a clear trend in personal computing toward multimedia-rich applications. These applications will incorporate a wide variety of multimedia technologies, including audio and video compression, 2D image processing, 3D graphics, speech and handwriting recognition, media mining, and narrow/broadband signal processing for communication. In response to this demand, major microprocessor vendors have announced architectural extensions to their general-purpose processors in an effort to improve their multimedia performance. Intel extended IA-32 with MMX and SSE (alias KNI), Sun enhanced Sparc with VIS, Hewlett-Packard added MAX to its PA-RISC architecture, Silicon Graphics extended the MIPS architecture with MDMX, and Digital (now Compaq) added MVI to Alpha. This article describes the most recent, and what we believe to be the most comprehensive, addition to this list: PowerPC's AltiVec, AltiVec speeds not only media processing but also nearly any application in which data parallelism exists, as demonstrated by a cycle-accurate simulation of Motorola's MPC 7400, the heart of Apple G4 systems.

A high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture, 4PPM (4-Pulse Position Modulation) infrared signals detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a 1-bit digital demodulator. To extend the range of the link length, a 4PPM demodulator is synthesized to implement a demodulation algorithm which is constructed so as to accommodate the output tolerance of the infrared receiver. A part of the experimental results shows that the proposed 4 Mbps infrared communication system can achieve an error free link in the range of 0–140 cm at power consumption of 245 mW and 65 mW for transmitting and receiving, respectively. The communication controller is integrated in a 0.6 μm CMOS standard-cell chip which contains 10,015 transistors on a 12 mm2 die.

Seamless integration of distributed/renewable energy into a smart MicroGrid architecture is a hot topic of research for both public and defense applications. It is the DoD's intention to develop a more cost efficient and reliable power architecture on the battlefield. A smart MicroGrid seamlessly integrates an array of locally installed, distributed power sources and couples them using advanced control schemes to improve the reliability at the sources' point of common coupling. These islanded grids must be capable of powering a wide range of conventional and advanced loads including climate control systems, lights, communication systems, and high pulsed power systems such as radars, high power microwave (HPM) weapons, or electromagnetic launchers among others. The latter types of loads draw rapid high power bursts of energy from the grid and are typically powered using their own dedicated power supplies. The impact this type of loading has on the central DC or AC bus of a MicroGrid must be studied and it was the intent of this research to better understand how operation of these advanced loads impacts the quality of the voltage on the main bus of a MicroGrid.

The IBM PowerPC 603e floating-point unit (FPU) is an on-chip functional unit to support IEEE 754 standard single- and double-precision binary floating-point arithmetic operations. The design objectives are to be a low-cost, low-power, high-performance engine in a single-chip superscalar microprocessor. Using less than 15 mm 2 of the available silicon area on the chip (the size of the PowerPC 603e microprocessor is 98 mm 2 ) and operating at the peak clock frequency of 100 MHz, an average single-pumping multiply-add-fuse instruction has one-cycle throughput and four-cycle latency. An average double-pumping multiply-add-fuse instruction has two-cycle throughput and five-cycle latency. The estimated performance at 100 MHz is 105 against the SPECfp92 benchmark.

hcc is a portable optimizing compiler for ANSI C [8] [9] with code generators for the PowerPC and the MIMOS's RISC CPU. The PowerPC is a RISC processor developed jointly by IBM, Motorola, and Apple Computer among others in 1993, while the MIMOS's RISC CPU is an experimental 32-bit RISC processor. At the moment the compiler can be used to program PowerPC based computers including the PowerMacintoshes and the IBM RS6000 PowerPC based workstations.

The PowerPC AS™ A10 64-bit RISC microprocessor is a 4.7-million-transistor integrated circuit design, using IBM CMOS 5L 0.5-µm, 3-V, four-level-metal ASIC technology. Support for the PowerPC AS architecture is implemented in a 213-mm 2 die using a semicustom design methodology. Chip density and speed are enhanced through the use of custom macros and multiport arrays. An on-chip phase-locked-loop circuit is used to reduce chip-to-chip clock skew. Full utilization of the four-level-metal interconnect technology was achieved through architectural floorplanning, performance clustering, and timing-driven placement and wiring, with a total wire length of over 102 meters placed on the 14.6 × 14.6-mm die. The microprocessor is a pipelined, superscalar design with five separate functional units, a 4KB instruction cache, and an 8KB data cache. The design includes parity, error-correction, and error-logging functions, as well as self-test for logic and arrays during power-on. The design is robust and implements a wide range of performance configurations at the system level, allowing direct attachment of DRAM to the processor, or high-performance L2 cache options using high-speed SRAM. An on-chip system I/O bus and bus controller are provided for attachment of peripherals.

In this paper a novel control strategy is proposed for a three-phase-four-leg UPS-inverter for data center application. The control strategy takes care of the unbalanced three-phase loading of the data center server without the manifestation of the neutral current. Thus, the power distribution unit (PDU) transformer can be eliminated from the power architecture while feeding the total data center load from a standard three-phase-three-wire utility supply. The proposed control strategy adjusts the inverter output voltages in such a way that even in the presence of unbalanced loading of the servers, the neutral current is maintained at zero in the steady-state. The proposed methodology is thus capable of reducing the thermal losses due to PDU as well as neutral wire improving the power usage efficiency (PUE) of the date center.

As design cycle times in the computer industry decrease, it becomes increasingly important to have a fast, effective software-development environment quickly available so that software may be developed for emergent microprocessors well before general availability. This paper discusses how gdb (an industry-standard source-level debugger) was paired with a software microprocessor simulator for the Motorola PowerPC 601* and PowerPC 603* microprocessors in order to provide a seamless and highly productive compile-edit-debug environment from the time that the PowerPC instruction set was first announced through general availability.

Real-time monitoring technology about wire windy swing is one of key technologies in smart grid, which is well-known as an advanced power architecture. The technology is proposed in this paper by incorporating Micro Doppler Algorithm, which is a hotspot in signal processing. According to others, this monitoring technology has the special characteristics such as all-day, all-weather, compact, and reliable. The relationship between the wire windy swing parameters and micro-Doppler is derived after the model of wire windy swing formed. The simulated results is shown to illustrate the validity of the proposed algorithm.

The PowerPC 601 microprocessor, the first of a family of processors based on the PowerPC architecture, is described. The general-purpose processor contains a 32-Kb cache and a superscalar machine organization that allows dispatch and execution of up to three instructions each clock cycle. The bus interface and storage control mechanisms can be configured for a wide range of system designs, from low-cost desktop personal computers to high-performance multi-processor systems. The PowerPC architecture, machine organization, chip packaging technology, and performance are discussed. >

The ability to discriminate between falls and activities of daily living (ADL) has been investigated by using tri-axial accelerometer sensors, mounted on the trunk and using simulated falls performed by young healthy subjects under supervised conditions and ADL performed by elderly subjects. In this paper we propose a power-aware real-time fall detection integrated circuit (IC) that can distinguish Falls from ADL by processing the accelerations measured during 240 falls and 240 ADL. In the proposed fixed point custom DSP architecture, a threshold algorithm was implemented to analyze the effectiveness of Programmable Truncated Multiplication regarding power reduction while maintaining a high output accuracy. The presented system runs a real time implementation of the algorithm on a low power architecture that allows up to 23% power savings through its digital blocks when compared to a standard implementation, without any accuracy loss.

Power Generators are presently being used to power large (>1MW) radars whose pulsed-load profile can influence the Generator's performance and vice versa. This paper explores the limitations of the Generator in providing power to a pulsed-load, and how the power architecture may be modified to improve the coupling between source and load with the objective of maximizing performance. Simulated examples of a generic radar power system will be demonstrated showing progressive improvement as better coupling is attained, detailing generator limitation thresholds and overall system performance.

We present a methodology for the design and analysis of power grids in the PowerPC TM microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology to the PowerPC TM 750 microprocessor is presented.

The 801 minicomputer 1 project at IBM Research in Yorktown Heights, NY, USA, in 1975 pioneered many of architectural concepts used in RISC including IBM's RT System. The paper describes a second-generation RISC architecture, the POWER architecture, which is based on subsequent research by the original 801 team and is used in the recently announced RISC System/6000. The architecture was designed to support superscalar implementations which can execute multiple instructions every cycle. It provides compound-function instructions which allow application path lengths to be less than would be required on many complex instruction set computers. The architecture also exploits advances in optimizing compiler and operating system technology. An extension to the original 801 virtual memory architecture for hardware support of database storage is also described.

This paper proposes system two-stage power architecture for laptop voltage regulators (VRs). By taking advantage of the Thermal Design Power (TDP) requirement in the laptop, VRs for microprocessor, graphics, DDR memory and main power can share the same first stage with very low design power. The high-efficiency and high-frequency first stage based on switching capacitor technology and second stage design is presented in this paper respectively. Two different designs are illustrated and verified by experiments. One design keeps the similar VR cost as the current single-stage solution and improves VR light load efficiency by 5%. Another design has slightly higher VR efficiency comparing with single-stage solution while reducing the footprint of VR output inductors and capacitors by 25%∼33% and VR total cost by 5%.

The latest high-performance IBM PowerPC microprocessor, the POWERS chip, poses challenges for performance model validation. The current state-of-the-art is to use simple hand-coded bandwidth and latency testcases, but these are not comprehensive for processors as complex as the POWER5 chip. Applications and benchmark suites such as SPEC CPU are difficult to set up or take too long to execute on functional models or even on detailed performance models. We present an automatic testcase synthesis methodology to address these concerns. By basing testcase synthesis on the workload characteristics of an application, source code is created that largely represents the performance of the application, but which executes in a fraction of the runtime. We synthesize representative PowerPC versions of the SPEC2000, STREAM, TPC-C and Java benchmarks, compile and execute them, and obtain an average IPC within 2.4% of the average IPC of the original benchmarks and with many similar average workload characteristics. The synthetic testcases often execute two orders of magnitude faster than the original applications, typically in less than 300K instructions, making performance model validation for today's complex processors feasible.

The RAD750trade space hardened microprocessor is a fully licensed PowerPCtrade that is identical in architecture, function and operation to the commercial PowerPC 750trade microprocessor. Ongoing performance improvements in both the processor and surrounding devices provide a complete space computer solution for current and future space programs

A PowerPC system-on-a-chip processor which integrates high speed state of the art 800 MHz PowerPC, DDRII-667 memory controller, RAID assist logic, and three PCI-X DDR266 interfaces with a rich mix of conventional peripherals is described. The PowerPC, with on-chip L2 cache enabled, executes up to 1600 DMIPS. The RAID assist logic is capable of transferring 2 Gbytes/sec. The state of the art PowerPC, the high bandwidth data pipes, and the RAID assist logic make the SOC an ideal solution for RAID controller applications. Active power consumption is as low as 6W with a 1.5 volt supply. The SOC has been implemented in a 0.13 /spl mu/m, 1.5 V nominal-supply, bulk CMOS process.

International audience; Energy consumption is a hot topic in the design of embedded systems. As mobile computing system (video camera, cellular phone, etc.) becomes more popular, how to lengthen the battery life of these systems becomes a critical issue. Also embedded system design is one of the most challenging tasks because the increasing complexity of new and various applications and the great variety of constraints to meet (lower cost, higher performance, lower energy). In this paper, we focus on the constraint of low energy consumption in hardware/software codesign tool. Our goal is to reach the best trade-off between system performance and energy consumption. For hardware and software units (DSP, RISC processors), we have developed a model of energy consumption and the methodology to evaluate the energy consumption of the designed systems. Then to reduce this energy, we introduce optimizations in allocation and scheduling steps. Experimental results show that this approach is promising and that it provides architectures with an energy saving of 50%.

The AltiVec/sup TM/ technology is an extension to the PowerPC architecture/sup TM/ which provides new computational and storage operations for handling vectors of various data lengths and data types. The first implementation using this technology is a low-cost, low-power processor based on the acclaimed PowerPC 750/sup TM/ microprocessor. This paper describes the microarchitecture and design of the vector arithmetic unit of this implementation.

With the introduction of AltiVec technology, Motorola is again demonstrating its commitment to the PowerPC architecture and to meeting the requirements of next generation high performance computing applications. AltiVec technology expands the PowerPC's capabilities by adding high-bandwidth SIMD functional units to attack complex signal processing challenges. An example 2-D convolution was examined on both scalar and AltiVec processors. An AltiVec enabled processor provides a significant performance improvement over a scalar processor. General purpose processors with SIMD functional units will provide an aggressive performance growth path for embedded and computing systems designers, while lowering development barriers inherent in multiple architecture designs, thereby reducing the time to market and total system development expense.

Testing of modern microprocessor designs remains a challenging problem. At Motorola's Somerset Design Center, we rely heavily on Design-For-Test (DFT) to address these challenges. To date our efforts have been very successful. This paper reviews our DFT methodology and how the DFT group is dealing with the new challenges that are facing PowerPC/sup TM/ microprocessor designs.

This superscalar microprocessor implements the PowerPC/sup TM/ Architecture specification incorporating AltiVec/sup TM/ technology. Two instructions per cycle can be dispatched to two of seven execution units in this microarchitecture designed for high execution performance, high memory bandwidth, and low power. The processor includes 8-way set-associative 32 KB instruction and data caches, a floating-point unit, two integer units, a branch unit, a load/store unit, a vector arithmetic/logic unit, a vector permute unit, and a system unit. An L2 tag and cache controller with a dedicated L2 bus interface supports L2 cache sizes of 512 KB, 1MB, or 2 MB with 2-way set associativity. At 450 MHz, and with a 2M B L2 cache, this processor is estimated to have a SPECint95 and SPECfp95 performance of 20. The processor shares many microarchitectural features with the PowerPC 750/sup TM/ microprocessor. New to this processor are two vector execution units which are part of the AltiVec/sup TM/ instruction set implementation, memory subsystem bandwidth enhancements, symmetric multiprocessing support and improved floating-point performance. Supporting up to 8 simultaneous data cache misses, the memory subsystem sustains bandwidths of 3.2 GB/s on the L2 data SRAM interface running at 200 MHz or 1.6 GB/s on the system interface running at 100 MHz.

Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving input buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit. >

The authors describe the multiprocessing capabilities of the PowerPC architecture and the first implementation of that architecture, the 601 microprocessor. The architected multiprocessing (MP) facilities of PowerPC are presented, and the 601 microarchitecture and system interface are discussed in the context of multiprocessing support. It is pointed out that the PowerPC architecture and the 601 seek to advance the state of the art for multiprocessing by providing a building block that addresses full MP functionality and MP performance in a way that has little risk for the system designer and with performance features heretofore unavailable in the microprocessor marketplace. >