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This letter presents a novel method for the sensitivity analysis between a process parameter and an electrical characteristic using the gradient of a neural network (NN). As devices become scaled and new emerging devices appear, it becomes more complex and the development of a SPICE model takes considerable time. Sensitivity analysis based on NN can accurately obtain the sensitivity even if the data are correlated with each other and have a non-linear relationship. The proposed method can be used to model the device characteristics and optimize process control through component analysis. It is verified using a feedback field-effect transistor (FBFET), one of the emerging neuromorphic devices. We execute experiments with 1055 TCAD simulations calibrated based on 33 measurement data for various process parameters and bias combinations and compare the results with a general linear model (GLM). In this work, we select 7 input parameters and extract voltage threshold ( ${V} _{\text {th}}$ ) and on-current ( ${I} _{\text {ON}}$ ), which are key characteristics of FBFET, as output parameters, and analyze the sensitivity with our method and provide a process control solution. This letter shows an important role in filling the gap between the emerging device proposal and the development of the SPICE model.

In this paper, we proposed and fabricated a polysilicon-based four-terminal synaptic transistor. The device has an asymmetric dual-gate structure. The top gate, which uses a thin SiO₂ layer as the gate dielectric, is the input terminal of the synaptic transistor, which receives spikes from pre-synaptic neurons. Meanwhile, a nitride trapping layer was inserted between the channel and the bottom gate to serve as a non-volatile memory. The bottom gate is the node that receives the post-neuron feedback signals and adjusts the synaptic weight. With this double-gate structure, the proposed artificial synapse can perform short-/long-term memory operations. In addition to the basic unit cell characteristics, a highly integrated synapse array structure is also proposed. In our array structure, the top gate is tied in the word-line direction to accept the input signal. Drain contacts are also tied in the same direction. With regard to bit-line direction, the source terminals are tied to carry post-synaptic signals and the bottom gate line receives feedback signals from the post-synaptic neurons.

We have developed a capacitor-less I&F neuron circuit with a dual gate positive feedback fieldeffect transistor (FBFET) and successfully co-integrated FBFET and CMOS in a wafer. By implementing the neuron circuit with FBFET, we can overcome the limits of conventional CMOS, reduce energy consumption, and imitate the biological neuron. The floating body of the FBFET can replace the membrane capacitor that occupies a large area and performs leaky integration of the neuron. Due to the extremely low sub-threshold swing of the FBFET (less than 0.528mv/dc), energy consumption of the neuron is significantly reduced by suppressing sub-threshold current. Finally, we analyzed the fabricated neuron circuit operation, retention time of the integrated charges and energy consumption compare to conventional CMOS neuron circuit.

We studied the pseudo-homeothermic synaptic behaviors by integrating complimentary metal–oxide–semiconductor-compatible materials (hafnium oxide, aluminum oxide, and silicon substrate). A wide range of temperatures, from 25 °C up to 145 °C, in neuronal dynamics was achieved owing to the homeothermic properties and the possibility of spike-induced synaptic behaviors was demonstrated, both presenting critical milestones for the use of emerging memristor-type neuromorphic computing systems in the near future. Biological synaptic behaviors, such as long-term potentiation, long-term depression, and spike-timing-dependent plasticity, are developed systematically, and comprehensive neural network analysis is used for temperature changes and to conform spike-induced neuronal dynamics, providing a new research regime of neurocomputing for potentially harsh environments to overcome the self-heating issue in neuromorphic chips.

We perform a system-level simulation of hardware spiking neural network (SNN) consisting of silicon-based synaptic transistors and integrate-and-fire (I&F) neuron circuits. Using electrical models of the synaptic device and I&F neuron circuit, a three-layer fully connected SNN in hardware is presented for MNIST pattern recognition by means of ex situ training. Right-justified rate coding is employed as an information encoding method, and negative weight values are implemented by a pair of the synaptic transistors (specifically, excitatory and inhibitory synapses). Furthermore, the variability effect occurring in the devices and circuits is demonstrated. This result indicates that the system has tolerance to the variations and how precisely the variations need to be controlled for hardware SNN applications.

We designed the CMOS analog integrate and fire (I&F) neuron circuit can drive resistive synaptic device. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, asymmetric negative and positive pulse generation part, a refractory part, and finally a back-propagation pulse generation part for learning of the synaptic devices. The resistive synaptic devices were fabricated using HfOx switching layer by atomic layer deposition (ALD). The resistive synaptic device had gradual set and reset characteristics and the conductance was adjusted by spike-timing-dependent-plasticity (STDP) learning rule. We carried out circuit simulation of synaptic device and CMOS neuron circuit. And we have developed an unsupervised spiking neural networks (SNNs) for 5 × 5 pattern recognition and classification using the neuron circuit and synaptic devices. The hardware-based SNNs can autonomously and efficiently control the weight updates of the synapses between neurons, without the aid of software calculations.

In this paper, we propose a compact neuromorphic system that can work with four-terminal Si-based synaptic devices for spiking neural networks. The system consists of Si-based floating-body synaptic transistors and integrate-and-fire neuron circuit. The synaptic device can change its weight using floating-body effect and charge injection into the floating gate. The neuron circuit integrates signals from the synaptic devices through current mirrors and generates an action-potential when the integrated signal value exceeds a threshold value. The generated action potential that is transmitted to postsynaptic neurons is simultaneously returned to the back gate of the synaptic device for the change of weight based on spike-timing-dependent-plasticity. As the four-terminal synaptic device can transmit preneuron signals and change its weight at the same time, we can constitute the compact neuromorphic system without additional switches or logic operation and emulate the operation of neuron with a minimum number of devices and power dissipation (~3 pJ).

In this work, we developed a SPICE compact model of a dual-gate positive-feedback field-effect transistor (FBFET) for circuit simulations by fitting the model to measurement results. We fabricated a FBFET and investigated the DC and transient characteristics. The fabricated FBFET has an extremely low sub-threshold slope and a low off current. The FBFET operates as a forward-biased PN diode after the device is turned on due to the positive feedback loop between the integrated charges and the potential barrier. When enough electrons are accumulated in the floating body, the potential barrier is lowered and the FBFET is turned on rapidly, and due to the integrated charges, the FBFET has memory characteristics which approximate hose of 1T-DRAM. Reflecting these electrical characteristics of the FBFET, we undertook SPICE modeling and obtained simulation results that were similar to the measurement characteristics. Finally, we implement a modified inverter with the FBFET connected in parallel with an n-type MOSFET (NMOS). Due to the superior sub-threshold characteristics of the FBFET, it effectively suppresses the sub-threshold currents.

Tunneling field-effect transistors (TFETs) have been studied as a candidate for low-power device due to the remarkable subthreshold characteristics. However, digital circuits composed of TFET have significantly large propagation delay compared with the conventional MOSFET circuits because of small current drivability and large gate-to-drain capacitance. In this work, the electrical characteristics of the self-boosted TFETs with nitride charge trapping layer have been studied using TCAD simulations. Trapped charges in the nitride layer improve subthreshold characteristics and on-current (I(ON)) of both nTFET and pTFET during gate bias sweep. In addition, the benefits of the self-boosted TFET devices to low supply voltage system application are investigated. Energy consumption and propagation delay of both conventional and self-boosted TFET inverters are compared by the mixed-mode circuit simulation study. Energy consumption is almost same but the propagation delay of the self-boosted TFET inverter is reduced especially for ultra-low voltage operation where system delay is increased dramatically.

A new synaptic transistor was fabricated with two separated gates based on a FinFET structure in order to mimic short- and long-term memories in a biological synapse and connect with a postsynaptic neuron circuit directly. The transition between short- and long-term memories occurred after applying repetitive input pulses and strongly depended upon intervals between input pulses. These findings indicate that it has very similar learning characteristics with a biological synapse and the possibility as a synaptic device in neuromorphic systems.

In this work, we investigate the dual gate positive feedback field-effect transistor (FBFET) using DC and transient TCAD simulation. I-V characteristics, subthreshold swing, and transient characteristics are analyzed. The FBFET has steep switching property and low off current. We design an inverter that can low power operate with the FBFET. By using the FBFET, the stand-by current is effectively suppressed in analog circuit.

We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has shortterm and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.

In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy consumption of a conventional and the proposed neuron circuits. In a single neuron circuit with microsecond duration pulses, 58% of the energy consumption is reduced by incorporating a FBFET. We performed SPICE compact modeling of FBFET, and its parameters were fitted to match the measurement results of the fabricated FBFET. Then, we conducted a circuit simulation to verify the operating neural networks. We implemented a single layer spiking neural network (SNN) that had resistive synaptic devices. In the SNN simulation, approximately 94% of the average power consumption of all output neurons was reduced.

A new object tracking mask-based novel-look-up-table (OTM-NLUT) method is proposed and implemented on graphics-processing-units (GPUs) for real-time generation of holographic videos of three-dimensional (3-D) scenes. Since the proposed method is designed to be matched with software and memory structures of the GPU, the number of computeunified-device-architecture (CUDA) kernel function calls and the computergenerated hologram (CGH) buffer size of the proposed method have been significantly reduced. It therefore results in a great increase of the computational speed of the proposed method and enables real-time generation of CGH patterns of 3-D scenes. Experimental results show that the proposed method can generate 31.1 frames of Fresnel CGH patterns with 1,920 x 1,080 pixels per second, on average, for three test 3-D video scenarios with 12,666 object points on three GPU boards of NVIDIA GTX TITAN, and confirm the feasibility of the proposed method in the practical application of electro-holographic 3-D displays. (C) 2015 Optical Society of America

In this paper, we propose a new approach for accelerated computation of the computer-generated hologram (CGH) of a 3-D object by using the N×N-point principle fringe patterns (PFPs)-based novel look-up table (N-LUT) method. Using the two-dimensional (2-D) run-length encoding (RLE) algorithm, redundant data of a 3-D object are extracted in image blocks and re-grouped into an N×N-point redundancy map depending on the block size. Basing on this redundancy map, the N×N-point PFPs are calculated, from which the CGH pattern of a 3-D object can be generated. With the block-based extraction of the redundant data and the N×N-point PFPs-based computation of the CGH pattern, the object points to be calculated could be significantly reduced, which results in a great increase in the computational speed. Experimental results show that for 3×3-point PFPs, the computational speed of the proposed method has been improved by 61.16% compared to the conventional N-LUT method.

In this paper, a new method for efficient generation of video hologram for 3-D video is proposed by combined use of redundant data of 3-D video and look-up table techniques. That is, temporal redundant data in inter-frame of 3-D video image is removed using differential pulse code modulation (DPCM) method between frames then inter-line redundant data in intra-frame of 3-D video image is also removed using DPCM algorithm between lines. Experimental results show that, in the proposed method, the average number of calculated object points for 3-D objects have been reduced by 23.3% for top-down scanning scheme, compared to the conventional TR_NLUT method. And, the average calculation time for one object point has been also reduced by 21.0%, compared to the conventional TR_NLUT. Good experimental results with 3-D test moving pictures finally confirmed the feasibility of the proposed method in fast generation of CGH patterns for 3-D videos.

A one-dimensional novel-look-up-table (1-D N-LUT) has been implemented on the graphics process- ing unit of GTX 690 for the real-time computation of Fresnel hologram patterns of three-dimensional (3-D) objects. For that, three types of optimization techniques have been employed, which include the packing tech- nique of input 3-D object data and the managing techniques of on-chip shared memory and registers. Experimental results show that the average hologram calculation time for one object point of the proposed sys- tem has been found to be 0.046 ms, which confirms that the proposed system can generate almost 3 frames of Fresnel holograms with 1920 × 1080 pixels per second for a 3-D object with 8000 object points. © The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires

In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word line.