Search

The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this article adopts a staggered PAD using the redistribution layer (RDL) to reduce the distance to four PADs; it enables the mitigation of bandwidth limitation of half-rate clocking, a lower phase mismatch, and a reduced propagation delay. The proposed half-rate clocking-based GDDR6 DRAM achieves 24 Gb/s/pin on a 1.35-V DRAM process. Also, the power-supply-induced-jitter (PSIJ) value is improved from 9.97 to 3.22 ps, compared to a GDDR6 design using a quarter-rate clocking. In addition, the phase mismatch of the proposed clock distribution network (CDN) is reduced compared to the conventional CDN, resulting in an improvement of the 3-σ value of the phase skew from 4.16 to 2.25 ps.

Conventional implantable electrocardiogram monitors are impenetrable to electromagnetic radiation, posing challenges in imaging (i.e. X-rays). In this study, we demonstrate a radiolucent implantable electrocardiogram (ECG) device using graphene sheets and Parylene substrate which allows bypassing of electromagnetic radiation through the implanted device. Evaluated on a canine model, the graphene electrodes detect signals comparable to those recorded using surface electrodes, presenting a valuable and novel modality for medium and long-term monitoring of cardiac rhythm. When compared with current technology, the new system has the distinct advantages of being flexible and radiolucent, thereby improving patient comfort, and avoiding device artifact and shadowing on clinical radiographic imaging.

Two approaches to extract equivalent dipole arrays of integrated circuits (ICs) from only magnitude information of near-field scanning data are compared and applied to a test IC. One approach is based on the nonlinear least square (NLS) fitting, and the other is extracting the dipoles from the complex field data after retrieving the field phases. Using a commercial simulation tool, the extracted dipole arrays are tested to estimate the fields caused by the IC with- and without-an additional shielding structure.

The jitter probability density function (PDF) at multistage output buffers due to supply voltage fluctuations is analytically derived. For experimental validation, an integrated circuit (IC) is designed, fabricated, and assembled in a printed circuit board (PCB). The on-chip supply voltage fluctuations are extracted from the simultaneous measurements at the pads on IC and PCB and used to calculate the jitter PDF of the multistage buffers. Also, characteristics of the output channels are measured and modeled with the separately designed channel pattern. Finally, the jitter PDFs for multistage buffers are calculated and compared with the measured jitter histograms.

Hyungsoo Kim and Ze’ev Ronai preview work from Colaluca et al. that reveals the function of Numb exon 3–containing isoforms in the formation of a fuzzy complex with Mdm2 and the regulation of p53 stability., Although numerous pathways are known to control the tumor suppressor protein p53, coordinated regulation of the p53–Notch axis by Numb may have an even more remarkable impact. In this issue, Colaluca at al. (2018. J. Cell Biol. https://doi.org/10.1083/jcb.201709092) reveal an unexpected role of a newly characterized Numb splice variant in the regulation of p53, which may have significant implications for therapeutic intervention in breast cancer.

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics.

An analytical method to calculate the electric- and magnetic fields near a planar PDN with decoupling capacitors has been proposed. Magnetic current source along the plane edges with multiple decoupling capacitors is calculated using the cavity resonant model. The electric- and magnetic fields in the near field region calculated from the magnetic currents are validated with the results obtained using PEEC method.

In this paper, we present and verify a new chip-package co-modeling and simulation approach for a low-noise chip-package hierarchical power distribution network (PDN) design. It is based on a hierarchical modeling to combine distributed circuit models at both chip-level PDN and package-level PDN. In particular, it includes all on- and off-chip parasitic circuit elements in the hierarchical PDN with a special consideration on on-chip decoupling capacitor design and placement inside chip. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z11 and Z21 PDN impedance measurements with a frequency range from 1MHz to 3GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the chip-level PDN and the package-level PDN. Furthermore, we can precisely anticipate PDN resonance frequencies, noise generation sources, and noise propagation paths through the multiple levels in the hierarchical PDN.

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme and Duty-Training Circuit (DTC) is presented. A Low Voltage-Swing Terminated Logic (LVSTL) driver using 4-to-1 multiplexer is implemented to the transmitter. A DTC to adjust the CK duty is implemented to the receiver. In addition, a ZQ calibration scheme for Multi-VOH level is also presented. Designed schemes are compatible with the LPDDR4 standard. Power efficiency for the I/O interface is about 2.3mW/Gb/s/pin with 1.1V supply in 2y-nm DRAM process, which is 31% lower than that of LPDDR3.

Thanks to numerous empirical research studies, a general consensus has been reached on the effects of an aging population on the economy, particularly in terms of economic growth and savings. However, most of the previous research examines the effects of the aging on economically advanced countries. Furthermore, rarely have those studies used the time-series properties of the data. By applying two popular time-series statistical tools (multivariate cointegration analysis and vector error correction model) to Korean data, this paper finds: (1) There is a long-run equilibrium linkage among the aging, medical expenditure and savings; however (2) there is no Granger-causality present between aging and national savings in the short run in Korea.

von Hippel-Lindau (VHL) disease is a rare autosomal dominant cancer syndrome. Although hypoxia-inducible factor-alpha (HIFalpha) is a well-documented substrate of von Hippel-Lindau tumor suppressor protein (pVHL), it remains unclear whether the dysregulation of HIF is sufficient to account for de novo tumorigenesis in VHL-deleted cells. Here we found that pVHL directly associates with and stabilizes p53 by suppressing Mdm2-mediated ubiquitination and nuclear export of p53. Moreover, upon genotoxic stress, pVHL invoked an interaction between p53 and p300 and the acetylation of p53, which ultimately led to an increase in p53 transcriptional activity and p53-mediated cell cycle arrest and apoptosis. These results suggest that the tumor suppressor pVHL has an unexpected function to upregulate the tumor suppressor p53.

Epoxy/BaTiO/sub 3/ composite embedded capacitor films (ECFs) were newly designed for high dielectric constant and low-tolerance (less than /spl plusmn/5%) embedded capacitor fabrication for organic substrates. In terms of material formulation, ECFs are composed of a specially formulated epoxy resin and latent curing agent, and in terms of a coating process, a comma roll coating method is used for uniform film thickness in large area. The dielectric constant of ECF in high frequency range (0.5/spl sim/3 GHz) is measured using the cavity resonance method. In order to estimate dielectric constant, the reflection coefficient is measured with a network analyzer. The dielectric constant is calculated by observing the frequencies of the resonant cavity modes. Calculated dielectric constants in this frequency range are about 3/4 of the dielectric constants at 1 MHz. This difference is due to the decrease of the dielectric constant of the epoxy matrix. The dielectric relaxation of barium titanate (BaTiO/sub 3/: BT) powder is not observed within measured frequency. An alternative material for embedded capacitor fabrication is epoxy/BaTiO/sub 3/ composite embedded capacitor paste (ECP). It uses similar materials formulation like ECF and a screen printing method for film coating. The screen printing method has the advantage of forming a capacitor partially in the desired part. However, the screen printing makes surface irregularities during mask peel-off. Surface flatness is significantly improved by adding some additives and by applying pressure during curing. As a result, a dielectric layer with improved thickness uniformity is successfully demonstrated. Using epoxy/BaTiO/sub 3/ composite ECP, a dielectric constant of 63 and specific capacitance of 5.1 nF/cm/sup 2/ were achieved.

Through silicon via (TSV) based 3-dimensional integrated circuit (3D IC) has become the key solution to satisfy continuously increasing demands for small form factor, wide bandwidth, high performance, and low power consumption on electronic devices. However, there still remain several challenges to be solved; one of the most significant issues in 3D IC is TSV to active circuit noise coupling. In this paper, we analyzed the noise coupling between TSV and LC-VCO, which is an important component in RF communication system. When TSV is located near LC-VCO, the noise can easily travel through silicon substrate to the body of MOSFETs in LC-VCO. The noise coupling mechanisms of TSV to PMOS and NMOS are analyzed by voltage transfer functions in frequency-domain obtained by 3D electromagnetic solver simulation. The voltage transfer function between TSV and MOS is analyzed under variations of several physical parameters to clarify the tendencies of noise coupling. In addition, the noise coupling effect on PMOS and NMOS in LCVCO are investigated and compared in terms of sensitivity, such as phase noise.

Crosstalk noise has become a significant problem in the design of high-speed digital interconnections. In this paper, we demonstrate a crosstalk reduction method, which has been successfully applied to the design of a CAT-5E modular jack. The CAT-5E is a newly adopted cabling and connector standard for advanced cabling network systems to assure more robust, reliable and high-speed operation, which is based on differential mode signal transmission using unshielded twist pair (UTP) cable. The improved design of the modular jack shows minimal crosstalk noise and return loss over a wide range of manufacturing conditions. The improved crosstalk characteristics of the modular jack were accomplished by inserting embedded capacitors on the printed circuit board (PCB) of the modular jack. The embedded capacitors compensate for the unbalanced capacitive crosstalk that occurs in the plug and insert. In particular, the embedded balancing capacitor is designed to have maximum capacitance, with limited PCB area, by using a double-sided PCB design. Less than -45 dB near-end-crosstalk (NEXT) was achieved after the crosstalk noise compensation, satisfying the CAT-5E specification for frequencies up to 100 MHz.

Transmission line structures are needed for the high-performance interconnection lines of GHz integrated circuits (ICs) and multichip modules (MCMs), to minimize undesired electromagnetic wave phenomena and, therefore, to maximize the transmission bandwidth of the interconnection lines. In addition, correct and simple models of the interconnection lines are required for the efficient design and analysis of the circuits containing the interconnection lines. In this paper, we present electrical comparisons of three transmission line structures: conventional metal-insulator-semiconductor (MIS) and the embedded microstrip structures-embedded microstrip (EM) and inverted embedded microstrip (IEM). In addition, we propose closed-form expressions for the embedded microstrip structures EM and IEM and validate the expressions by comparing with empirical results based on S-parameter measurements and subsequent microwave network analysis. Test devices were fabricated using a 1-poly and 3-metal 0.6 /spl mu/m Si process. The test devices contained the conventional MIS and the two embedded microstrip structures of different sizes. The embedded microstrip structures were shown to carry GHz digital signals with less loss and less dispersion than the conventional MIS line structures. S-parameter measurements of the test devices showed that the embedded microstrip structures could support the quasi-TEM mode propagation at frequencies above 2 GHz. On the other hand, the conventional MIS structure showed slow-wave mode propagation up to 20 GHz. More than 3-dB/mm difference of signal attenuation was observed between the embedded microstrip structures and the conventional MIS structure at 20 GHz. Finally, analytical RLCG transmission line models were developed and shown to agree well with the empirical models deduced from S-parameter measurements.

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method.

We measured and demonstrated the great advantages of embedded film capacitors in reducing power/ground inductive impedance and the suppression of SSN at frequencies up to 3 GHz for high-performance multilayer packages and PCBs. Eight-layer test PCBs were fabricated, and their inductive power/ground network impedances were measured as a function of film thickness, via distribution, and combined use with discrete decoupling capacitors, using a two-port self-impedance measurement method. This successfully demonstrated that the power/ground inductive impedance was reduced from 270 pH to 106 pH simply by using an embedded film capacitor instead of 16 discrete decoupling capacitors.

While multiple-input multiple-output (MIMO) system gives many advantages to wireless communication, the complexity of multiple RF chains gives a burden to the system. Antenna selection is introduced as a technique to reduce the burden. On the transmit antenna selection scheme, the exhaustive search for optimal antenna set quickly becomes impractical as adopting more antennas. To reduce complexity for searching, we propose an efficient transmit antenna selection method. We first make a threshold for optimal antenna set by using Poincare separation theorem. Instead of exhaustive search, we select a transmit antenna subset that exceeds the threshold. On the exponentially correlated channel of array antennas, we give an order to search for reducing complexity further. We search from the most remotely located antenna subset which in generally less correlated to the closely located antennas which is more correlated. Finally, we show the BER performance and tradeoff relation between performance and complexity by Monte-Carlo simulations.

In this paper, we propose an adaptive on-chip equivalent series resistor (ESR) controller scheme to reduce on-chip simultaneous switching noise (SSN). The on-chip controllable ESR is adaptively changed to reduce the on-chip SSN by using the proposed scheme. Reduction of on-chip resonance and on-chip SSN is well proved through simulated results and measurements of the fabricated test chip in a 65 nm HYNIX CMOS process.

The modeling and simulation results about the IC and package power/ground network have been depicted. With the modeling for broadband frequency region, the effect of each part in power/ground network on IC and package was analyzed in frequency domain. Keywords-modeling; simulation; power/ground network; high frequency; IC and package

The co-modeling and co-simulation results about the package and on-chip power/ground network have been demonstrated. The inevitable parallel resonance peak, due to the inductive parasitic on the package and on-chip decoupling capacitor, was analyzed in frequency domain. Subsequently, the co-design procedure for the resonant free power/ground network was suggested and evaluated simply in frequency domain.

Epoxy/BaTiO/sub 3/ composite embedded capacitor films (ECFs) were newly designed for high dielectric constant and low tolerance (less than /spl plusmn/5%) embedded capacitor fabrication in organic substrates. In terms of material formulation, ECFs were composed of specially formulated epoxy resin and latent curing agent. And in terms of coating process, a comma roll coating method was used for a uniform film thickness over large area. Dielectric constants of BaTiO/sub 3/ & SrTiO/sub 3/ composite ECFs were measured with MIM (metal-insulator-metal) capacitors at 100 kHz using LCR meter. Dielectric constants of BaTiO/sub 3/ ECFs were larger than these of SrTiO/sub 3/ ECFs, due to the difference of permittivity of BaTiO/sub 3/ and SrTiO/sub 3/ particles. Dielectric constants of BaTiO-, & SrTiO/sub 3/ ECFs at high frequency range (0.5/spl sim/10GHz) were measured using a cavity resonance method. For both powders, dielectric constants in high frequency range were about 3/4 of the dielectric constants at 1 MHz. This difference is mainly due to the decrease of dielectric constant of epoxy matrix. For BaTiO/sub 3/ ECFs, there was a dielectric relaxation at 5/spl sim/9GHz presumably due to the polarization mode change of BaTiO/sub 3/ powder. However in case of SrTiO/sub 3/ ECFs, there was no relaxation up to 10GHz.

We have thoroughly investigated and experimentally demonstrated the great advantages of thin film embedded capacitors of high dielectric constant in reducing power/ground impedance and suppressing SSN and radiated emission up to a frequency of 1 GHz. About 10 dB or more suppression of the radiated emission was acquired for a wide frequency range, including high-numbered harmonics of the clock frequency, by using the thin film embedded capacitor of high dielectric constant.

The voltage fluctuations of the power/ground lines on ICs, packages, and modules have become the major source of the radiated emission. Combined suppression techniques including shielding, cabling and filtering at the package level and the module level are not enough for the complete suppression of radiated emission. Moreover, the power/ground line fluctuations and the resulted radiated emissions caused by the IC surge current must be controlled and considered at the IC design procedure. We have demonstrated more than 10-dB suppression of the radiated emission from a commercial 8-bit micro-controller using on-chip gate oxide filtering capacitors. The filtering capacitors are placed under the power/ground buses and the signal buses without ever increasing the die size.

Significant reduction of power/ground inductive impedance and SSN suppression was successfully demonstrated by using embedded capacitor film in high performance package and PCB up to 3GHz frequency range. The reduction of the inductance impedance and SSN are acquired by the help of reduced via inductance in the embedded film capacitor.

The Java platform provides a fully fledged programming environment for graphics applications using the Abstract Window Toolkit (AWT). We present a power-aware basis profile of the Java 2 Micro Edition (J2ME) for embedded applications. The low-power basis profile (LPBP) is responsive to backlight luminance scaling in such a way that dynamic adjustment of the backlight luminance is accompanied by adaptive image compensation. The proposed scheme performs aggressive backlight dimming while maintaining the readability of screen contents based on image compensation techniques such as brightness compensation, image enhancement and context processing. Experiments show that on average the LPBP can easily achieve approximately 30% backlight system power reduction.

The power/ground fluctuation is known as a significant source of radiated emission. We discuss the separated functions of on-PCB and on-chip decoupling capacitors on the suppression of electromagnetic radiated emission. Due to the different ranges of parasitic inductance and the different locations of the on-chip current drivers, on-PCB and on-chip decoupling capacitors exhibit separated frequency characteristics in terms of suppression efficiency of radiation. The roles of on-PCB and on-chip decoupling capacitors are estimated by circuit simulation and a simple antenna model, and are confirmed by experiments. It is found that the on-chip decoupling capacitors are mainly effective for the suppression of radiated emission over 100 MHz frequency. Increase of the on-chip decoupling capacitance and decrease of the parasitic inductance of the package produce an improved suppression ratio at high frequency range. Combined placement and sizing of the decoupling capacitors have achieved more than 10 dB suppression of the electromagnetic radiated emission over a wide spectrum range.

We have successfully designed a PCB substrate with the embedded balancing capacitors for the category-5E modular jack to compensate the unbalanced capacitive crosstalk noise. The NEXT (near-end crosstalk) after the crosstalk compensation is below -45 dB at 100 MHz.

Recently, electromagnetic interference (EMI) and radiated emission has become a major problem for high-speed circuit and package designers, and it is likely to become even severe in the future. However, until recently, designers of integrated circuit and package did not give much consideration to electromagnetic radiated emission and interference in their designs. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital system and boards. However, there has not been a systematic study to understand the effects of on-chip and off-chip decoupling capacitors on the electromagnetic radiated emission. In this paper, we report the simulation and the measurement results regarding the radiated emission due to the power/ground bounce. And we discuss the effects of the on-chip and off-chip decoupling capacitors to the power/ground bounce and the electromagnetic radiated emission. This circuit is simulated using HSPICE. Test ICs and printed circuit boards were designed and fabricated. Using a transverse electromagnetic (TEM) cell, the radiated electric field of the device under test (DUT) is measured. Combined placement of the on-chip and off-chip decoupling capacitor achieves more than 10 dB suppression of the radiated emission on the whole spectrum region. The design rule of the optimum placement of the decoupling capacitor was obtained.

Even though the electromagnetic radiated emission due to the ground and power line fluctuation of the integrated circuit (IC) and printed circuit board (PCB) is minimized, the additional reduction of the radiated emission from the clock and the signal lines are not easy. In this paper, we introduce a new clock and signal line scheme to suppress the radiated emission from the fast transition of the clock and data signals. We proved that the proposed differential-line-scheme (DLS) could reduce the radiated emission by more than 10 dB compared to the conventional single-line-scheme (SLS). First, we report the necessity and the usefulness of the differential-line-scheme and explain the operation of the inverter circuit for the differential-line-scheme using HSPICE simulation. Test ICs and PCBs were designed and fabricated, to verify the effect of differential-line-scheme with the proposed inverter circuit. The electromagnetic radiated emission due to the device under test (DUT) is measured using a gigahertz transverse electromagnetic (GTEM) cell. The measured result has shown that the differential-line-scheme with the proposed inverter circuit achieves more than 10 dB suppression of the electromagnetic radiated emission. The results confirm that the clock and signal line is fundamental source of the radiation. The proposed differential-line-scheme with the proposed inverter circuit will be useful for both high-speed digital IC and PCB design.

Recently, electrical performances of high-speed digital integrated circuits and MCMs have been limited by undesired RF phenomena of interconnection lines, such as delay attenuation, crosstalk, dispersion, reflection, and noise. Transmission line structures are required for future interconnection lines of the integrated circuits and MCMs to minimize the RF effects and, therefore, to maximize transmission bandwidth and minimize signal loss of the interconnection lines. Also, to predict those effects, it is necessary to use correct and simple electrical models of the transmission line structures. In this paper, we propose new embedded microstrip structures, such as an embedding microstrip (EM) and an inverted embedding microstrip (IEM) structures for the MCM-Si interconnection line. The proposed IEM and EM structures are proven to be less lossy and dispersive at high frequencies than the conventional MCM-Si interconnection line structures. The proposed line structures were demonstrated to support low loss quasi-TEM mode propagation through the lines. The characteristics and frequency dependent electrical models of the proposed structures will be reported based on microwave S-parameter measurements up to 20 GHz.