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This article presents a circuit model that is able to capture the full nonlinear behavior of an asymmetric electrostatic transducer whose dynamics are governed by a single degree of freedom. Effects such as stress-stiffening and pull-in are accounted for. The simulation of a displacement-dependent capacitor and a nonlinear spring is accomplished with arbitrary behavioral sources, which are a standard component of circuit simulators. As an application example, the parameters of the model were fitted to emulate the behavior of an electrostatic MEMS loudspeaker whose finite-element (FEM) simulations and acoustic characterisation where already reported in the literature. The obtained waveforms show good agreement with the amplitude and distortion that was reported both in the transient FEM simulations and in the experimental measurements. This model is also used to predict the performance of this device as a microphone, coupling it to a two-stage charge amplifier. Additional complex behaviors can be introduced to this network model if it is required.

The charge-generating sensors are widely used in many applications in consumer, automotive and medical electronics. They generate a charge proportional to the applied input quantity: pressure, temperature, acceleration, strain, light, etc. Usually, charge amplifiers are used to register such signals. The charge amplifier is an integrator that integrates the input current over time. In continuous-time signal processing, a parallel resistor is used to dissipate the energy stored on the integration capacitor, and such self-zeroed integrator circuits are known as lossy integrators. To achieve low-frequency operation, when a capacitor is in the picofarad range, a very high-ohmic resistor, in the range of gigaohms, must be used. Such a high-ohmic resistor increases the output offset voltage to an unacceptable level. To overcome the output offset problems, a composite charge amplifier has been recently introduced. This paper presents an innovative lossy integrator readout circuit which contains only one opamp in the feedback. The circuit can be easily adapted to the needed gain and cut-off frequency. Its operation is validated by experimental results. The sufficiently low high-pass cut-off frequency allows the circuit to be used for biosignal amplification. Heart and respiration rates can be easily recorded with piezoelectric sensors attached to the wrist or lung wall. The presented circuit can benefit many applications where charge-to-voltage conversion is needed.

Piezo-electric sensors have found widespread application today due to their ability to provide an interface between the mechanical and electronic world. For humans, in order to interact with these materials, we require an electronic interface. This paper describes one of the possible interfaces, which includes a charge amplifier cascaded with a filter circuit to obtain the frequency response. A novel circuitry consisting of a rectifier and comparator is used to identify the activated channels of the array of piezoelectric sensor. This signal conditioning circuit makes use of active devices such as op amps and nonlinear devices such as diodes along with passive components. The novel circuitry is designed for 2 channels, and demonstrates the logic of selection of these based on the signal parameters. This concept can be extended to any number of channels.

The charge amplifier is an important building block in various electronic circuits. In this paper a new charge amplifier for piezoelectric sensors is introduced. The advantages of the new proposed charge amplifier becomes obvious in the quasi-static applications. In some quasi-static applications the traditional charge amplifiers uses an extremely large feedback resistor (in the range of $\text{G}\Omega $ ) whereas the proposed charge amplifier no longer requires such extremely large resistors. Moreover the proposed circuit reduces the output offset voltage significantly in comparison with conventional charge amplifier. The proposed circuit can be also implemented by using general purpose JFET operational amplifiers instead of using electrometer operational amplifiers therefore the cost of implementation will be reduced significantly in comparison with conventional charge amplifier. The proposed charge amplifier was assembled by using general purpose JFET Op-Amp to capture and amplify the output voltage of the piezoelectric vibration sensor Minisense100. In this experiment the low-cutoff frequency and the gain of the proposed charge amplifier were set equal to 0.2Hz and 20.5 dB respectively. The output offset voltage of the circuit was measured equal to 210 $\mu \text{V}$ .The measurement of very small vibration (±0.015g) showed a relative error equal to 2.1% with respect to the value which is obtained by using vibration meter as reference.

A charge amplifier with noise peaking suppression and gain drop compensation is proposed. By utilizing the proposed Quasi-Miller RC network, the noise peaking is suppressed and gain drop is compensated, which alleviates the design trade-off between charge gain and output root-mean-square (RMS) noise, therefore obtains an improved sensitivity. Meanwhile, the Quasi-Miller RC network permits the charge amplifier to support ultra-low frequency operation without using a huge resistor, which is normally required by the charge amplifier. The fabricated charge amplifier demonstrates an input-referred RMS noise charge of 909 aC, a charge gain of 10.2 V/pC and a 3-dB bandwidth from 80 Hz to 38 MHz. Low noise and high charge gain are obtained simultaneously. Meanwhile, extremely low cut-off frequency is also obtained, which is beneficial to maintain the signal integrity.

Charge amplifiers, characterized by their charge-sensitivity or charge gain, are essential components of a transducer-interfacing system that amplify charge signals emerging from various sensors and convert them into voltage signals. Today, with increased scaling of MOSFETs, it becomes challenging to obtain the charge amplifiers with high charge sensitivity and low power. Furthermore, if the charge amplifier is to be operated at lower bandwidth, then obtaining low noise at higher charge sensitivity is also difficult. In this paper, the authors propose a novel design of a charge-sensitive preamplifier in 90 nm CMOS technology that can be operated at the frequency range of 10 Hz-10 kHz, suitable for biosignals at lower frequencies. The opamp in the preamplifier is designed to have a folded-cascode structure with composite cascoding at its input transistors for low power operation. A feedback resistance of 185.20 GΩ for the preamplifier is actively realized using long-channel cascode MOSFET stage in the opamp, thereby eliminating the need for a large value of passive resistance on-chip. The preamplifier has a high charge sensitivity of 8.875 mV/fC at a low power consumption of 214.32 nW with input-referred noise of 256.89 μV for the bandwidth 10 Hz-10 kHz. The preamplifier operation is verified by interfacing the model of the preamplifier with the small-signal equivalent of a SPICE model of a Silicon Nanowire Field-effect Transistor (SiNW-FET) based biosensor which was proposed for impedimetric sensing of biomolecules.

We describe a common-mode feedback circuit (CMFB) for a charge detector. The amplifier is implemented in a 180-nm complementary metal-oxide-semiconductor (CMOS) process. The amplifier combines a folded differential topology, active reset, and small feedback capacitors. This allows for low noise, high-gain, high-dynamic-range, and robust operations. The design and analysis of the CMFB for the proposed high-gain charge amplifier is discussed. Simulation results show that the CMFB loop has a phase margin of 62.1 degrees and a gain margin of 25 dB. Measurement results show the amplifier chip exhibits a stable common mode voltage.

A detector connected to a charge amplifier adds parasitic input capacitance that alters the amplifier's gain. The detector capacitance therefore must be characterized so as to properly account for its effect. This paper presents a novel, compact technique to measure the detector capacitance by exploiting the circuit elements within the charge amplifier itself. Reconfiguring the charge amplifier with programmable switches, a capacitor divider network emerges to measure the detector capacitance without the need for any accurate timing references and complex controls. Experimental results of the proposed charge amplifier fabricated in a 180-nm CMOS technology demonstrate the ability to measure the detector capacitance to within 3% of its actual value. An actual charge measurement is also presented.

The paper theoretically determines the dependence of the electrically excited noise, damped oscillations piezoelectric sensor, integrated with SWCNT (single-wall carbon nanotube) needle and charge amplifier, from defects of an SWCNT graphene sheet and sensor malfunctions generally, for AFM (atomic force microscopy) with high-resolution. Also is the proposed method for estimating the piezoelectric sensor state, integrated with the SWCNT needle and charge amplifier when evaluating “SWCNT needle-surface” contact in real-time scanning AFM. Many micro-machining techniques have been employed to fabricate signal oscillations piezoelectric sensors and piezoelectric nanoactuators. The properties of SWCNT, for example, high strength, many times greater than the strength of steel, makes them suitable elements for use as needles probe microscopy. This paper presents both experimental and analytical data to show the critical characteristics of a piezoelectric sensor, integrated with SWCNT needle contact in the real-time scanning AFM.

A digital closed-loop system design of a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) is proposed in this paper. Vibration models with non-ideal factors are provided based on the structure characteristics and operation mode of the sensing element. The DRG operates in force balance mode with four control loops. A closed self-excited loop realizes stable vibration amplitude on the basis of peak detection technology and phase control loop. Force-to-rebalance technology is employed for the closed sense loop. A high-frequency carrier loaded on an anchor weakens the effect of parasitic capacitances coupling. The signal detected by the charge amplifier is demodulated and converted into a digital output for subsequent processing. Considering compatibility with digital circuits and output precision demands, a low passband sigma-delta (&Sigma, &Delta, ) analog-to-digital converter (ADC) is implemented with a 111.8dB signal-to-noise ratio (SNR). The analog front-end and digital closed self-excited loop is manufactured with a standard 0.35 &micro, m complementary metal-oxide-semiconductor (CMOS) technology. The experimental results show a bias instability of 2.1 &deg, /h and a nonlinearity of 0.035% over the &plusmn, 400&deg, full-scale range.

We report the characterisation and calibration of a new laser pulse energy measurement device, developed for pico-joule pulse energy measurement at repetition rates up to 1 kHz. The device comprises a charge integration amplifier operating in conjunction with an input charge source; a light trapping photo-detector, which converts an incident laser pulse to a charge pulse. The novel amplifier individually integrates each charge pulse from the source and outputs a corresponding 20-bit resolution digital signal. This signal is converted to pulse energy through post processing, knowing the absolute responsivity of the photodiode detector and the calibration factors of the charge amplifier. A differential evolution algorithm is used to determine optimised values for the feedback capacitors of the amplifier, the amplifier gain and offset. The values measured by the new laser pulse energy meter were compared with those obtained from measurements traceable to both the high and low-level laser pulse energy scales maintained by NIST, Boulder. These were consistent within the combined expanded measurement uncertainty. This new device offers lower uncertainty and portability, suitable for field use.

This study is dedicated to design an in-cell active-matrix capacitive (IAMC) touch panel and its readout circuitry. This IAMC touch panel is in a structure that embeds all components for touch panel in a standard active matrix display. In this way, the thickness of the display-touch combined module can be significantly reduced, but introducing much noise from display to touch module, leading to higher mis-judgements on touches. To solve the problem, this study proposes a new readout circuit and digital signal processing techniques to tackle well the aforementioned noise for much accurate touch sensing. The readout consists essentially of an analog front-end switched capacitor charge amplifier (SCCA), a 12-bit SAR ADC and a digital signal processing (DSP) unit for calibration and filtering. A field-programmable gate array (FPGA) board is adopted to implement the designed digital signal processing in practice. The performance of the readout is tested for a 5 × 12, 0.88-inch IAMC touch panel with a scanning frequency of 200 Hz. Experimental data show clearly that the sensed capacitance was successfully converted to 200 digits in a full dynamic range of 12-bits and a SNR of 52 dB, which facilitates well accurate determination of touches and locations on an IAMC touch panel.

This paper is concerned with the experimental characterization of a charge sensitive amplifier featuring dynamic signal compression, fast recovery time, low noise, and reduced area occupancy. The device takes the advantage of the nonlinear characteristic of a feedback transistor that behaves like a voltage-controlled capacitance. This property has been exploited to fit a wide input dynamic range into the available output swing. The charge amplifier can be operated in synchronous mode at high frame rates, of the order of few megahertz, thanks to a wide bandwidth, an improved output stage, and a fast reset network. Thanks to the small area occupancy, the amplifier is suitable for integration in a $100\times 100\,\,\mu \text {m}^{2}$ pixel area. All these features make the device a good candidate for applications where a fast front end with a nonlinear response is required, such as in imaging instrumentation for free electron laser experiments. The aim of this paper is to present and discuss the experimental results coming from the characterization of the first prototype of the circuit, which has been designed in a 65-nm CMOS technology. This paper has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare, Italy.

In this paper, we have proposed an input interfacing scheme with differential output for integrated capacitive sensor applications. In the proposed scheme, the front-end interfacing is based on switched capacitor charge amplifier configuration using a fully differential operational transconductance amplifier and one differential capacitive sensor arrangement which provides differential output with minimum number of circuit components. In the back end, a sigma–delta ( $\Sigma \Delta $ ) modulator is integrated for modulated digital output. The signal conditioning circuit also includes gain programmability by selecting proper feedback capacitor and mismatch cancellation between the sensing capacitors through on-chip capacitors array. The complete application specific integrated circuit (ASIC) is designed and fabricated in United Microelectronics Corporation (UMC) $0.18-\mu \text{m}$ CMOS process technology. The fabricated ASIC is then integrated with a silicon-on-insulator microelectromechnical systems capacitive accelerometer to test and characterize the performance of the proposed scheme. The measured result shows that the sensitivity of the proposed circuit can be varied from 200 to 900 mV/g by changing the feedback capacitor. The integrated system is also tested with electrostatic actuation as well as with a vibrating shaker and the measurement results are presented.

An improved topology for the baseband super-regenerative sampling amplifier is proposed and analyzed, which employs a series-capacitors output load to realize positive feedback. As in the conventional circuit, the gain of the amplifier is continuously variable by controlling the length of the capacitor charging phase. It is shown that decreasing feedback enhances the linearity of the circuit while trading off with a lower sampling speed. Entirely removing the feedback yields the integrating amplifier circuit. This is a practical implementation in terms of linearity, power, noise, and gain in low-frequency applications, including biomedical signal amplification. The analysis is verified by measured results from an integrated circuit prototype in 180-nm CMOS technology.

Integrators are an important functional module of several filters, PID controllers and automated systems. Designing these integrators in fractional domain enhance their operations and make the responses highly precise and accurate. This paper presents a Fractional Order Current Integrator using second generation current conveyor as the active block, and fractional capacitor as a grounded fractance. Analog realization of this fractance comprises of resistances and capacitances arranged in parallel RC ladder topology. The motivation behind this work is that more accurate and stable fractional integrator with fewer passive elements, for lower bias voltage and high dynamic range, can be designed and implemented. Integrators of fractional orders from 0.1 to 0.9 are simulated using TSMC 0.25 µm technology parameters. The transient and frequency responses obtained in Mentor Graphics are in close conformity with the theoretical values of magnitude and phase. Robustness of the proposed model is verified by performing Monte Carlo analysis in time and in frequency domain. Comparisons of fractional order current integrators with existing analog fractance models have also been included to further validate the work presented in the paper.

In this paper, a new tomography technique called electrical charge tomography for two-phase flow imaging is presented. The probe consists of few pair of electrodes which are electrically energized to generate electrical charges within the fluid under test. The intensity of these charges depends on the chemical and physical properties of the fluid, as well as to its molecular distribution. Another group of electrodes surrounding the cross section of the fluid under test are used to capture the induced electrical charges. These are then converted into an electrical signal using a high sensitive charge amplifier. A postprocessing unit which consists of an analog to digital converter, followed by an field programmable gate array (FPGA) module is then used for high level signal processing (i.e., a dedicated dynamic thresholding algorithm) and image reconstruction. Experimental results demonstrate the capability of the system to accurately generate 2-D cross-sectional images, where the error is lower by up to 14% when using another electrical capacitance (ECT) tomography probe. The other advantage of this technique over ECT is the reduced data acquisition time, since in ECT a minimum time is required for the charge and discharge of the capacitance in order to achieve acceptable accuracy. This makes the probe another attractive concept for future tomography systems targeting real-time applications.

This article provides insight into the development of a powerful and low-cost chopper amplifier for piezoelectric pressure sensors and shows its possible applications for injection moulding machines. With a power supply of 3.3 volts and the use of standard components, a circuit is introduced which can be connected to a commercially available microcontroller without any additional effort. This amplifier is specialised for low frequencies and high-pressure environments. With the adjustment of the sample and chopper frequency by means of software, the amplifier can easily be adapted for other applications. This chopper amplifier is a very compact and cost-effective solution with a small number of required components. In this contribution, it will be shown that the amplifier has good results in various laboratory tests as well as in the production process. Furthermore, an approach to fuse data from force and pressure signals by using a Kalman filter will be presented. With this method, the quality of the sensor signals can be significantly improved. This article is an extension of our previous work in Schneider et al. (2016b).

In this work, we propose a method to increase the parasitic input resistance caused by application of chopper modulation to indirect current feedback instrumentation amplifiers. The result is obtained by applying dynamic element matching to the input and feedback ports at the same frequency as chopper modulation. The proposed approach requires effective offset ripple rejection and equalization of the input and feedback common mode voltages. An in-amp architecture that meets both requirements and embodies the proposed input resistance boosting method is described. Experimental verification is provided by means of a prototype designed and fabricated using the $0.32~\mu \text {m}$ CMOS devices of the STMicroelectronics BCD6s process. The amplifier operates with a 3.3 V supply voltage and a total current absorption of $170~\mu \text {A}$ . An input impedance in excess of $1~\text {G}\Omega $ has been measured at a chopper frequency of 20 kHz. The input referred voltage noise density is 18 nV/sqrt(Hz) with a flicker corner of 0.2 Hz and 200 Hz bandwidth.

This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time-interleaved integrating-type optical receiver, it provides 1:2 demultiplexing operation with a tolerance to lower bandwidth photodiodes. The bandwidth of current amplifier is chosen as $0.35\times $ operating data rate for maximizing the receiver signal-to-noise ratio. Experimental results show that the receiver can achieve 25 Gb/s operation when integrated with a 9 or 17 GHz GaAs photodiode. Input sensitivities in the two cases are -7.2 dBm (w/i a 9 GHz photodiode) and -10.8 dBm (w/i a 17 GHz photodiode), respectively, for a bit error rate of less than $10^{-12}$ . In addition, a single-tap decision-feedback equalizer (DFE) is embedded to compensate photodiode bandwidth and improve input sensitivity. Integrated with a low-cost 9 GHz photodiode, the input sensitivity and timing margin of the receiver are improved by 2 dB and 0.25 UI, respectively, after DFE compensation. By utilizing a current integrator and time-interleaved comparators, its energy efficiency is 1.13 pJ/b at 25 Gb/s under a 1.2 V power supply. Fabricated in a 40 nm bulk-CMOS technology, the core circuit occupies a chip area of 0.007 mm 2 only.

This paper presents an alternative implementation of a chopper-modulated current-mode instrumentation amplifier. The structure provides very low-offset voltage at the output due to chopper modulation and residual offset removal path. The residual offset removal path is based on low-pass filtering using grounded capacitances which provides compact design structure compared to various chopper-modulated instrumentation amplifier designs. Rail-to-rail input common-mode range is possible due to transmission gate-based input chopper switching scheme. The design is made using a 0.35-µm CMOS process with ±1.65 V supply voltage. The area of the amplifier is 234µm × 344 µm, including all the filtering elements. The proposed circuit with residual offset removal path provides less than 1 µV input referred offset voltage. The advantage of the proposed instrumentation amplifier is its large bandwidth, simple design scheme and compact area compared to chopper-modulated voltage mode amplifiers.

In this paper, we investigate the responsivities and output voltage noise power spectral densities of magnetoelectric (ME) laminate sensors, consisting of length magnetized Terfenol-D alloys and transverse/width poled Pb(Mg 1/3 Nb 2/3 )O 3 -PbTiO 3 (PMNT) crystals (i.e. L-T mode and L-W mode respectively), which are directly integrated with custom-build low noise charge amplifier circuits. Both the theoretical analyses and experimental results prove that the L-W mode sensor with the optimized polarized direction of the PMNT plate possesses lower magnetic detection limit at the interested high frequency range of 10 kHz≤ f ≤50 kHz. The equivalent magnetic noise ( EMN ) of the L-W mode sensor is 0.78 pT/Hz 1/2 at 30 kHz, which is about 1.7 times lower than the 1.35 pT/Hz 1/2 for conventional L-T mode sensor. Furthermore, an effective method of using operational amplifiers with low equivalent input noise voltage and employing ME laminate composites with high voltage coefficient to reduce the EMN s of the ME laminate sensors at high frequency range has been established.

We have considered results of SiPM analog interface schematic design on array chip MH2XA030. The SiPM includes current buffer, current integrator and base level recovery (BLR) circuit. We have described analog interface operation for this type of sensor in details, specified electrical circuit and computer simulation results.

This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (&Sigma, &Delta, ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 &mu, m complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm2. Experimental results show a bias instability of 2.2 &deg, /h and a nonlinearity of 0.016% over the full-scale range.

Hybrid System-in-Foil (HySiF) is one of the emerging branches of flexible electronics in which ultra-thin silicon chips are integrated with flexible sensors in polymeric foils (Elsobky et al., 2018; Alavi et al., 2018). Intensive attention was given to the implementation of flexible environmental sensing platforms for logistics and food packaging (Cartasegna et al., 2011; Liu et al., 2016). The aim of this work is the implementation of a sensor system demonstrator using HySiF components, namely an ultra-thin microcontroller chip in addition to an on-chip temperature and an on-foil humidity sensors. The measurement concept for the relative humidity sensor is measuring the capacitance difference between an off-chip (on the foil substrate) humidity dependent sensor capacitor, and another humidity independent reference capacitor. The electrical readout technique is based on the charge amplifier switched capacitor circuit. It is implemented using a commercially available microcontroller (EM microelectronics EM6819) which has the advantage of being available as single chips to enable post-processing steps such as backthining and chip embedding in a thin polymer package. Sensor and reference capacitors are homogeneously integrated on-foil. 400 and 30 µm thick microcontroller dies (MCU) are used in this application. The charge amplifier result is digitized using an internal 10-bit analog-to-digital converter (ADC). The 10-bit ADC is time multiplexed between the charge amplifier structure and the internal temperature sensor. Linear interpolation is used to fit the digital output of the ADC and calibrate the output of the sensor system. Readings of the humidity level and the temperature are written to an NFC tag (from the company EM microelectronics based on chip EM NF4) using the contact interface. Readings can be accessed using a customized android application on a smartphone.

This paper proposes an interface electronic circuit for capacitive sensors using a phase-based measurement technique. Novel scheme for compensating the variable offset capacitance of the sensor has been derived. This method can also be easily adapted to provide a direct digital readout, eliminating the need for high-resolution ADC. The proposed methodology is derived and analyzed for various non-idealities of the circuit elements. Simulation studies are used to prove that the output-phase varied from 45° to 135° (as expected) for different offset capacitances of the sensor. Further experimental studies are carried out with standard capacitors as well as variable-area based capacitive sensor module, and the performance is validated.

This paper presents a low offset, differential output, switched capacitor based capacitive sensor interfacing circuit. The interfacing circuit senses the physical signal as a change in capacitance from a differential capacitive sensor and generates a differential output voltage. Chopper modulation, charge amplification, and auto-zeroing techniques are applied to the proposed circuit to minimize the effect of offset and low-frequency noise introduced by the circuit components. The interfacing circuit contains a fully differential operational amplifier, offset reduction scheme, buffer and low pass filter. The main advantage of the interfacing circuit is utilizing a single differential capacitive sensor and a single feedback network with minimum circuit components. The gain of the interfacing circuit is programmable through the feedback capacitor of the charge amplifier configuration. The interfacing circuit is designed using SCL 0.18 µm CMOS process technology and simulated using spectre simulator. The simulation results with and without offset reduction scheme are presented to show how effectively the proposed circuit is reducing the effect of offset and low-frequency noise.

International audience; We investigate the development of a sensor for dynamic pressure measurement. The sensor relies on a Bauer shock gauge of 25-μm thin Polyvinylidene fluoride (PVDF) film [AIP Conf. Proc 706:1121–1124, [21]. These gauges unfortunately require some skills to be integrated in an acquisition chain and the obtained results are strongly “experiment dependent.” In the presented work, the classical Bauer gauge has been adapted: the reproducible PVDF film is poled at high voltage, in electrical symmetrical response and reproducibility. The sensitive area is a 3 × 3 mm square. The gauge has been electrically shielded and overlaid with a heat conductive material. A 5-m long coaxial wire connects the gauge to a charge amplifier, allowing its connection to a deported oscilloscope. The output electrical charge of the PVDF gauge has been correlated with the pressure measured by calibrated PCB® sensors. Measured pressures are validated by an analytical approach and numerical simulations of the flow in the shock tube. A calibration curve can be deduced for pressures below 10 bar, values which are often met in blast loading situations. This customizable sensor is hence suitable and easy to use to measure the blast-reflected pressure on a flat material.

This paper explores the modeling and design of Miller-based operational amplifier structures that are highly immune to electromagnetic interference (EMI). The proposed CMOS Miller-based operational amplifier is derived using the present modeling. It provides higher immunity to EMI that is injected into the amplifier's input over a wide range of frequencies; moreover, the frequency response is comparable to that of a Miller operational amplifier. Simulation results show that the maximum EMI-induced input offset voltage for the proposed CMOS operational amplifier is 5 mV at an EMI frequency of 40 MHz, when a 900 mVpp EMI signal is applied at its input. In contrast, the standard Miller operational amplifier generates an input offset voltage of 32 mV under the same operating conditions. The developed mathematical modeling of the EMI-induced offset correlates with the circuit simulations, providing superior accuracy when designing for high EMI robustness.

An analog front-end (AFE) for a multifunction environmental sensor is proposed. The AFE is designed to be able to sense $1~\mu \text {V}$ , 1 fC, and 1 pA level signals in a low-frequency band around DC, and consists of an instrumentation amplifier (IA), a charge amplifier (CA), and a continuous time delta-sigma (CT- $\Delta \Sigma $ ) ADC. To reduce the low-frequency noise of operational amplifier (OPAMP) which is used for signal path, this paper proposes a weak-inversion biasing technique. The designed IA achieved 26 nVrms input-referred noise (IRN) in the band of 0.1–10 Hz with 0.22 mm2 die area. The designed CA achieved 25 aCrms IRN in charge sensing mode and 19 fArms IRN in current sensing mode in the band of 0.01–1 Hz, respectively, and occupies 0.12 mm2 die area. The AFE has been fabricated in a $0.18~\mu \text {m}$ CMOS process with 4.5 mm2 die area. The current consumption at 2.56 kHz output data rate (ODR) is 2.5 mA, reducing to $2~\mu \text {A}$ at 0.01 Hz ODR.

As electrolytic capacitor is apt to fail in power converters, it is very important to monitor its electrical parameters, mainly the equivalent series resistance (ESR) and capacitance (C). A novel non-invasive online monitoring method of DC-link capacitor's ESR and C for boost power factor correction (PFC) converter is proposed in this paper. By analyzing the capacitor voltage ripple which is composed of that of ESR and C, the calculation model is founded, which shows that instead of additional current sensor, only two values of capacitor voltage in particular moments within a line cycle need to be sampled for the calculation of ESR and C. The schematic of the monitoring system together with the design considerations of the trigger circuit, the isolated voltage amplifier, the isolated current amplifier are described in detail. The experimental results show the effectiveness of the method.

A current subtraction technique with parallel operation system is proposed to remove excessive current in touch screen application. The proposed current subtraction remove the current which go into the input node of charge amplifier. The value of subtraction current is same with current when touch screen is not touched. As a result, charge amplifier output is only proportional to variation of mutual capacitor, which make dynamic rage is increased. Also, Transmitter (Tx) driving signal and subtraction driving signal are out of phase each other. Thus, noise generated in Tx is cancelled. The proposed IC is implemented in a mixed-mode 0.18-um CMOS process. Overall system is designed for touch screen panel (TSP) with 16 driving lines and 8 sensing lines. 5-V supply voltages are used in the proposed circuits. For multiple Tx driving signal, Walsh codes are used and signal frequency is 300 khz. By using proposed technique, dynamic rage is improved 36 dB.

A novel frequency compensation technique, named Regular Miller plus Reversed Indirect Compensation (RMRIC), is presented in this paper for fast-settling three-stage amplifiers. The RMRIC topology includes, on the one hand, a Miller capacitor combined with one nulling resistor connected between the first stage and the third stage, and on the other hand, an indirect compensation capacitor in series with a resistor added between the first and the second stage, which improves remarkably the performance such as gain---bandwidth product (GBW) and sensitivity of the proposed amplifier. Detailed design considerations are carried out to demonstrate the stability of the compensation technique. Circuit simulation results show the amplifier driving a 2-pF load capacitance achieves a 9.25-GHz GBW dissipating only 16.5 mW with a 1.2 V supply voltage using a TSMC 65 nm CMOS technology, which shows a significant improvement in figure of merits. The implemented amplifier reaches a settling time of 3.35 ns with 0.006 % accuracy.

A new current feedback amplifier is proposed which is suitable for high gain and constant bandwidth applications. This new topology is employing a inverter based positive current conveyor followed by an amplifier to achieve high gain and a constant bandwidth. The inverter based current conveyor has no on –chip capacitors so it will reduce the cost of chip fabrication The proposed Design is simulated in 180nm technology in cadence kit.

This paper describes a self-compensating system for fixed pattern noise reduction (FPNR) of focal plane arrays (FPA) of infrared (IR) bolometer detectors. The proposed system used a ΔΣ modulator of first order which operates as non-saturating current integrator. The method also suppressed the self-heating effect as well as the effect of resistance non-uniformity across the FPA. The read-out circuit (ROIC) was designed in ONSemi I2T100 technology considering the matching and noise effects and fabricated using EUROPRACTICE service. Its verification was made on the test printed circuit board (PCB) with the variable resistors. These resistors were changed to emulate the real bolometer behavior due to IR radiation.

This paper presents a novel ${z}$ -axis Lorentz force magnetometer coupled with a low-power readout integrated circuit. The sensor is fabricated using an industrial process, and exploits an Al-on-polysilicon multi-loop architecture that gives a five-fold sensitivity and resolution improvement, useful for off-resonance operation. The integrated readout is based on a differential charge amplifier front-end, and designed to be balanced with the sensor in terms of noise and power consumption. The overall system, including demodulation and filtering stages, shows a programmable full-scale up to ±2.4 mT, limited by the electronics saturation. The bandwidth can be programmed up to 150 Hz for off-resonance operation where a sub-400-nT/ $\sqrt {\text {Hz}}$ resolution at 775- $\mu \text{W}$ power consumption is obtained, including the integrated readout and the Lorentz current. Perspectives on low-consumption driving oscillators for off-resonance mode are finally given. [2015-0139]

We define the virtual infinite capacitor (VIC) as a nonlinear capacitor that has the property that for an interval of the charge Q (the operating range), the voltage V remains constant. We propose a lossless approximate realization for the VIC using a switched power converter and capacitors. This circuit is simple but it requires a complex control algorithm that we describe. There are two controllers needed to operate a VIC: the voltage controller acts fast to maintain the desired terminal voltage, while the charge controller acts more slowly and maintains the charge Q in the desired operating range by influencing the incoming current. The VIC is useful as a filter capacitor for various applications, for example power factor compensators (PFC), as we describe. In spite of using small capacitors, the VIC can replace a very large capacitor in applications that do not require substantial energy storage. We give simulation results for a PFC working in critical conduction mode with a VIC for output voltage filtering.

Area-changed capacitive displacement transducers have been widely applied in micro-electro-mechanical-system (MEMS) sensors such as sandwich-type MEMS accelerometers to detect in-plane displacement with a high sensitivity. The cross-axis disturbance could result in out-of-plane displacement of the proof mass, which brings a gap variation of sensing capacitor electrodes and lead to an undesirable variation of the accelerometer’s scale factor. In order to solve this problem, this paper presents a novel method to improve out-of-plane robustness of an Area-changed capacitive displacement transducer in a MEMS accelerometer. An on-chip capacitor, sensitive to the out-of-plane displacement of proof mass, was integrated as the feedback capacitor of the charge amplifier. Thus, the influence of the out-of-plane displacement on the scale factor caused by cross-axis disturbance is compensated. The method was verified by theoretical calculation, simulation and experiments. The results indicated that the cross-sensitivity of the MEMS accelerometer with an on-chip feedback capacitor was less than 1/3 of that with off-chip feedback capacitor when acceleration was applied on the out-of-plane direction. Besides, the noise floor of the accelerometer maintained at 60 ng/√Hz regardless of the on-chip or off-chip feedback capacitors.

In this paper, we propose a nano-ampere current sensing technique for organic light-emitting diode (OLED) mobile displays. The nano-ampere current sensing system consists of a current integrator and an 8-bit single-slop analog to digital converter (SS-ADC). In order to reduce area and power consumption, the current integrator and a comparator of the SS-ADC share an amplifier, called differential difference amplifier (DDA). From the experimental results, we obtain 399.21 pA of accuracy with 8-bit current sensing resolution ranged from 0 to 102.2 nA. The proposed current sensing circuit was fabricated with a 90 nm CMOS technology and chip size is about 600 μm × 3000 μm.

This paper presents a switched capacitor based capacitive sensor interfacing circuit, which can sense the change in capacitance from differential capacitive sensor and produces differential voltage output. The proposed circuit has the ability to reduce the errors like offset and low frequency noise introduced by the circuit components. The main advantage of this interfacing circuit is, it utilizes a single differential capacitive sensor and a single feedback network to provide differential output. The gain of the interfacing circuit is programmable through the feedback capacitor of the charge amplifier configuration. The interfacing circuit comprises of a fully differential operational amplifier, offset reduction scheme, buffer and low pass filter. The proposed circuit is designed and simulated using UMC 0.18-μm CMOS process technology. Both schematic and post-layout simulation results are presented.

This paper presents an implementation of Current Integrator for fractional orders (n/3). The circuit uses second-generation current conveyor (CCII) as the active element along with the passive elements based fractional-order element (FOE). The resistors and capacitors of FOE are in geometric progression and are arranged as RC ladder. The functionality of the fractional integrator has been verified for n, viz. n = {0.75, 1.0, 1.5, 2.0 and 2.25}. The simulations results have been obtained in PSPICE using 0.25 µm CMOS technology parameters.

This paper presents a catheter-based capacitive force sensor interface for cardiovascular diagnosis. The force sensor is implemented on a flexible printed circuit board (FPCB) substrate with a force-sensitive polydimethylsiloxane (PDMS), and a force-induced change in a capacitance of the sensor is measured by a precision capacitive sensor interface. To recover the performance degradation caused by the large parasitic capacitance ${\rm C}_{\rm P}$ of a long catheter, we present a parasitic insensitive analog front-end (AFE) with active ${\rm C}_{\rm P}$ cancellation, which employs a charge amplifier and a negative capacitor at the virtual ground of the charge amplifier. The prototype sensor was measured with a force loader in whole blood. The proposed AFE successfully cancels ${\rm C}_{\rm P}$ of 348 pF in a 0.9-m-long sensor and measurement results show the SNR of 53.8 dB and the capacitance resolution of 16 aF, a 19.6 dB improvement by canceling nonideal effect of ${\rm C}_{\rm P}$ . This corresponds to a force resolution of 2.22 gf, which is 9.29 $\times$ reduction compared to the work without the ${\rm C}_{\rm P}$ cancellation. The proposed sensor interface is insensitive to ${\rm C}_{\rm P}$ from hundreds to 1-nF level, and the force-dependent stiffness of two different tissues has been successfully distinguished with an ex-vivo experiment. The proposed sensor interface enables the integration of capacitive force sensors in a smart catheter.

This paper proposes an accurate tunable-gain 1/x circuit. The output voltage of the 1/x circuit is generated by using a capacitor-charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/x circuit is tuned by an 10-bit digital code. The 1/x circuit was fabricated using a 0.1 8μm CMOS process . Its core area is 0.011m m 2 (144μm×78μm) and it consumes 278μW at VDD=1.8V and fCLK=1MHz. Its error is within 1. 7% at VIN=0.05~1V.

A wide input range, compliant with electrochemical amperometric and voltammetric sensors analog-front-end (AFE) integrated circuit (IC) is proposed. The AFE employs current integrator (CI) and trans-impedance amplifier (TIA) to deal with the input current in the order of nA and µA separately, achieving the advantage of high dynamic range and high resolution. Input voltage is converted to current through a series of precise resistances, and detected by CI or TIA, which making the input voltage range is not limited by the power supply. An incremental sigma-delta ADC is employed to digitize the transferring signal, reducing the complexity and power dissipation. Compared to other alternatives, the AFE could handle current and voltage signals simultaneously, and input voltage range is not limited by power supply, showing high dynamic range and resolution. The AFE IC is fabricated in 0.18µm 1P5M mixed-signal CMOS process, occupies an area of 3.2mmi?2mm, the readout circuit has a dynamic range of 120dB, consumes 4.2mA. The AFE IC present in this manuscript employs dual-path, current integrator (CI) and trans-impedance amplifier (TIA), to deal with the input current in the order of nA and µA separately, achieving the advantage of high dynamic range and high resolution.The AFE IC can be compliant with both electrochemical amperometric and voltammetric sensors, instead of traditional instrument amplifier, a voltage-to-current circuit is adopted to convert an input voltage to a current, making the input voltage range is not limited by the power supply.Instead of a traditional sigma-delta ADC, a incremental sigma-delta ADC is employed to digitize the transferring signal, reducing the complexity and power dissipation, providing the feature of one-to-one mapping between input and output.

This study presents a reduced state feedback sliding-mode current controller (RSFSMCC) for a voltage source inverter (VSI)-based higher-order circuit. The proposed controller consists of an inner current loop and an outer voltage loop. The reference for the inner input inverter current is generated from the outer voltage loop through a proportional plus integral controller. The stability of the system is ensured by using feedback of only two state variables, that is, input inverter current and output capacitor voltage of the VSI circuit. A reduced state feedback analysis is used to obtain the gain matrix for the higher-order circuit. The tracking control convergence criterion of the system is examined through the eigen values of the resultant state matrix derived for the VSI circuit. The frequency response plot shows that the proposed RSFSMCC is robust with good stability margins. The simulation results show that the output voltage well tracks the reference voltage with reduced steady-state error for both linear and non-linear loads. The simulation results obtained in power systems CAD/electromagnetic transients including DC (PSCAD/EMTDC) v4.2.1 software are verified through the experimental results conducted on a single-phase VSI circuit using field programmable gate array implementation of the RSFSMCC.

A linear front-end electronic system based on a high-speed charge sensitive amplifier and a tunable shaping amplifier suitable for silicon detectors has been presented. The designed charge sensitive amplifier features simplicity and compactness. It is based on the combination of a low-noise field-effect transistor input device and a current feedback opamp ensuring high frequency and small rise time. The circuit provides both an energy signal and a timing signal. The shaping amplifier is a fifth-order complex filter based on an opamp- RC topology providing a nearly Gaussian response. The shaper also includes a pole-zero cancellation circuit and a base line restorer to preclude the pileup of subsequent input signals. A control system has been developed to adjust the main parameters of the channel. The designed readout channel has been optimized for a medium energy range up to 50 MeV coupled to silicon detectors up to 100 pF. Its feasibility for nuclear physics applications has been experimentally validated.

The paper presents the radiation test results of a readout ASIC (CASCA: Charge Amplifier with Switched Capacitor Array) for a Time Projection Chamber (TPC). The CASCA integrated 32 channels with full signal processing circuits and was fabricated in 0.18 $\mu {\mathrm{ m}}$ CMOS process. Both Total Ionizing Dose effect (TID), including static TID and dynamic TID and Single Event Effects (SEE) tests, which mainly focus on Single Event Latch-up (SEL), Single Event Upset (SEU) and Single Event Transient (SET) of CASCA were taken. The tests were taken with 200MeV and 62.8MeV protons. The radiation test setup and test results were given and discussed.

Due to its excellent dynamic performance for vibration measurement, MEMS-based piezoelectric accelerometer has been studied in recent years. Piezoelectric micro-accelerometer can be regarded as a component that can produce electric charge with high internal impedance, but the quantity of electric charge is very subtle. By taking this into account, the general measuring circuit does not meet the requirement. In this paper, a charge amplifier with an integrated chip is used instead of a large number of discrete components, and cold-discharge design is also included to decrease the thermal noise of the whole circuit.

This paper presents the modeling and design of a source-buffered Miller operational amplifier structure that is highly immune to electromagnetic interference (EMI). The source-buffered Miller operational amplifier is designed and fabricated in the 0.18 μm mixed-mode CMOS process and modeled mathematically including the body effect and channel length modulation. Measurement results show that the maximum EMI-induced input offset voltage for the source-buffered Miller operational amplifier is 22 mV at 1 GHz, when a 900 mVpp EMI signal is applied at its input. In contrast, the standard Miller operational amplifier generates an input offset voltage of 215 mV under the same operating conditions.