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Integrating two-dimensional (2D) materials into semiconductor manufacturing lines is essential to exploit their material properties in a wide range of application areas. However, current approaches are not compatible with high-volume manufacturing on wafer level. Here, we report a generic methodology for large-area integration of 2D materials by adhesive wafer bonding. Our approach avoids manual handling and uses equipment, processes, and materials that are readily available in large-scale semiconductor manufacturing lines. We demonstrate the transfer of CVD graphene from copper foils (100-mm diameter) and molybdenum disulfide (MoS2) from SiO2/Si chips (centimeter-sized) to silicon wafers (100-mm diameter). Furthermore, we stack graphene with CVD hexagonal boron nitride and MoS2 layers to heterostructures, and fabricate encapsulated field-effect graphene devices, with high carrier mobilities of up to \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$4520\;{\mathrm{cm}}^2{\mathrm{V}}^{ - 1}{\mathrm{s}}^{ - 1}$$\end{document}4520cm2V−1s−1. Thus, our approach is suited for backend of the line integration of 2D materials on top of integrated circuits, with potential to accelerate progress in electronics, photonics, and sensing., The existing integration approaches for 2D materials often degrade material properties and are not compatible with industrial processing. Here, the authors devise an adhesive wafer bonding strategy to transfer and stack monolayers, suitable for back end of the line integration of 2D materials.

The integration of 2D materials for photonic applications is not compatible with high-volume manufacturing. We report a generic methodology that uses only readily available semiconductor equipment and experimentally demonstrate the stacking of graphene and molybdenum disulfide (MoS2). Part of proceedings: ISBN 978-1-943580-91-0, QC 20230117

We report the integration of graphene/hexagonal boron nitride (hBN) heterostructure devices on large-areas by adhesive wafer bonding, a method suitable for industrial mass-production. In this new approach, we stack graphene and hBN by two consecutive bond transfers whereby the graphene and its interface to hBN is not in contact with potentially contaminating polymers or adhesives at any time. To show the feasibility of our approach for back end of the line (BEOL) integration of two-dimensional (2D) material heterostructures on standard silicon substrates, we fabricated graphene/hBN devices with electrical bottom contacts using only established semiconductor manufacturing tools, processes and materials. QC 20200611

Graphene is an extremely promising material for emerging nanoelectromechanical systems (NEMS) and sensors, but the transfer from its growth substrate to silicon substrates remains manual and laborious. We report a novel method for the transfer of large-area chemical vapor deposited (CVD) graphene from copper foil to a target wafer by adhesive wafer bonding using bisbenzocyclobutene (BCB) as an intermediate adhesive layer. The use of conventional wafer bonding equipment enables the scalable transfer of graphene and the realization of both supported and suspended graphene devices on wafer-scale. Our method circumvents manual handling of graphene after release from its growth substrate and avoids polymeric carrier layers, a well-known source of contamination. Hence, the proposed process promises the transfer of graphene with high quality and repeatability.

The electrical contact resistance at metal-graphene interfaces can significantly degrade the properties of graphene devices and is currently hindering the full exploitation of graphene's potential. Therefore, the influence of environmental factors, such as humidity, on the metal-graphene contact resistance is of interest for all graphene devices that operate without hermetic packaging. We experimentally studied the influence of humidity on bottom-contacted chemical-vapor-deposited (CVD) graphene-gold contacts, by extracting the contact resistance from transmission line model (TLM) test structures. Our results indicate that the contact resistance is not significantly affected by changes in relative humidity (RH). This behavior is in contrast to the measured humidity sensitivity (0.059 +/- 0.011 %/% RH) of graphene's sheet resistance. In addition, we employ density functional theory (DFT) simulations to support our experimental observations. Our DFT simulation results demonstrate that the electronic structure of the graphene sheet on top of silica is much more sensitive to adsorbed water molecules than the charge density at the interface between gold and graphene. Thus, we predict no degradation of device performance by alterations in contact resistance when such contacts are exposed to humidity. This knowledge underlines that bottom-contacting of graphene is a viable approach for a variety of graphene devices and the back end of the line integration on top of conventional integrated circuits.

There is an urgent need to fulfill future energy demands for micro and nanoelectronics. This work outlines a number of important design features for carbon-based microsupercapacitors, which enhance both their performance and integration potential and are critical for complimentary metal oxide semiconductor (CMOS) compatibility. Based on these design features, we present CMOS-compatible, graphene-based microsupercapacitors that can be integrated at the back end of the line of the integrated circuit fabrication. Electrode materials and their interfaces play a crucial role for the device characteristics. As such, different carbon-based materials are discussed and the importance of careful design of current collector/electrode interfaces is emphasized. Electrode adhesion is an important factor to improve device performance and uniformity. Additionally, doping of the electrodes can greatly improve the energy density of the devices. As microsupercapacitors are engineered for targeted applications, device scaling is critically important, and we present the first steps toward general scaling trends. Last, we outline a potential future integration scheme for a complete microsystem on a chip, containing sensors, logic, power generation, power management, and power storage. Such a system would be self-powering.